OpenCores
URL https://opencores.org/ocsvn/astron_sim_tools/astron_sim_tools/trunk

Subversion Repositories astron_sim_tools

[/] [astron_sim_tools/] [trunk/] [dp_wideband_wb_arr_scope.vhd] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 danv
-------------------------------------------------------------------------------
2
--
3 3 danv
-- Copyright 2020
4 2 danv
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
5
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
6 3 danv
-- 
7
-- Licensed under the Apache License, Version 2.0 (the "License");
8
-- you may not use this file except in compliance with the License.
9
-- You may obtain a copy of the License at
10
-- 
11
--     http://www.apache.org/licenses/LICENSE-2.0
12
-- 
13
-- Unless required by applicable law or agreed to in writing, software
14
-- distributed under the License is distributed on an "AS IS" BASIS,
15
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16
-- See the License for the specific language governing permissions and
17
-- limitations under the License.
18 2 danv
--
19
-------------------------------------------------------------------------------
20
 
21
-- Purpose: Scope component to show the arrayed DP SOSI data at the SCLK
22
--          sample rate
23
-- Description:
24
--   The SCLK rate is g_wideband_factor faster than the DCLK rate. The input
25
--   is one wideband stream that is carried by an array of g_wideband_factor
26
--   sosi streams at the DCLK rate. The output is a single sosi integer stream
27
--   at the SCLK rate.
28
-- Remark:
29
-- . Only for simulation.
30
-- . When g_use_sclk=TRUE then the input SCLK is used. Else the SCLK is derived
31
--   from the DCLK so that it does not have to be applied via an input. This
32
--   eases the use of this scope within a design.
33
-- . In this dp_wideband_wb_arr_scope the input is only one wideband stream
34
--   and the input sosi array has size g_wideband_factor, so the wideband
35
--   data is carried via the sosi array dimension.
36
--   In dp_wideband_sp_arr_scope the input is one or more wideband streams
37
--   and the input sosi array has size g_nof_streams, so there the wideband
38
--   data is carried by g_wideband_factor concatenated symbols in the data
39
--   field or in the (re, im) fields.
40
 
41
 
42
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib;
43
USE IEEE.STD_LOGIC_1164.ALL;
44
USE common_pkg_lib.common_pkg.ALL;
45
USE dp_pkg_lib.dp_stream_pkg.ALL;
46
 
47
ENTITY dp_wideband_wb_arr_scope IS
48
  GENERIC (
49
    g_sim                 : BOOLEAN := FALSE;
50
    g_use_sclk            : BOOLEAN := TRUE;
51
    g_wideband_factor     : NATURAL := 4;        -- Wideband rate factor = 4 for dp_clk processing frequency is 200 MHz frequency and SCLK sample frequency Fs is 800 MHz
52
    g_wideband_big_endian : BOOLEAN := FALSE;    -- When true wb_sosi_arr[3:0] = sample[t0,t1,t2,t3], else when false : wb_sosi_arr[3:0] = sample[t3,t2,t1,t0]
53
    g_dat_w               : NATURAL := 8         -- Actual width of the data field or of the re field, im field
54
  );
55
  PORT (
56
    -- Digital processing clk
57
    DCLK         : IN STD_LOGIC := '0';
58
 
59
    -- Sampling clk, for simulation only
60
    SCLK         : IN STD_LOGIC := '0';   -- SCLK rate = g_wideband_factor * DCLK rate
61
 
62
    -- Streaming input samples for one stream
63
    wb_sosi_arr  : IN t_dp_sosi_arr(g_wideband_factor-1 DOWNTO 0);   -- = [3:0] = Signal Path time samples [t3,t2,t1,t0]
64
 
65
    -- Scope output samples for one stream
66
    scope_sosi   : OUT t_dp_sosi_integer
67
  );
68
END dp_wideband_wb_arr_scope;
69
 
70
 
71
ARCHITECTURE beh OF dp_wideband_wb_arr_scope IS
72
 
73
  SIGNAL SCLKi        : STD_LOGIC;  -- sampling clk, for simulation only
74
  SIGNAL sample_cnt   : NATURAL RANGE 0 TO g_wideband_factor-1 := 0;
75
  SIGNAL st_sosi      : t_dp_sosi;
76
 
77
BEGIN
78
 
79
  sim_only : IF g_sim=TRUE GENERATE
80
    use_sclk : IF g_use_sclk=TRUE GENERATE
81
      SCLKi <= SCLK;  -- no worry about the delta cycle delay from SCLK to SCLKi
82
    END GENERATE;
83
    gen_sclk : IF g_use_sclk=FALSE GENERATE
84
      proc_common_dclk_generate_sclk(g_wideband_factor, DCLK, SCLKi);
85
    END GENERATE;
86
 
87
    -- View wb_sosi_arr at the sample rate using st_sosi
88
    p_st_sosi : PROCESS(SCLKi)
89
    BEGIN
90
      IF rising_edge(SCLKi) THEN
91
        IF g_wideband_big_endian=TRUE THEN
92
          st_sosi <= wb_sosi_arr(g_wideband_factor-1-sample_cnt);
93
        ELSE
94
          st_sosi <= wb_sosi_arr(sample_cnt);
95
        END IF;
96
        sample_cnt <= 0;
97
        IF wb_sosi_arr(0).valid='1' AND sample_cnt < g_wideband_factor-1 THEN  -- all wb_sosi_arr().valid are the same, so use (0)
98
          sample_cnt <= sample_cnt + 1;
99
        END IF;
100
      END IF;
101
    END PROCESS;
102
 
103
    -- Map sosi to SLV of actual g_dat_w to allow observation in Wave Window in analogue format
104
    scope_sosi <= func_dp_stream_slv_to_integer(st_sosi, g_dat_w);
105
  END GENERATE;
106
 
107
END beh;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.