URL https://opencores.org/ocsvn/astron_sim_transceiver/astron_sim_transceiver/trunk

Subversion Repositories astron_sim_transceiver

[/] [astron_sim_transceiver/] [trunk/] [hdllib.cfg] - Blame information for rev 2

Details | Compare with Previous | View Log


hdl_lib_name = astron_sim_transceiver
hdl_library_clause_name = astron_sim_transceiver_lib
hdl_lib_uses_synth = common_pkg
hdl_lib_uses_sim =
hdl_lib_technology =
 
synth_files =
    sim_transceiver_serializer.vhd
    sim_transceiver_deserializer.vhd
 
test_bench_files =
    tb_sim_transceiver_serdes.vhd
 
regression_test_vhdl =
    tb_sim_transceiver_serdes.vhd
 
 
[modelsim_project_file]
 
 
[quartus_project_file]
 

Line No.	Rev	Author	Line
1	2	danv	`hdl_lib_name = astron_sim_transceiver`
2			`hdl_library_clause_name = astron_sim_transceiver_lib`
3			`hdl_lib_uses_synth = common_pkg`
4			`hdl_lib_uses_sim =`
5			`hdl_lib_technology =`
6
7			`synth_files =`
8			`sim_transceiver_serializer.vhd`
9			`sim_transceiver_deserializer.vhd`
10
11			`test_bench_files =`
12			`tb_sim_transceiver_serdes.vhd`
13
14			`regression_test_vhdl =`
15			`tb_sim_transceiver_serdes.vhd`
16
17
18			`[modelsim_project_file]`
19
20
21			`[quartus_project_file]`
22

Browse

Tools

Subversion Repositories astron_sim_transceiver

[/] [astron_sim_transceiver/] [trunk/] [hdllib.cfg] - Blame information for rev 2