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-------------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib, common_components_lib, astron_adder_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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-- Purpose:
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-- Accumulate input data to an accumulator that is stored externally. In this
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-- way blocks of input samples (e.g. subband products) can be accumulated to
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-- a set of external accumulators. At the in_load the accumulator input value
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-- is ignored so that the accumulation restarts with the in_dat.
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--
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-- Description:
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-- if in_load = '1' then
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-- out_acc = in_dat + 0 -- restart accumulation
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-- else
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-- out_acc = in_dat + in_acc -- accumulate
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--
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-- Remarks:
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-- . in_val propagates to out_val after the pipeline latency but does not
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-- affect the sum
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ENTITY st_acc IS
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GENERIC (
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g_dat_w : NATURAL;
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g_acc_w : NATURAL; -- g_acc_w >= g_dat_w
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g_hold_load : BOOLEAN := TRUE;
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g_pipeline_input : NATURAL; -- 0 no input registers, else register input after in_load
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g_pipeline_output : NATURAL -- pipeline for the adder
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);
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PORT (
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clk : IN STD_LOGIC;
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clken : IN STD_LOGIC := '1';
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in_load : IN STD_LOGIC;
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in_dat : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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in_acc : IN STD_LOGIC_VECTOR(g_acc_w-1 DOWNTO 0);
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in_val : IN STD_LOGIC := '1';
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out_acc : OUT STD_LOGIC_VECTOR(g_acc_w-1 DOWNTO 0);
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out_val : OUT STD_LOGIC
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);
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END st_acc;
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ARCHITECTURE rtl OF st_acc IS
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CONSTANT c_pipeline : NATURAL := g_pipeline_input + g_pipeline_output;
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-- Input signals
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SIGNAL hld_load : STD_LOGIC := '0';
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SIGNAL nxt_hld_load : STD_LOGIC;
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SIGNAL acc_clr : STD_LOGIC;
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SIGNAL reg_dat : STD_LOGIC_VECTOR(g_acc_w-1 DOWNTO 0) := (OTHERS=>'0');
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SIGNAL nxt_reg_dat : STD_LOGIC_VECTOR(g_acc_w-1 DOWNTO 0);
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SIGNAL reg_acc : STD_LOGIC_VECTOR(g_acc_w-1 DOWNTO 0) := (OTHERS=>'0');
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SIGNAL nxt_reg_acc : STD_LOGIC_VECTOR(g_acc_w-1 DOWNTO 0);
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-- Pipeline control signals, map to slv to be able to use common_pipeline
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SIGNAL in_val_slv : STD_LOGIC_VECTOR(0 DOWNTO 0);
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SIGNAL out_val_slv : STD_LOGIC_VECTOR(0 DOWNTO 0);
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BEGIN
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ASSERT NOT(g_acc_w < g_dat_w)
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REPORT "st_acc: output accumulator width must be >= input data width"
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SEVERITY FAILURE;
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------------------------------------------------------------------------------
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-- Input load control
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------------------------------------------------------------------------------
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p_clk : PROCESS(clk)
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BEGIN
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IF rising_edge(clk) THEN
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IF clken='1' THEN
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hld_load <= nxt_hld_load;
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END IF;
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END IF;
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END PROCESS;
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nxt_hld_load <= in_load WHEN in_val='1' ELSE hld_load;
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-- Hold in_load to save power by avoiding unneccessary out_acc toggling when in_val goes low
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-- . For g_pipeline_input>0 this is fine
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-- . For g_pipeline_input=0 this may cause difficulty in achieving timing closure for synthesis
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use_in_load : IF g_hold_load = FALSE GENERATE
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acc_clr <= in_load; -- the in_load may already be extended during in_val
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END GENERATE;
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use_hld_load : IF g_hold_load = TRUE GENERATE
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acc_clr <= in_load OR (hld_load AND NOT in_val);
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END GENERATE;
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-- Do not use g_pipeline_input of u_adder, to allow registered acc clear if g_pipeline_input=1
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nxt_reg_dat <= RESIZE_SVEC(in_dat, g_acc_w);
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nxt_reg_acc <= in_acc WHEN acc_clr='0' ELSE (OTHERS=>'0');
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no_input_reg : IF g_pipeline_input=0 GENERATE
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reg_dat <= nxt_reg_dat;
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reg_acc <= nxt_reg_acc;
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END GENERATE;
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gen_input_reg : IF g_pipeline_input>0 GENERATE
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p_reg : PROCESS(clk)
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BEGIN
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IF rising_edge(clk) THEN
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IF clken='1' THEN
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reg_dat <= nxt_reg_dat;
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reg_acc <= nxt_reg_acc;
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END IF;
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END IF;
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END PROCESS;
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END GENERATE;
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------------------------------------------------------------------------------
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-- Adder for the external accumulator
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------------------------------------------------------------------------------
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u_adder : ENTITY astron_adder_lib.common_add_sub
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GENERIC MAP (
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g_direction => "ADD",
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g_representation => "SIGNED", -- not relevant because g_out_dat_w = g_in_dat_w
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g_pipeline_input => 0,
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g_pipeline_output => g_pipeline_output,
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g_in_dat_w => g_acc_w,
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g_out_dat_w => g_acc_w
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)
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PORT MAP (
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clk => clk,
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clken => clken,
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in_a => reg_dat,
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in_b => reg_acc,
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result => out_acc
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);
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------------------------------------------------------------------------------
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-- Parallel output control pipeline
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------------------------------------------------------------------------------
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in_val_slv(0) <= in_val;
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out_val <= out_val_slv(0);
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u_out_val : ENTITY common_components_lib.common_pipeline
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GENERIC MAP (
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g_representation => "UNSIGNED",
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g_pipeline => c_pipeline,
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g_reset_value => 0,
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g_in_dat_w => 1,
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g_out_dat_w => 1
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)
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PORT MAP (
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clk => clk,
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clken => clken,
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in_dat => slv(in_val),
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out_dat => out_val_slv
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);
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END rtl;
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