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-------------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib, common_components_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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ENTITY tb_st_acc IS
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GENERIC (
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g_dat_w : NATURAL := 6;
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g_acc_w : NATURAL := 9;
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g_hold_load : BOOLEAN := TRUE;
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g_pipeline_input : NATURAL := 0;
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g_pipeline_output : NATURAL := 4
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);
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END tb_st_acc;
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ARCHITECTURE tb OF tb_st_acc IS
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CONSTANT clk_period : TIME := 10 ns;
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CONSTANT c_pipeline : NATURAL := g_pipeline_input + g_pipeline_output;
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FUNCTION func_acc(in_dat, in_acc : STD_LOGIC_VECTOR;
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in_val, in_load : STD_LOGIC) RETURN STD_LOGIC_VECTOR IS
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VARIABLE v_dat, v_acc, v_result : INTEGER;
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BEGIN
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-- Calculate expected result
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IF in_val='0' THEN -- hold: out_acc = in_acc
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v_result := TO_SINT(in_acc);
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ELSIF in_load='1' THEN -- force: out_acc = 0 + in_dat
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v_result := TO_SINT(in_dat);
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ELSE -- accumulate: out_acc = in_acc + in_dat
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v_result := TO_SINT(in_dat) + TO_SINT(in_acc);
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END IF;
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-- Wrap to avoid warning: NUMERIC_STD.TO_SIGNED: vector truncated
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IF v_result > 2**(g_acc_w-1)-1 THEN v_result := v_result - 2**g_acc_w; END IF;
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IF v_result < -2**(g_acc_w-1) THEN v_result := v_result + 2**g_acc_w; END IF;
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RETURN TO_SVEC(v_result, g_acc_w);
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END;
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SIGNAL tb_end : STD_LOGIC := '0';
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL in_dat : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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SIGNAL in_acc : STD_LOGIC_VECTOR(g_acc_w-1 DOWNTO 0) := (OTHERS=>'0');
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SIGNAL in_val : STD_LOGIC;
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SIGNAL in_load : STD_LOGIC;
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SIGNAL out_val : STD_LOGIC;
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SIGNAL out_acc : STD_LOGIC_VECTOR(g_acc_w-1 DOWNTO 0);
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SIGNAL expected_acc_p : STD_LOGIC_VECTOR(g_acc_w-1 DOWNTO 0);
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SIGNAL expected_acc : STD_LOGIC_VECTOR(g_acc_w-1 DOWNTO 0);
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BEGIN
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clk <= NOT clk OR tb_end AFTER clk_period/2;
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------------------------------------------------------------------------------
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-- Input stimuli
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------------------------------------------------------------------------------
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-- run -all
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p_stimuli : PROCESS
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BEGIN
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in_load <= '0';
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in_dat <= TO_SVEC(0, g_dat_w);
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in_val <= '0';
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WAIT UNTIL rising_edge(clk);
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FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(clk); END LOOP;
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in_load <= '1';
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in_val <= '1';
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FOR R IN 0 TO 2 LOOP -- Repeat some intervals marked by in_load = '1'
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in_load <= '1';
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-- All combinations
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FOR I IN -2**(g_dat_w-1) TO 2**(g_dat_w-1)-1 LOOP
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in_dat <= TO_SVEC(I, g_dat_w);
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WAIT UNTIL rising_edge(clk);
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-- keep in_load low during rest of period
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in_load <= '0';
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-- -- keep in_val low during rest of st_acc latency, to ease manual interpretation of out_acc as in_acc
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-- in_val <= '0';
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-- FOR J IN 1 TO c_pipeline-1 LOOP WAIT UNTIL rising_edge(clk); END LOOP;
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-- in_val <= '1';
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END LOOP;
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END LOOP;
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in_load <= '1'; -- keep '1' to avoid further toggling of out_acc (in a real design this would safe power)
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in_val <= '0';
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FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(clk); END LOOP;
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tb_end <= '1';
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WAIT;
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END PROCESS;
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------------------------------------------------------------------------------
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-- DUT
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------------------------------------------------------------------------------
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dut : ENTITY work.st_acc
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GENERIC MAP (
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g_dat_w => g_dat_w,
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g_acc_w => g_acc_w,
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g_hold_load => g_hold_load,
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g_pipeline_input => g_pipeline_input,
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g_pipeline_output => g_pipeline_output
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)
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PORT MAP (
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clk => clk,
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clken => '1',
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in_load => in_load, -- start of accumulate period
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in_dat => in_dat,
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in_acc => in_acc, -- use only one accumulator
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in_val => in_val,
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out_acc => out_acc,
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out_val => out_val
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);
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in_acc <= out_acc WHEN c_pipeline>0 ELSE
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out_acc WHEN rising_edge(clk); -- if DUT has no pipeline, then register feedback to avoid combinatorial loop
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------------------------------------------------------------------------------
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-- Verify
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------------------------------------------------------------------------------
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expected_acc <= func_acc(in_dat, in_acc, in_val, in_load);
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u_result : ENTITY common_components_lib.common_pipeline
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GENERIC MAP (
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g_representation => "SIGNED",
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g_pipeline => c_pipeline,
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g_reset_value => 0,
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g_in_dat_w => g_acc_w,
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g_out_dat_w => g_acc_w
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)
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PORT MAP (
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clk => clk,
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clken => '1',
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in_dat => expected_acc,
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out_dat => expected_acc_p
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);
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p_verify : PROCESS(clk)
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BEGIN
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IF rising_edge(clk) THEN
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IF out_val='1' THEN
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ASSERT out_acc = expected_acc_p REPORT "Error: wrong result" SEVERITY ERROR;
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END IF;
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END IF;
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END PROCESS;
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END tb;
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