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[/] [astron_statistics/] [trunk/] [tb_st_calc.vhd] - Blame information for rev 3

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-------------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- 
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- 
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--     http://www.apache.org/licenses/LICENSE-2.0
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-- 
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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ENTITY tb_st_calc IS
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  GENERIC (
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    g_in_dat_w     : NATURAL := 16;
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    g_out_dat_w    : NATURAL := 32
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  );
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END tb_st_calc;
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ARCHITECTURE tb OF tb_st_calc IS
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  CONSTANT clk_period             : TIME := 10 ns;
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  CONSTANT c_nof_sync             : NATURAL := 3;
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  CONSTANT c_nof_stat             : NATURAL := 100;
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  CONSTANT c_out_adr_w            : NATURAL := ceil_log2(c_nof_stat);
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  CONSTANT c_gap_size             : NATURAL := 2**c_out_adr_w - c_nof_stat;
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  CONSTANT c_nof_accum_per_sync   : NATURAL := 5;  -- integration time
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  SIGNAL tb_end          : STD_LOGIC := '0';
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  SIGNAL clk             : STD_LOGIC := '0';
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  SIGNAL rst             : STD_LOGIC;
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  SIGNAL in_sync         : STD_LOGIC;
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  SIGNAL in_val          : STD_LOGIC;
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  SIGNAL in_dat          : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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  SIGNAL in_a_re         : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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  SIGNAL in_a_im         : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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  SIGNAL in_b_re         : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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  SIGNAL in_b_im         : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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  SIGNAL out_adr         : STD_LOGIC_VECTOR(c_out_adr_w-1 DOWNTO 0);
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  SIGNAL out_re          : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
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  SIGNAL out_im          : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
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  SIGNAL out_val         : STD_LOGIC;
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BEGIN
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  clk  <= NOT clk OR tb_end AFTER clk_period/2;
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  in_a_re <= in_dat;
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  in_a_im <= in_dat;
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  in_b_re <= in_dat;
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  in_b_im <= in_dat;
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  in_dat <= (OTHERS=>'0') WHEN rst='1' ELSE INCR_UVEC(in_dat, 1) WHEN rising_edge(clk) AND in_val='1';
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  -- run 1 us
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  p_stimuli : PROCESS
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  BEGIN
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    rst <= '1';
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    in_sync <= '0';
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    in_val <= '0';
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    WAIT UNTIL rising_edge(clk);
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    FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(clk); END LOOP;
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    rst <= '0';
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    FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(clk); END LOOP;
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    FOR I IN 0 TO c_nof_sync-1 LOOP
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      in_sync <= '1';
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      WAIT UNTIL rising_edge(clk);
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      in_sync <= '0';
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      FOR J IN 0 TO c_nof_accum_per_sync-1 LOOP
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        in_val <= '1';
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        FOR I IN 0 TO c_nof_stat-1 LOOP WAIT UNTIL rising_edge(clk); END LOOP;
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        in_val <= '0';
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        FOR I IN 0 TO c_gap_size-1 LOOP WAIT UNTIL rising_edge(clk); END LOOP;
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      END LOOP;
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    END LOOP;
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    FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(clk); END LOOP;
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    tb_end <= '1';
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    WAIT;
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  END PROCESS;
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  u_dut : ENTITY work.st_calc
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  GENERIC MAP (
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    g_nof_mux       => 1,
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    g_nof_stat      => c_nof_stat,
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    g_in_dat_w      => g_in_dat_w,
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    g_out_dat_w     => g_out_dat_w,
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    g_out_adr_w     => c_out_adr_w,
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    g_complex       => FALSE
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  )
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  PORT MAP (
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    rst        => rst,
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    clk        => clk,
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    clken      => '1',
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    in_ar      => in_a_re,
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    in_ai      => in_a_im,
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    in_br      => in_b_re,
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    in_bi      => in_b_im,
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    in_val     => in_val,
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    in_sync    => in_sync,
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    out_adr    => out_adr,
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    out_re     => out_re,
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    out_im     => out_im,
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    out_val    => out_val,
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    out_val_m  => OPEN
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  );
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END tb;

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