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-------------------------------------------------------------------------------
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--
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danv |
-- Copyright 2020
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danv |
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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danv |
--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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danv |
--
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-------------------------------------------------------------------------------
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-- Purpose: Test bench for fft_r2_bf_par
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-- Features:
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--
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-- Usage:
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-- > as 10
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-- > run -all
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-- Testbench is selftesting.
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library IEEE, common_pkg_lib, dp_pkg_lib, diag_lib, rTwoSDF_lib, common_ram_lib, mm_lib, common_components_lib;
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use IEEE.std_logic_1164.ALL;
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use IEEE.numeric_std.ALL;
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use common_pkg_lib.common_pkg.ALL;
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use common_ram_lib.common_ram_pkg.ALL;
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use common_pkg_lib.common_lfsr_sequences_pkg.ALL;
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use common_pkg_lib.tb_common_pkg.ALL;
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use mm_lib.tb_common_mem_pkg.ALL;
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use dp_pkg_lib.dp_stream_pkg.ALL;
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use diag_lib.diag_pkg.ALL;
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use rTwoSDF_lib.twiddlesPkg.all;
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use rTwoSDF_lib.rTwoSDFPkg.all;
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entity tb_fft_r2_bf_par is
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generic(
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g_stage : natural := 4;
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g_element : natural := 2
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);
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end tb_fft_r2_bf_par;
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architecture tb of tb_fft_r2_bf_par is
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constant c_pipeline : t_fft_pipeline := c_fft_pipeline; -- defined in rTwoSDF_lib.rTwoSDFPkg
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constant c_clk_period : time := 10 ns;
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constant c_nof_points : natural := 1024; -- Number of points should be a power of 2
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constant c_conjugate : boolean := FALSE;
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constant c_in_dat_w : natural := 16;
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constant c_weight_w : natural := 16;
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constant c_prod_w : natural := c_in_dat_w+c_weight_w;
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constant c_complex_prod_w : natural := c_prod_w+1;
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constant c_bit_growth : natural := 1;
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constant c_round_w : natural := c_weight_w-c_bit_growth; -- the weights are normalized
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-- BG derived constants
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constant c_nof_streams : natural := 2;
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constant c_bg_mem_size : natural := 1024;
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constant c_bg_addr_w : natural := ceil_log2(c_bg_mem_size);
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constant c_nof_samples_in_packet : natural := c_nof_points;
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constant c_gap : natural := 0; -- Gapsize is set to 0 in order to generate a continuous stream of packets.
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constant c_bst_skip_nof_sync : natural := 3;
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constant c_nof_accum_per_sync : natural := 10;
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constant c_bsn_init : natural := 32;
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constant c_bg_prefix : string := "data/ramp";
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signal tb_end : std_logic := '0';
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signal rst : std_logic;
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signal clk : std_logic := '1';
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signal ram_bg_data_mosi : t_mem_mosi;
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signal reg_bg_ctrl_mosi : t_mem_mosi;
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signal in_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 downto 0);
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signal in_siso_arr : t_dp_siso_arr(c_nof_streams-1 downto 0);
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signal out_sosi : t_dp_sosi;
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signal in_dat : std_logic_vector(2*c_in_dat_w-1 downto 0);
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signal x_out_re : std_logic_vector(c_in_dat_w-1 downto 0);
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signal x_out_im : std_logic_vector(c_in_dat_w-1 downto 0);
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signal y_out_re : std_logic_vector(c_in_dat_w-1 downto 0);
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signal y_out_im : std_logic_vector(c_in_dat_w-1 downto 0);
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signal out_val : std_logic;
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signal ref_x_out_re_dly : std_logic_vector(c_in_dat_w-1 downto 0);
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signal ref_x_out_im_dly : std_logic_vector(c_in_dat_w-1 downto 0);
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signal ref_x_out_re : std_logic_vector(c_in_dat_w-1 downto 0);
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signal ref_x_out_im : std_logic_vector(c_in_dat_w-1 downto 0);
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signal ref_y_out_re_dly : std_logic_vector(c_in_dat_w-1 downto 0);
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signal ref_y_out_im_dly : std_logic_vector(c_in_dat_w-1 downto 0);
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signal ref_y_out_re : std_logic_vector(c_in_dat_w-1 downto 0);
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signal ref_y_out_im : std_logic_vector(c_in_dat_w-1 downto 0);
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signal ref_y_out_re_dif : std_logic_vector(c_in_dat_w-1 downto 0);
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signal ref_y_out_im_dif : std_logic_vector(c_in_dat_w-1 downto 0);
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signal ref_y_prod_re : std_logic_vector(2*c_in_dat_w-1 downto 0);
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signal ref_y_prod_im : std_logic_vector(2*c_in_dat_w-1 downto 0);
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signal weight_re : wTyp;
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signal weight_im : wTyp;
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begin
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clk <= (not clk) or tb_end after c_clk_period/2;
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rst <= '1', '0' after c_clk_period*3;
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p_control_input_stream : process
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begin
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tb_end <= '0';
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reg_bg_ctrl_mosi <= c_mem_mosi_rst;
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-- Wait until reset is done
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proc_common_wait_until_high(clk, rst);
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proc_common_wait_some_cycles(clk, 10);
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-- Set and enable the waveform generators. All generators are controlled by the same registers
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proc_mem_mm_bus_wr(1, c_nof_samples_in_packet, clk, reg_bg_ctrl_mosi); -- Set the number of samples per block
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proc_mem_mm_bus_wr(2, c_nof_accum_per_sync, clk, reg_bg_ctrl_mosi); -- Set the number of blocks per sync
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proc_mem_mm_bus_wr(3, c_gap, clk, reg_bg_ctrl_mosi); -- Set the gapsize
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proc_mem_mm_bus_wr(4, 0, clk, reg_bg_ctrl_mosi); -- Set the start address of the memory
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proc_mem_mm_bus_wr(5, c_nof_samples_in_packet-1, clk, reg_bg_ctrl_mosi); -- Set the end address of the memory
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proc_mem_mm_bus_wr(6, c_bsn_init, clk, reg_bg_ctrl_mosi); -- Set the BSNInit low value
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proc_mem_mm_bus_wr(7, 0, clk, reg_bg_ctrl_mosi); -- Set the BSNInit high value
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proc_mem_mm_bus_wr(0, 1, clk, reg_bg_ctrl_mosi); -- Enable the BG
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-- Run time
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proc_common_wait_some_cycles(clk, c_nof_points);
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proc_mem_mm_bus_wr(0, 0, clk, reg_bg_ctrl_mosi); -- Disable the BG
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-- The end
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proc_common_wait_some_cycles(clk, c_nof_points + 20);
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tb_end <= '1';
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wait;
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end process;
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u_block_generator : entity diag_lib.mms_diag_block_gen
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generic map(
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g_nof_streams => c_nof_streams,
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g_buf_dat_w => c_nof_complex*c_in_dat_w,
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g_buf_addr_w => c_bg_addr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
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g_file_name_prefix => c_bg_prefix
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)
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port map(
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-- Clocks and reset
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mm_rst => rst,
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mm_clk => clk,
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dp_rst => rst,
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dp_clk => clk,
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en_sync => '1',
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ram_bg_data_mosi => ram_bg_data_mosi,
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ram_bg_data_miso => open,
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reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
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reg_bg_ctrl_miso => open,
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out_siso_arr => in_siso_arr,
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out_sosi_arr => in_sosi_arr
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);
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in_siso_arr(0) <= c_dp_siso_rdy;
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in_siso_arr(1) <= c_dp_siso_rdy;
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-- device under test
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u_dut : entity work.fft_r2_bf_par
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generic map (
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g_stage => g_stage,
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g_element => g_element
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)
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port map (
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clk => clk,
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rst => rst,
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x_in_re => in_sosi_arr(0).re(c_in_dat_w-1 downto 0),
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x_in_im => in_sosi_arr(0).im(c_in_dat_w-1 downto 0),
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y_in_re => in_sosi_arr(1).re(c_in_dat_w-1 downto 0),
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y_in_im => in_sosi_arr(1).im(c_in_dat_w-1 downto 0),
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in_val => in_sosi_arr(0).valid,
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x_out_re => x_out_re,
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x_out_im => x_out_im,
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y_out_re => y_out_re,
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y_out_im => y_out_im,
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out_val => out_val
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);
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-- verification
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weight_re <= wRe(wMap(g_element, g_stage));
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weight_im <= wIm(wMap(g_element, g_stage));
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p_verify : process
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variable v_ref_y_out_re_dif : std_logic_vector(c_in_dat_w-1 downto 0);
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variable v_ref_y_out_im_dif : std_logic_vector(c_in_dat_w-1 downto 0);
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variable v_ref_y_prod_re : std_logic_vector(2*c_in_dat_w-1 downto 0);
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variable v_ref_y_prod_im : std_logic_vector(2*c_in_dat_w-1 downto 0);
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begin
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wait until (rising_edge(clk) and in_sosi_arr(0).valid = '1');
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ref_x_out_re <= ADD_SVEC(in_sosi_arr(0).re(c_in_dat_w-1 downto 0), in_sosi_arr(1).re(c_in_dat_w-1 downto 0), ref_x_out_re'length);
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ref_x_out_im <= ADD_SVEC(in_sosi_arr(0).im(c_in_dat_w-1 downto 0), in_sosi_arr(1).im(c_in_dat_w-1 downto 0), ref_x_out_im'length);
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v_ref_y_out_re_dif := SUB_SVEC(in_sosi_arr(0).re(c_in_dat_w-1 downto 0), in_sosi_arr(1).re(c_in_dat_w-1 downto 0), ref_x_out_re'length);
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v_ref_y_out_im_dif := SUB_SVEC(in_sosi_arr(0).im(c_in_dat_w-1 downto 0), in_sosi_arr(1).im(c_in_dat_w-1 downto 0), ref_x_out_im'length);
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v_ref_y_prod_re := func_complex_multiply(v_ref_y_out_re_dif, v_ref_y_out_im_dif, weight_re, weight_im, c_conjugate, "RE", ref_y_prod_re'length);
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v_ref_y_prod_im := func_complex_multiply(v_ref_y_out_re_dif, v_ref_y_out_im_dif, weight_re, weight_im, c_conjugate, "IM", ref_y_prod_im'length);
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ref_y_out_re <= truncate_and_resize_svec(v_ref_y_prod_re, c_round_w, ref_y_out_re'length);
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ref_y_out_im <= truncate_and_resize_svec(v_ref_y_prod_im, c_round_w, ref_y_out_im'length);
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end process;
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u_verify_pipeline_x_re : entity common_components_lib.common_pipeline
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generic map (
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g_pipeline => (c_pipeline.bf_lat + c_pipeline.mul_lat),
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g_in_dat_w => ref_x_out_re'length,
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g_out_dat_w => ref_x_out_re'length
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)
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port map (
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clk => clk,
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in_dat => ref_x_out_re,
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out_dat => ref_x_out_re_dly
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);
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u_verify_pipeline_x_im : entity common_components_lib.common_pipeline
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generic map (
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g_pipeline => (c_pipeline.bf_lat + c_pipeline.mul_lat),
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g_in_dat_w => ref_x_out_im'length,
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g_out_dat_w => ref_x_out_im'length
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)
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port map (
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clk => clk,
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in_dat => ref_x_out_im,
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out_dat => ref_x_out_im_dly
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);
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u_verify_pipeline_y_re : entity common_components_lib.common_pipeline
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generic map (
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g_pipeline => (c_pipeline.bf_lat + c_pipeline.mul_lat),
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g_in_dat_w => ref_y_out_re'length,
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g_out_dat_w => ref_y_out_re'length
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)
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port map (
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clk => clk,
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in_dat => ref_y_out_re,
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out_dat => ref_y_out_re_dly
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);
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u_verify_pipeline_y_im : entity common_components_lib.common_pipeline
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generic map (
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g_pipeline => (c_pipeline.bf_lat + c_pipeline.mul_lat),
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g_in_dat_w => ref_y_out_im'length,
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g_out_dat_w => ref_y_out_im'length
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)
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port map (
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clk => clk,
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in_dat => ref_y_out_im,
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out_dat => ref_y_out_im_dly
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);
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------------------------------------------------------------------------
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-- Simples process that does the final test.
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------------------------------------------------------------------------
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p_tester : process(rst, clk)
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variable I : integer;
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begin
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if rst='0' then
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if rising_edge(clk) and out_val = '1' then
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assert ref_x_out_re_dly = x_out_re report "Error: wrong RTL result in X real path" severity error;
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assert ref_x_out_im_dly = x_out_im report "Error: wrong RTL result in X imag path" severity error;
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assert ref_y_out_re_dly = y_out_re report "Error: wrong RTL result in Y real path" severity error;
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assert ref_y_out_im_dly = y_out_im report "Error: wrong RTL result in Y imag path" severity error;
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end if;
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end if;
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end process p_tester;
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end tb;
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