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-------------------------------------------------------------------------------
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-- Author: Harm Jan Pepping : HJP at astron.nl: April 2012
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--
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-- Copyright (C) 2011
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-------------------------------------------------------------------------------
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-- Purpose: Test bench for fft_sepa
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-- Features:
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--
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-- Usage:
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-- > as 10
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-- > run -all
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-- > Testbench is selftesting.
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-- First frame contains always some errors.
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library IEEE, common_pkg_lib, dp_pkg_lib, diag_lib, common_ram_lib, mm_lib;
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use IEEE.std_logic_1164.ALL;
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use IEEE.numeric_std.ALL;
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use common_pkg_lib.common_pkg.ALL;
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use common_ram_lib.common_ram_pkg.ALL;
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use common_pkg_lib.tb_common_pkg.ALL;
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use mm_lib.tb_common_mem_pkg.ALL;
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use dp_pkg_lib.dp_stream_pkg.ALL;
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use diag_lib.diag_pkg.ALL;
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entity tb_fft_sepa is
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end tb_fft_sepa;
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architecture tb of tb_fft_sepa is
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constant c_clk_period : time := 10 ns;
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constant c_nof_points : natural := 8;
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constant c_nof_points_b : natural := 1024;
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constant c_in_dat_w : natural := 16;
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constant c_bg_addr_w : natural := ceil_log2(c_nof_points_b);
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type t_input_buf_arr is array (integer range <>) of std_logic_vector(c_in_dat_w-1 downto 0);
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-- BG derived constants
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constant c_nof_samples_in_packet : natural := c_nof_points;
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constant c_gap : natural := 8;
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constant c_bst_skip_nof_sync : natural := 3;
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constant c_nof_accum_per_sync : natural := 10;
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constant c_bsn_init : natural := 32;
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constant c_bg_prefix : string := "data/to_separate";
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signal tb_end : std_logic := '0';
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signal rst : std_logic;
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signal clk : std_logic := '1';
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signal ram_bg_data_mosi : t_mem_mosi;
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signal reg_bg_ctrl_mosi : t_mem_mosi;
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signal in_sosi_arr : t_dp_sosi_arr(0 downto 0);
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signal in_siso_arr : t_dp_siso_arr(0 downto 0);
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signal out_sosi : t_dp_sosi;
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signal in_dat : std_logic_vector(2*c_in_dat_w-1 downto 0);
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signal out_dat : std_logic_vector(2*c_in_dat_w-1 downto 0);
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signal out_dat_re : std_logic_vector(c_in_dat_w-1 downto 0);
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signal out_dat_im : std_logic_vector(c_in_dat_w-1 downto 0);
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signal out_val : std_logic;
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signal buf_input_re : t_input_buf_arr(c_nof_points-1 downto 0);
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signal buf_input_im : t_input_buf_arr(c_nof_points-1 downto 0);
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signal buf_output_a_re : t_input_buf_arr(c_nof_points/2-1 downto 0);
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signal buf_output_a_im : t_input_buf_arr(c_nof_points/2-1 downto 0);
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signal buf_output_b_re : t_input_buf_arr(c_nof_points/2-1 downto 0);
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signal buf_output_b_im : t_input_buf_arr(c_nof_points/2-1 downto 0);
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signal buf_output_re : t_input_buf_arr(c_nof_points-1 downto 0);
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signal buf_output_im : t_input_buf_arr(c_nof_points-1 downto 0);
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begin
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clk <= (not clk) or tb_end after c_clk_period/2;
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rst <= '1', '0' after c_clk_period*3;
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p_control_input_stream : process
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begin
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tb_end <= '0';
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reg_bg_ctrl_mosi <= c_mem_mosi_rst;
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-- Wait until reset is done
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proc_common_wait_until_high(clk, rst);
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proc_common_wait_some_cycles(clk, 10);
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-- Set and enable the waveform generators. All generators are controlled by the same registers
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proc_mem_mm_bus_wr(1, c_nof_samples_in_packet, clk, reg_bg_ctrl_mosi); -- Set the number of samples per block
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proc_mem_mm_bus_wr(2, c_nof_accum_per_sync, clk, reg_bg_ctrl_mosi); -- Set the number of blocks per sync
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proc_mem_mm_bus_wr(3, c_gap, clk, reg_bg_ctrl_mosi); -- Set the gapsize
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proc_mem_mm_bus_wr(4, 0, clk, reg_bg_ctrl_mosi); -- Set the start address of the memory
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proc_mem_mm_bus_wr(5, c_nof_samples_in_packet-1, clk, reg_bg_ctrl_mosi); -- Set the end address of the memory
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proc_mem_mm_bus_wr(6, c_bsn_init, clk, reg_bg_ctrl_mosi); -- Set the BSNInit low value
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proc_mem_mm_bus_wr(7, 0, clk, reg_bg_ctrl_mosi); -- Set the BSNInit high value
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proc_mem_mm_bus_wr(0, 1, clk, reg_bg_ctrl_mosi); -- Enable the BG
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-- Run time
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proc_common_wait_some_cycles(clk, 300);
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proc_mem_mm_bus_wr(0, 0, clk, reg_bg_ctrl_mosi); -- Disable the BG
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-- The end
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proc_common_wait_some_cycles(clk, c_nof_points + 20);
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tb_end <= '1';
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wait;
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end process;
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u_block_generator : entity diag_lib.mms_diag_block_gen
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generic map(
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g_nof_streams => 1,
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g_buf_dat_w => c_nof_complex*c_in_dat_w,
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g_buf_addr_w => c_bg_addr_w, -- Waveform buffer size 2**g_buf_addr_w nof samples
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g_file_name_prefix => c_bg_prefix
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)
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port map(
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-- Clocks and reset
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mm_rst => rst,
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mm_clk => clk,
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dp_rst => rst,
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dp_clk => clk,
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en_sync => '1',
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ram_bg_data_mosi => ram_bg_data_mosi,
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ram_bg_data_miso => open,
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reg_bg_ctrl_mosi => reg_bg_ctrl_mosi,
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reg_bg_ctrl_miso => open,
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out_siso_arr => in_siso_arr,
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out_sosi_arr => in_sosi_arr
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);
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in_siso_arr(0) <= c_dp_siso_rdy;
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-- device under test
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u_dut : entity work.fft_sepa
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port map (
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clk => clk,
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rst => rst,
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in_dat => in_dat,
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in_val => in_sosi_arr(0).valid,
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out_dat => out_dat,
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out_val => out_val
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);
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in_dat <= in_sosi_arr(0).im(c_in_dat_w-1 downto 0) & in_sosi_arr(0).re(c_in_dat_w-1 downto 0);
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out_dat_re <= out_dat(c_in_dat_w-1 downto 0);
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out_dat_im <= out_dat(2*c_in_dat_w-1 downto c_in_dat_w);
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out_sosi.re(c_in_dat_w-1 downto 0) <= out_dat(c_in_dat_w-1 downto 0);
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out_sosi.im(c_in_dat_w-1 downto 0) <= out_dat(2*c_in_dat_w-1 downto c_in_dat_w);
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-- verification
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p_verify : process
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variable I : integer;
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variable v_buf_output_a_re : t_input_buf_arr(c_nof_points/2-1 downto 0);
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variable v_buf_output_a_im : t_input_buf_arr(c_nof_points/2-1 downto 0);
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variable v_buf_output_b_re : t_input_buf_arr(c_nof_points/2-1 downto 0);
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variable v_buf_output_b_im : t_input_buf_arr(c_nof_points/2-1 downto 0);
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begin
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I := 0;
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wait until in_sosi_arr(0).sync = '1';
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while I < c_nof_points loop
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wait until (rising_edge(clk) and in_sosi_arr(0).valid = '1');
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buf_input_re(I) <= in_sosi_arr(0).re(c_in_dat_w-1 downto 0);
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buf_input_im(I) <= in_sosi_arr(0).im(c_in_dat_w-1 downto 0);
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I := I + 1;
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end loop;
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proc_common_wait_some_cycles(clk, 1);
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for J in 0 to c_nof_points/2-1 loop
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v_buf_output_a_re(J) := ADD_SVEC(buf_input_re(2*J+1), buf_input_re(2*J), c_in_dat_w+1)(c_in_dat_w downto 1);
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v_buf_output_a_im(J) := SUB_SVEC(buf_input_im(2*J), buf_input_im(2*J+1), c_in_dat_w+1)(c_in_dat_w downto 1);
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v_buf_output_b_re(J) := ADD_SVEC(buf_input_im(2*J+1), buf_input_im(2*J), c_in_dat_w+1)(c_in_dat_w downto 1);
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v_buf_output_b_im(J) := SUB_SVEC(buf_input_re(2*J+1), buf_input_re(2*J), c_in_dat_w+1)(c_in_dat_w downto 1);
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buf_output_re(2*J) <= v_buf_output_a_re(J);
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buf_output_im(2*J) <= v_buf_output_a_im(J);
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buf_output_re(2*J+1) <= v_buf_output_b_re(J);
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buf_output_im(2*J+1) <= v_buf_output_b_im(J);
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end loop;
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wait;
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end process;
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------------------------------------------------------------------------
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-- Simples process that does the final test.
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------------------------------------------------------------------------
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p_tester : process(rst, clk)
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variable I : integer;
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begin
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if rst='0' then
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if rising_edge(clk) and out_val = '1' then
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assert buf_output_re(I) = out_dat_re report "Error: wrong RTL result in real path" severity ERROR;
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assert buf_output_im(I) = out_dat_im report "Error: wrong RTL result in imag path" severity ERROR;
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if(I = c_nof_points - 1 ) then
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I := 0;
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else
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I := I + 1;
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end if;
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end if;
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else
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I := 0;
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end if;
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end process p_tester;
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end tb;
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