URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [branches/] [clos_opt/] [clos_opt/] [src/] [clos_buf.v] - Blame information for rev 72

Go to most recent revision | Details | Compare with Previous | View Log


/*
 Asynchronous SDM NoC
 (C)2011 Wei Song
 Advanced Processor Technologies Group
 Computer Science, the Univ. of Manchester, UK
 
 Authors:
 Wei Song     wsong83@gmail.com
 
 License: LGPL 3.0 or later
 
 Buffered Clos switch for SDM-Clos routers
 *** SystemVerilog is used ***
 
 History:
 09/07/2011  Initial version. <wsong83@gmail.com>
 
*/
 
// the router structure definitions
`include "define.v"
 
module clos (/*AUTOARG*/);
 
   parameter MN = 2;            // number of CMs
   parameter NN = 2;            // number of ports in an IM or OM, equ. to number of virtual circuits
   parameter DW = 8;            // datawidth of a single virtual circuit/port
   parameter SCN = DW/2;        // number of 1-of-4 sub-channels in one port
 
   input [NN-1:0][SCN-1:0]     si0, si1, si2, si3; // south input [0], X+1
   input [NN-1:0][SCN-1:0]     wi0, wi1, wi2, wi3; // west input [1], Y-1
   input [NN-1:0][SCN-1:0]     ni0, ni1, ni2, ni3; // north input [2], X-1
   input [NN-1:0][SCN-1:0]     ei0, ei1, ei2, ei3; // east input [3], Y+1
   input [NN-1:0][SCN-1:0]     li0, li1, li2, li3; // local input
   output [NN-1:0][SCN-1:0]    so0, so1, so2, so3; // south output
   output [NN-1:0][SCN-1:0]    wo0, wo1, wo2, wo3; // west output
   output [NN-1:0][SCN-1:0]    no0, no1, no2, no3; // north output
   output [NN-1:0][SCN-1:0]    eo0, eo1, eo2, eo3; // east output
   output [NN-1:0][SCN-1:0]    lo0, lo1, lo2, lo3; // local output
 
   // eof bits and ack lines
`ifdef ENABLE_CHANNEL_SLICING
   input [NN-1:0][SCN-1:0]     si4, wi4, ni4, ei4, li4;
   output [NN-1:0][SCN-1:0]    so4, wo4, no4, eo4, lo4;
   output [NN-1:0][SCN-1:0]    sia, wia, nia, eia, lia;
   input [NN-1:0][SCN-1:0]     soa, woa, noa, eoa, loa;
 `ifdef ENABLE_BUFFERED_CLOS
   input [NN-1:0][SCN-1:0]     soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
 `endif
`else
   input [NN-1:0]               si4, wi4, ni4, ei4, li4;
   output [NN-1:0]              so4, wo4, no4, eo4, lo4;
   output [NN-1:0]              sia, wia, nia, eia, lia;
   input [NN-1:0]               soa, woa, noa, eoa, loa;
 `ifdef ENABLE_BUFFERED_CLOS
   input [NN-1:0]               soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
 `endif
`endif // !`ifdef ENABLE_CHANNEL_SLICING
 
   input [NN-1:0][3:0]           sdec, ndec, ldec; // the routing requests
   input [NN-1:0][1:0]         wdec, edec;         // the routing requests
 
   genvar                      i,j;
 
 
   // the IMs
   im #(.MN(MN), .NN(NN), .DW(DW), .SN(4))
   SIM (
        .do0   ( sim0   ),
        .do1   ( sim1   ),
        .do2   ( sim2   ),
        .do3   ( sim3   ),
        .deco  ( simdec ),
        .dia   ( sia    ),
        .do4   ( sim4   ),
        .di0   ( si0    ),
        .di1   ( si1    ),
        .di2   ( si2    ),
        .di3   ( si3    ),
        .deci  ( sdec   ),
        .di4   ( si4    ),
        .doa   ( sima   ),
`ifndef ENABLE_CRRD
        .cms   ( sims   ),
`endif
        .rst_n ( rst_n  )
        );
 
   im #(.MN(MN), .NN(NN), .DW(DW), .SN(2))
   WIM (
        .do0   ( wim0   ),
        .do1   ( wim1   ),
        .do2   ( wim2   ),
        .do3   ( wim3   ),
        .deco  ( wimdec ),
        .dia   ( wia    ),
        .do4   ( wim4   ),
        .di0   ( wi0    ),
        .di1   ( wi1    ),
        .di2   ( wi2    ),
        .di3   ( wi3    ),
        .deci  ( wdec   ),
        .di4   ( wi4    ),
        .doa   ( wima   ),
`ifndef ENABLE_CRRD
        .cms   ( wims   ),
`endif
        .rst_n ( rst_n  )
        );
 
   im #(.MN(MN), .NN(NN), .DW(DW), .SN(4))
   NIM (
        .do0   ( nim0   ),
        .do1   ( nim1   ),
        .do2   ( nim2   ),
        .do3   ( nim3   ),
        .deco  ( nimdec ),
        .dia   ( nia    ),
        .do4   ( nim4   ),
        .di0   ( ni0    ),
        .di1   ( ni1    ),
        .di2   ( ni2    ),
        .di3   ( ni3    ),
        .deci  ( ndec   ),
        .di4   ( ni4    ),
        .doa   ( nima   ),
`ifndef ENABLE_CRRD
        .cms   ( nims   ),
`endif
        .rst_n ( rst_n  )
        );
 
   im #(.MN(MN), .NN(NN), .DW(DW), .SN(2))
   EIM (
        .do0   ( eim0   ),
        .do1   ( eim1   ),
        .do2   ( eim2   ),
        .do3   ( eim3   ),
        .deco  ( eimdec ),
        .dia   ( eia    ),
        .do4   ( eim4   ),
        .di0   ( ei0    ),
        .di1   ( ei1    ),
        .di2   ( ei2    ),
        .di3   ( ei3    ),
        .deci  ( edec   ),
        .di4   ( ei4    ),
        .doa   ( eima   ),
`ifndef ENABLE_CRRD
        .cms   ( eims   ),
`endif
        .rst_n ( rst_n  )
        );
 
   im #(.MN(MN), .NN(NN), .DW(DW), .SN(4))
   LIM (
        .do0   ( lim0   ),
        .do1   ( lim1   ),
        .do2   ( lim2   ),
        .do3   ( lim3   ),
        .deco  ( limdec ),
        .dia   ( lia    ),
        .do4   ( lim4   ),
        .di0   ( li0    ),
        .di1   ( li1    ),
        .di2   ( li2    ),
        .di3   ( li3    ),
        .deci  ( ldec   ),
        .di4   ( li4    ),
        .doa   ( lima   ),
`ifndef ENABLE_CRRD
        .cms   ( lims   ),
`endif
        .rst_n ( rst_n  )
        );
 
   // data wire shuffle
   // the CMs
   generate
      for(i=0; i<MN; i++) begin:CMSH
         assign cmi0[i][0] = sim0[i];
         assign cmi1[i][0] = sim1[i];
         assign cmi2[i][0] = sim2[i];
         assign cmi3[i][0] = sim3[i];
         assign sima[i] = cmia[i][0];
         assign sima4[i] = cmia[i][0];
 
         assign cmi0[i][1] = wim0[i];
         assign cmi1[i][1] = wim1[i];
         assign cmi2[i][1] = wim2[i];
         assign cmi3[i][1] = wim3[i];
         assign wima[i] = cmia[i][1];
         assign wima4[i] = cmia[i][1];
 
         assign cmi0[i][2] = nim0[i];
         assign cmi1[i][2] = nim1[i];
         assign cmi2[i][2] = nim2[i];
         assign cmi3[i][2] = nim3[i];
         assign nima[i] = cmia[i][2];
         assign nima4[i] = cmia[i][2];
 
         assign cmi0[i][3] = eim0[i];
         assign cmi1[i][3] = eim1[i];
         assign cmi2[i][3] = eim2[i];
         assign cmi3[i][3] = eim3[i];
         assign eima[i] = cmia[i][3];
         assign eima4[i] = cmia[i][3];
 
         assign cmi0[i][4] = lim0[i];
         assign cmi1[i][4] = lim1[i];
         assign cmi2[i][4] = lim2[i];
         assign cmi3[i][4] = lim3[i];
         assign lima[i] = cmia[i][4];
         assign lima4[i] = cmia[i][4];
 
         cm #(.KN(5), .DW(DW))
         CMSW (
               .do0   ( cmo0[i]  ),
               .do1   ( cmo1[i]  ),
               .do2   ( cmo2[i]  ),
               .do3   ( cmo3[i]  ),
               .dia   ( cmia[i]  ),
               .do4   ( cmo4[i]  ),
               .di0   ( cmi0[i]  ),
               .di1   ( cmi1[i]  ),
               .di2   ( cmi2[i]  ),
               .di3   ( cmi3[i]  ),
               .sdec  ( sdec[i]  ),
               .ndec  ( ndec[i]  ),
               .ldec  ( ldec[i]  ),
               .wdec  ( wdec[i]  ),
               .edec  ( edec[i]  ),
               .di4   ( cmi4[i]  ),
               .doa   ( cmoa[i]  ),
               .doa4  ( cmoa4[i] ),
`ifndef ENABLE_CRRD
               .cms   ( cms[i]   ),
`endif
               .rst_n ( rst_n    )
               );
 
         assign so0[i] = cmo0[i][0];
         assign so1[i] = cmo1[i][0];
         assign so2[i] = cmo2[i][0];
         assign so3[i] = cmo3[i][0];
         assign cmoa[i][0] = soa[i];
         assign cmoa[i][0] = soa4[i];
 
         assign wo0[i] = cmo0[i][1];
         assign wo1[i] = cmo1[i][1];
         assign wo2[i] = cmo2[i][1];
         assign wo3[i] = cmo3[i][1];
         assign cmoa[i][1] = woa[i];
         assign cmoa[i][1] = woa4[i];
 
         assign no0[i] = cmo0[i][2];
         assign no1[i] = cmo1[i][2];
         assign no2[i] = cmo2[i][2];
         assign no3[i] = cmo3[i][2];
         assign cmoa[i][2] = noa[i];
         assign cmoa[i][2] = noa4[i];
 
         assign eo0[i] = cmo0[i][3];
         assign eo1[i] = cmo1[i][3];
         assign eo2[i] = cmo2[i][3];
         assign eo3[i] = cmo3[i][3];
         assign cmoa[i][3] = eoa[i];
         assign cmoa[i][3] = eoa4[i];
 
         assign lo0[i] = cmo0[i][4];
         assign lo1[i] = cmo1[i][4];
         assign lo2[i] = cmo2[i][4];
         assign lo3[i] = cmo3[i][4];
         assign cmoa[i][4] = loa[i];
         assign cmoa[i][4] = loa4[i];
 
      end
   endgenerate
 
 
endmodule // clos

Browse

Tools

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [branches/] [clos_opt/] [clos_opt/] [src/] [clos_buf.v] - Blame information for rev 72

Line No.	Rev	Author	Line
1	71	wsong0210	`/*`
2			`Asynchronous SDM NoC`
3			`(C)2011 Wei Song`
4			`Advanced Processor Technologies Group`
5			`Computer Science, the Univ. of Manchester, UK`
6
7			`Authors:`
8			`Wei Song wsong83@gmail.com`
9
10			`License: LGPL 3.0 or later`
11
12			`Buffered Clos switch for SDM-Clos routers`
13			`* SystemVerilog is used *`
14
15			`History:`
16			`09/07/2011 Initial version. <wsong83@gmail.com>`
17
18			`*/`
19
20			`// the router structure definitions`
21			`include "define.v"
22
23			`module clos (/AUTOARG/);`
24
25			`parameter MN = 2; // number of CMs`
26			`parameter NN = 2; // number of ports in an IM or OM, equ. to number of virtual circuits`
27			`parameter DW = 8; // datawidth of a single virtual circuit/port`
28			`parameter SCN = DW/2; // number of 1-of-4 sub-channels in one port`
29
30			`input [NN-1:0][SCN-1:0] si0, si1, si2, si3; // south input [0], X+1`
31			`input [NN-1:0][SCN-1:0] wi0, wi1, wi2, wi3; // west input [1], Y-1`
32			`input [NN-1:0][SCN-1:0] ni0, ni1, ni2, ni3; // north input [2], X-1`
33			`input [NN-1:0][SCN-1:0] ei0, ei1, ei2, ei3; // east input [3], Y+1`
34			`input [NN-1:0][SCN-1:0] li0, li1, li2, li3; // local input`
35			`output [NN-1:0][SCN-1:0] so0, so1, so2, so3; // south output`
36			`output [NN-1:0][SCN-1:0] wo0, wo1, wo2, wo3; // west output`
37			`output [NN-1:0][SCN-1:0] no0, no1, no2, no3; // north output`
38			`output [NN-1:0][SCN-1:0] eo0, eo1, eo2, eo3; // east output`
39			`output [NN-1:0][SCN-1:0] lo0, lo1, lo2, lo3; // local output`
40
41			`// eof bits and ack lines`
42			`ifdef ENABLE_CHANNEL_SLICING
43			`input [NN-1:0][SCN-1:0] si4, wi4, ni4, ei4, li4;`
44			`output [NN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4;`
45			`output [NN-1:0][SCN-1:0] sia, wia, nia, eia, lia;`
46			`input [NN-1:0][SCN-1:0] soa, woa, noa, eoa, loa;`
47			`ifdef ENABLE_BUFFERED_CLOS
48			`input [NN-1:0][SCN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers`
49			`endif
50			`else
51			`input [NN-1:0] si4, wi4, ni4, ei4, li4;`
52			`output [NN-1:0] so4, wo4, no4, eo4, lo4;`
53			`output [NN-1:0] sia, wia, nia, eia, lia;`
54			`input [NN-1:0] soa, woa, noa, eoa, loa;`
55			`ifdef ENABLE_BUFFERED_CLOS
56			`input [NN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers`
57			`endif
58			`endif // !`ifdef ENABLE_CHANNEL_SLICING
59
60			`input [NN-1:0][3:0] sdec, ndec, ldec; // the routing requests`
61			`input [NN-1:0][1:0] wdec, edec; // the routing requests`
62
63			`genvar i,j;`
64
65
66			`// the IMs`
67			`im #(.MN(MN), .NN(NN), .DW(DW), .SN(4))`
68			`SIM (`
69			`.do0 ( sim0 ),`
70			`.do1 ( sim1 ),`
71			`.do2 ( sim2 ),`
72			`.do3 ( sim3 ),`
73			`.deco ( simdec ),`
74			`.dia ( sia ),`
75			`.do4 ( sim4 ),`
76			`.di0 ( si0 ),`
77			`.di1 ( si1 ),`
78			`.di2 ( si2 ),`
79			`.di3 ( si3 ),`
80			`.deci ( sdec ),`
81			`.di4 ( si4 ),`
82			`.doa ( sima ),`
83			`ifndef ENABLE_CRRD
84			`.cms ( sims ),`
85			`endif
86			`.rst_n ( rst_n )`
87			`);`
88
89			`im #(.MN(MN), .NN(NN), .DW(DW), .SN(2))`
90			`WIM (`
91			`.do0 ( wim0 ),`
92			`.do1 ( wim1 ),`
93			`.do2 ( wim2 ),`
94			`.do3 ( wim3 ),`
95			`.deco ( wimdec ),`
96			`.dia ( wia ),`
97			`.do4 ( wim4 ),`
98			`.di0 ( wi0 ),`
99			`.di1 ( wi1 ),`
100			`.di2 ( wi2 ),`
101			`.di3 ( wi3 ),`
102			`.deci ( wdec ),`
103			`.di4 ( wi4 ),`
104			`.doa ( wima ),`
105			`ifndef ENABLE_CRRD
106			`.cms ( wims ),`
107			`endif
108			`.rst_n ( rst_n )`
109			`);`
110
111			`im #(.MN(MN), .NN(NN), .DW(DW), .SN(4))`
112			`NIM (`
113			`.do0 ( nim0 ),`
114			`.do1 ( nim1 ),`
115			`.do2 ( nim2 ),`
116			`.do3 ( nim3 ),`
117			`.deco ( nimdec ),`
118			`.dia ( nia ),`
119			`.do4 ( nim4 ),`
120			`.di0 ( ni0 ),`
121			`.di1 ( ni1 ),`
122			`.di2 ( ni2 ),`
123			`.di3 ( ni3 ),`
124			`.deci ( ndec ),`
125			`.di4 ( ni4 ),`
126			`.doa ( nima ),`
127			`ifndef ENABLE_CRRD
128			`.cms ( nims ),`
129			`endif
130			`.rst_n ( rst_n )`
131			`);`
132
133			`im #(.MN(MN), .NN(NN), .DW(DW), .SN(2))`
134			`EIM (`
135			`.do0 ( eim0 ),`
136			`.do1 ( eim1 ),`
137			`.do2 ( eim2 ),`
138			`.do3 ( eim3 ),`
139			`.deco ( eimdec ),`
140			`.dia ( eia ),`
141			`.do4 ( eim4 ),`
142			`.di0 ( ei0 ),`
143			`.di1 ( ei1 ),`
144			`.di2 ( ei2 ),`
145			`.di3 ( ei3 ),`
146			`.deci ( edec ),`
147			`.di4 ( ei4 ),`
148			`.doa ( eima ),`
149			`ifndef ENABLE_CRRD
150			`.cms ( eims ),`
151			`endif
152			`.rst_n ( rst_n )`
153			`);`
154
155			`im #(.MN(MN), .NN(NN), .DW(DW), .SN(4))`
156			`LIM (`
157			`.do0 ( lim0 ),`
158			`.do1 ( lim1 ),`
159			`.do2 ( lim2 ),`
160			`.do3 ( lim3 ),`
161			`.deco ( limdec ),`
162			`.dia ( lia ),`
163			`.do4 ( lim4 ),`
164			`.di0 ( li0 ),`
165			`.di1 ( li1 ),`
166			`.di2 ( li2 ),`
167			`.di3 ( li3 ),`
168			`.deci ( ldec ),`
169			`.di4 ( li4 ),`
170			`.doa ( lima ),`
171			`ifndef ENABLE_CRRD
172			`.cms ( lims ),`
173			`endif
174			`.rst_n ( rst_n )`
175			`);`
176
177			`// data wire shuffle`
178			`// the CMs`
179			`generate`
180			`for(i=0; i<MN; i++) begin:CMSH`
181			`assign cmi0[i][0] = sim0[i];`
182			`assign cmi1[i][0] = sim1[i];`
183			`assign cmi2[i][0] = sim2[i];`
184			`assign cmi3[i][0] = sim3[i];`
185			`assign sima[i] = cmia[i][0];`
186			`assign sima4[i] = cmia[i][0];`
187
188			`assign cmi0[i][1] = wim0[i];`
189			`assign cmi1[i][1] = wim1[i];`
190			`assign cmi2[i][1] = wim2[i];`
191			`assign cmi3[i][1] = wim3[i];`
192			`assign wima[i] = cmia[i][1];`
193			`assign wima4[i] = cmia[i][1];`
194
195			`assign cmi0[i][2] = nim0[i];`
196			`assign cmi1[i][2] = nim1[i];`
197			`assign cmi2[i][2] = nim2[i];`
198			`assign cmi3[i][2] = nim3[i];`
199			`assign nima[i] = cmia[i][2];`
200			`assign nima4[i] = cmia[i][2];`
201
202			`assign cmi0[i][3] = eim0[i];`
203			`assign cmi1[i][3] = eim1[i];`
204			`assign cmi2[i][3] = eim2[i];`
205			`assign cmi3[i][3] = eim3[i];`
206			`assign eima[i] = cmia[i][3];`
207			`assign eima4[i] = cmia[i][3];`
208
209			`assign cmi0[i][4] = lim0[i];`
210			`assign cmi1[i][4] = lim1[i];`
211			`assign cmi2[i][4] = lim2[i];`
212			`assign cmi3[i][4] = lim3[i];`
213			`assign lima[i] = cmia[i][4];`
214			`assign lima4[i] = cmia[i][4];`
215
216			`cm #(.KN(5), .DW(DW))`
217			`CMSW (`
218			`.do0 ( cmo0[i] ),`
219			`.do1 ( cmo1[i] ),`
220			`.do2 ( cmo2[i] ),`
221			`.do3 ( cmo3[i] ),`
222			`.dia ( cmia[i] ),`
223			`.do4 ( cmo4[i] ),`
224			`.di0 ( cmi0[i] ),`
225			`.di1 ( cmi1[i] ),`
226			`.di2 ( cmi2[i] ),`
227			`.di3 ( cmi3[i] ),`
228			`.sdec ( sdec[i] ),`
229			`.ndec ( ndec[i] ),`
230			`.ldec ( ldec[i] ),`
231			`.wdec ( wdec[i] ),`
232			`.edec ( edec[i] ),`
233			`.di4 ( cmi4[i] ),`
234			`.doa ( cmoa[i] ),`
235			`.doa4 ( cmoa4[i] ),`
236			`ifndef ENABLE_CRRD
237			`.cms ( cms[i] ),`
238			`endif
239			`.rst_n ( rst_n )`
240			`);`
241
242	72	wsong0210	`assign so0[i] = cmo0[i][0];`
243			`assign so1[i] = cmo1[i][0];`
244			`assign so2[i] = cmo2[i][0];`
245			`assign so3[i] = cmo3[i][0];`
246			`assign cmoa[i][0] = soa[i];`
247			`assign cmoa[i][0] = soa4[i];`
248
249			`assign wo0[i] = cmo0[i][1];`
250			`assign wo1[i] = cmo1[i][1];`
251			`assign wo2[i] = cmo2[i][1];`
252			`assign wo3[i] = cmo3[i][1];`
253			`assign cmoa[i][1] = woa[i];`
254			`assign cmoa[i][1] = woa4[i];`
255
256			`assign no0[i] = cmo0[i][2];`
257			`assign no1[i] = cmo1[i][2];`
258			`assign no2[i] = cmo2[i][2];`
259			`assign no3[i] = cmo3[i][2];`
260			`assign cmoa[i][2] = noa[i];`
261			`assign cmoa[i][2] = noa4[i];`
262
263			`assign eo0[i] = cmo0[i][3];`
264			`assign eo1[i] = cmo1[i][3];`
265			`assign eo2[i] = cmo2[i][3];`
266			`assign eo3[i] = cmo3[i][3];`
267			`assign cmoa[i][3] = eoa[i];`
268			`assign cmoa[i][3] = eoa4[i];`
269
270			`assign lo0[i] = cmo0[i][4];`
271			`assign lo1[i] = cmo1[i][4];`
272			`assign lo2[i] = cmo2[i][4];`
273			`assign lo3[i] = cmo3[i][4];`
274			`assign cmoa[i][4] = loa[i];`
275			`assign cmoa[i][4] = loa4[i];`
276
277			`end`
278			`endgenerate`
279	71	wsong0210
280	72	wsong0210
281			`endmodule // clos`