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/*
 Asynchronous SDM NoC
 (C)2011 Wei Song
 Advanced Processor Technologies Group
 Computer Science, the Univ. of Manchester, UK
 
 Authors:
 Wei Song     wsong83@gmail.com
 
 License: LGPL 3.0 or later
 
 Buffered Clos switch for SDM-Clos routers
 *** SystemVerilog is used ***
 
 History:
 09/07/2011  Initial version. <wsong83@gmail.com>
 
*/
 
// the router structure definitions
`include "define.v"
 
module clos (/*AUTOARG*/
   // Outputs
   so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
   eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
   wia, nia, eia, lia,
   // Inputs
   si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
   ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
   woa, noa, eoa, loa, soa4, woa4, noa4, eoa4, loa4, sdec, ndec, ldec,
   wdec, edec
   );
 
   parameter MN = 2;            // number of CMs
   parameter NN = 2;            // number of ports in an IM or OM, equ. to number of virtual circuits
   parameter DW = 8;            // datawidth of a single virtual circuit/port
   parameter SCN = DW/2;        // number of 1-of-4 sub-channels in one port
 
   input [NN-1:0][SCN-1:0]     si0, si1, si2, si3; // south input [0], X+1
   input [NN-1:0][SCN-1:0]     wi0, wi1, wi2, wi3; // west input [1], Y-1
   input [NN-1:0][SCN-1:0]     ni0, ni1, ni2, ni3; // north input [2], X-1
   input [NN-1:0][SCN-1:0]     ei0, ei1, ei2, ei3; // east input [3], Y+1
   input [NN-1:0][SCN-1:0]     li0, li1, li2, li3; // local input
   output [NN-1:0][SCN-1:0]    so0, so1, so2, so3; // south output
   output [NN-1:0][SCN-1:0]    wo0, wo1, wo2, wo3; // west output
   output [NN-1:0][SCN-1:0]    no0, no1, no2, no3; // north output
   output [NN-1:0][SCN-1:0]    eo0, eo1, eo2, eo3; // east output
   output [NN-1:0][SCN-1:0]    lo0, lo1, lo2, lo3; // local output
 
   // eof bits and ack lines
`ifdef ENABLE_CHANNEL_SLICING
   input [NN-1:0][SCN-1:0]     si4, wi4, ni4, ei4, li4;
   output [NN-1:0][SCN-1:0]    so4, wo4, no4, eo4, lo4;
   output [NN-1:0][SCN-1:0]    sia, wia, nia, eia, lia;
   input [NN-1:0][SCN-1:0]     soa, woa, noa, eoa, loa;
// `ifdef ENABLE_BUFFERED_CLOS
   input [NN-1:0][SCN-1:0]     soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
// `endif
`else
   input [NN-1:0]               si4, wi4, ni4, ei4, li4;
   output [NN-1:0]              so4, wo4, no4, eo4, lo4;
   output [NN-1:0]              sia, wia, nia, eia, lia;
   input [NN-1:0]               soa, woa, noa, eoa, loa;
// `ifdef ENABLE_BUFFERED_CLOS
   input [NN-1:0]               soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
// `endif
`endif // !`ifdef ENABLE_CHANNEL_SLICING
 
   input [NN-1:0][3:0]           sdec, ndec, ldec; // the routing requests
   input [NN-1:0][1:0]         wdec, edec;         // the routing requests
 
   genvar                      i,j;
 
 
   // the IMs
   im #(.MN(MN), .NN(NN), .DW(DW), .SN(4))
   SIM (
        .do0   ( sim0   ),
        .do1   ( sim1   ),
        .do2   ( sim2   ),
        .do3   ( sim3   ),
        .deco  ( simdec ),
        .dia   ( sia    ),
        .do4   ( sim4   ),
        .di0   ( si0    ),
        .di1   ( si1    ),
        .di2   ( si2    ),
        .di3   ( si3    ),
        .deci  ( sdec   ),
        .di4   ( si4    ),
        .doa   ( sima   ),
`ifndef ENABLE_CRRD
        .cms   ( sims   ),
`endif
        .rst_n ( rst_n  )
        );
 
   im #(.MN(MN), .NN(NN), .DW(DW), .SN(2))
   WIM (
        .do0   ( wim0   ),
        .do1   ( wim1   ),
        .do2   ( wim2   ),
        .do3   ( wim3   ),
        .deco  ( wimdec ),
        .dia   ( wia    ),
        .do4   ( wim4   ),
        .di0   ( wi0    ),
        .di1   ( wi1    ),
        .di2   ( wi2    ),
        .di3   ( wi3    ),
        .deci  ( wdec   ),
        .di4   ( wi4    ),
        .doa   ( wima   ),
`ifndef ENABLE_CRRD
        .cms   ( wims   ),
`endif
        .rst_n ( rst_n  )
        );
 
   im #(.MN(MN), .NN(NN), .DW(DW), .SN(4))
   NIM (
        .do0   ( nim0   ),
        .do1   ( nim1   ),
        .do2   ( nim2   ),
        .do3   ( nim3   ),
        .deco  ( nimdec ),
        .dia   ( nia    ),
        .do4   ( nim4   ),
        .di0   ( ni0    ),
        .di1   ( ni1    ),
        .di2   ( ni2    ),
        .di3   ( ni3    ),
        .deci  ( ndec   ),
        .di4   ( ni4    ),
        .doa   ( nima   ),
`ifndef ENABLE_CRRD
        .cms   ( nims   ),
`endif
        .rst_n ( rst_n  )
        );
 
   im #(.MN(MN), .NN(NN), .DW(DW), .SN(2))
   EIM (
        .do0   ( eim0   ),
        .do1   ( eim1   ),
        .do2   ( eim2   ),
        .do3   ( eim3   ),
        .deco  ( eimdec ),
        .dia   ( eia    ),
        .do4   ( eim4   ),
        .di0   ( ei0    ),
        .di1   ( ei1    ),
        .di2   ( ei2    ),
        .di3   ( ei3    ),
        .deci  ( edec   ),
        .di4   ( ei4    ),
        .doa   ( eima   ),
`ifndef ENABLE_CRRD
        .cms   ( eims   ),
`endif
        .rst_n ( rst_n  )
        );
 
   im #(.MN(MN), .NN(NN), .DW(DW), .SN(4))
   LIM (
        .do0   ( lim0   ),
        .do1   ( lim1   ),
        .do2   ( lim2   ),
        .do3   ( lim3   ),
        .deco  ( limdec ),
        .dia   ( lia    ),
        .do4   ( lim4   ),
        .di0   ( li0    ),
        .di1   ( li1    ),
        .di2   ( li2    ),
        .di3   ( li3    ),
        .deci  ( ldec   ),
        .di4   ( li4    ),
        .doa   ( lima   ),
`ifndef ENABLE_CRRD
        .cms   ( lims   ),
`endif
        .rst_n ( rst_n  )
        );
 
   // data wire shuffle
   // the CMs
   generate
      for(i=0; i<MN; i++) begin:CMSH
         assign cmi0[i][0] = sim0[i];
         assign cmi1[i][0] = sim1[i];
         assign cmi2[i][0] = sim2[i];
         assign cmi3[i][0] = sim3[i];
         assign sima[i] = cmia[i][0];
         assign sima4[i] = cmia[i][0];
 
         assign cmi0[i][1] = wim0[i];
         assign cmi1[i][1] = wim1[i];
         assign cmi2[i][1] = wim2[i];
         assign cmi3[i][1] = wim3[i];
         assign wima[i] = cmia[i][1];
         assign wima4[i] = cmia[i][1];
 
         assign cmi0[i][2] = nim0[i];
         assign cmi1[i][2] = nim1[i];
         assign cmi2[i][2] = nim2[i];
         assign cmi3[i][2] = nim3[i];
         assign nima[i] = cmia[i][2];
         assign nima4[i] = cmia[i][2];
 
         assign cmi0[i][3] = eim0[i];
         assign cmi1[i][3] = eim1[i];
         assign cmi2[i][3] = eim2[i];
         assign cmi3[i][3] = eim3[i];
         assign eima[i] = cmia[i][3];
         assign eima4[i] = cmia[i][3];
 
         assign cmi0[i][4] = lim0[i];
         assign cmi1[i][4] = lim1[i];
         assign cmi2[i][4] = lim2[i];
         assign cmi3[i][4] = lim3[i];
         assign lima[i] = cmia[i][4];
         assign lima4[i] = cmia[i][4];
 
         cm #(.KN(5), .DW(DW))
         CMSW (
               .do0   ( cmo0[i]  ),
               .do1   ( cmo1[i]  ),
               .do2   ( cmo2[i]  ),
               .do3   ( cmo3[i]  ),
               .dia   ( cmia[i]  ),
               .do4   ( cmo4[i]  ),
               .di0   ( cmi0[i]  ),
               .di1   ( cmi1[i]  ),
               .di2   ( cmi2[i]  ),
               .di3   ( cmi3[i]  ),
               .sdec  ( sdec[i]  ),
               .ndec  ( ndec[i]  ),
               .ldec  ( ldec[i]  ),
               .wdec  ( wdec[i]  ),
               .edec  ( edec[i]  ),
               .di4   ( cmi4[i]  ),
               .doa   ( cmoa[i]  ),
               .doa4  ( cmoa4[i] ),
`ifndef ENABLE_CRRD
               .cms   ( cms[i]   ),
`endif
               .rst_n ( rst_n    )
               );
 
         assign so0[i] = cmo0[i][0];
         assign so1[i] = cmo1[i][0];
         assign so2[i] = cmo2[i][0];
         assign so3[i] = cmo3[i][0];
         assign cmoa[i][0] = soa[i];
         assign cmoa[i][0] = soa4[i];
 
         assign wo0[i] = cmo0[i][1];
         assign wo1[i] = cmo1[i][1];
         assign wo2[i] = cmo2[i][1];
         assign wo3[i] = cmo3[i][1];
         assign cmoa[i][1] = woa[i];
         assign cmoa[i][1] = woa4[i];
 
         assign no0[i] = cmo0[i][2];
         assign no1[i] = cmo1[i][2];
         assign no2[i] = cmo2[i][2];
         assign no3[i] = cmo3[i][2];
         assign cmoa[i][2] = noa[i];
         assign cmoa[i][2] = noa4[i];
 
         assign eo0[i] = cmo0[i][3];
         assign eo1[i] = cmo1[i][3];
         assign eo2[i] = cmo2[i][3];
         assign eo3[i] = cmo3[i][3];
         assign cmoa[i][3] = eoa[i];
         assign cmoa[i][3] = eoa4[i];
 
         assign lo0[i] = cmo0[i][4];
         assign lo1[i] = cmo1[i][4];
         assign lo2[i] = cmo2[i][4];
         assign lo3[i] = cmo3[i][4];
         assign cmoa[i][4] = loa[i];
         assign cmoa[i][4] = loa4[i];
 
      end
   endgenerate
 
 
endmodule // clos

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[/] [async_sdm_noc/] [branches/] [clos_opt/] [clos_opt/] [src/] [clos_buf.v] - Blame information for rev 74

Line No.	Rev	Author	Line
1	71	wsong0210	`/*`
2			`Asynchronous SDM NoC`
3			`(C)2011 Wei Song`
4			`Advanced Processor Technologies Group`
5			`Computer Science, the Univ. of Manchester, UK`
6
7			`Authors:`
8			`Wei Song wsong83@gmail.com`
9
10			`License: LGPL 3.0 or later`
11
12			`Buffered Clos switch for SDM-Clos routers`
13			`* SystemVerilog is used *`
14
15			`History:`
16			`09/07/2011 Initial version. <wsong83@gmail.com>`
17
18			`*/`
19
20			`// the router structure definitions`
21			`include "define.v"
22
23	74	wsong0210	`module clos (/AUTOARG/`
24			`// Outputs`
25			`so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,`
26			`eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,`
27			`wia, nia, eia, lia,`
28			`// Inputs`
29			`si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,`
30			`ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,`
31			`woa, noa, eoa, loa, soa4, woa4, noa4, eoa4, loa4, sdec, ndec, ldec,`
32			`wdec, edec`
33			`);`
34	71	wsong0210
35			`parameter MN = 2; // number of CMs`
36			`parameter NN = 2; // number of ports in an IM or OM, equ. to number of virtual circuits`
37			`parameter DW = 8; // datawidth of a single virtual circuit/port`
38			`parameter SCN = DW/2; // number of 1-of-4 sub-channels in one port`
39
40			`input [NN-1:0][SCN-1:0] si0, si1, si2, si3; // south input [0], X+1`
41			`input [NN-1:0][SCN-1:0] wi0, wi1, wi2, wi3; // west input [1], Y-1`
42			`input [NN-1:0][SCN-1:0] ni0, ni1, ni2, ni3; // north input [2], X-1`
43			`input [NN-1:0][SCN-1:0] ei0, ei1, ei2, ei3; // east input [3], Y+1`
44			`input [NN-1:0][SCN-1:0] li0, li1, li2, li3; // local input`
45			`output [NN-1:0][SCN-1:0] so0, so1, so2, so3; // south output`
46			`output [NN-1:0][SCN-1:0] wo0, wo1, wo2, wo3; // west output`
47			`output [NN-1:0][SCN-1:0] no0, no1, no2, no3; // north output`
48			`output [NN-1:0][SCN-1:0] eo0, eo1, eo2, eo3; // east output`
49			`output [NN-1:0][SCN-1:0] lo0, lo1, lo2, lo3; // local output`
50
51			`// eof bits and ack lines`
52			`ifdef ENABLE_CHANNEL_SLICING
53			`input [NN-1:0][SCN-1:0] si4, wi4, ni4, ei4, li4;`
54			`output [NN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4;`
55			`output [NN-1:0][SCN-1:0] sia, wia, nia, eia, lia;`
56			`input [NN-1:0][SCN-1:0] soa, woa, noa, eoa, loa;`
57	74	wsong0210	// `ifdef ENABLE_BUFFERED_CLOS
58	71	wsong0210	`input [NN-1:0][SCN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers`
59	74	wsong0210	// `endif
60	71	wsong0210	`else
61			`input [NN-1:0] si4, wi4, ni4, ei4, li4;`
62			`output [NN-1:0] so4, wo4, no4, eo4, lo4;`
63			`output [NN-1:0] sia, wia, nia, eia, lia;`
64			`input [NN-1:0] soa, woa, noa, eoa, loa;`
65	74	wsong0210	// `ifdef ENABLE_BUFFERED_CLOS
66	71	wsong0210	`input [NN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers`
67	74	wsong0210	// `endif
68	71	wsong0210	`endif // !`ifdef ENABLE_CHANNEL_SLICING
69
70			`input [NN-1:0][3:0] sdec, ndec, ldec; // the routing requests`
71			`input [NN-1:0][1:0] wdec, edec; // the routing requests`
72
73			`genvar i,j;`
74
75
76			`// the IMs`
77			`im #(.MN(MN), .NN(NN), .DW(DW), .SN(4))`
78			`SIM (`
79			`.do0 ( sim0 ),`
80			`.do1 ( sim1 ),`
81			`.do2 ( sim2 ),`
82			`.do3 ( sim3 ),`
83			`.deco ( simdec ),`
84			`.dia ( sia ),`
85			`.do4 ( sim4 ),`
86			`.di0 ( si0 ),`
87			`.di1 ( si1 ),`
88			`.di2 ( si2 ),`
89			`.di3 ( si3 ),`
90			`.deci ( sdec ),`
91			`.di4 ( si4 ),`
92			`.doa ( sima ),`
93			`ifndef ENABLE_CRRD
94			`.cms ( sims ),`
95			`endif
96			`.rst_n ( rst_n )`
97			`);`
98
99			`im #(.MN(MN), .NN(NN), .DW(DW), .SN(2))`
100			`WIM (`
101			`.do0 ( wim0 ),`
102			`.do1 ( wim1 ),`
103			`.do2 ( wim2 ),`
104			`.do3 ( wim3 ),`
105			`.deco ( wimdec ),`
106			`.dia ( wia ),`
107			`.do4 ( wim4 ),`
108			`.di0 ( wi0 ),`
109			`.di1 ( wi1 ),`
110			`.di2 ( wi2 ),`
111			`.di3 ( wi3 ),`
112			`.deci ( wdec ),`
113			`.di4 ( wi4 ),`
114			`.doa ( wima ),`
115			`ifndef ENABLE_CRRD
116			`.cms ( wims ),`
117			`endif
118			`.rst_n ( rst_n )`
119			`);`
120
121			`im #(.MN(MN), .NN(NN), .DW(DW), .SN(4))`
122			`NIM (`
123			`.do0 ( nim0 ),`
124			`.do1 ( nim1 ),`
125			`.do2 ( nim2 ),`
126			`.do3 ( nim3 ),`
127			`.deco ( nimdec ),`
128			`.dia ( nia ),`
129			`.do4 ( nim4 ),`
130			`.di0 ( ni0 ),`
131			`.di1 ( ni1 ),`
132			`.di2 ( ni2 ),`
133			`.di3 ( ni3 ),`
134			`.deci ( ndec ),`
135			`.di4 ( ni4 ),`
136			`.doa ( nima ),`
137			`ifndef ENABLE_CRRD
138			`.cms ( nims ),`
139			`endif
140			`.rst_n ( rst_n )`
141			`);`
142
143			`im #(.MN(MN), .NN(NN), .DW(DW), .SN(2))`
144			`EIM (`
145			`.do0 ( eim0 ),`
146			`.do1 ( eim1 ),`
147			`.do2 ( eim2 ),`
148			`.do3 ( eim3 ),`
149			`.deco ( eimdec ),`
150			`.dia ( eia ),`
151			`.do4 ( eim4 ),`
152			`.di0 ( ei0 ),`
153			`.di1 ( ei1 ),`
154			`.di2 ( ei2 ),`
155			`.di3 ( ei3 ),`
156			`.deci ( edec ),`
157			`.di4 ( ei4 ),`
158			`.doa ( eima ),`
159			`ifndef ENABLE_CRRD
160			`.cms ( eims ),`
161			`endif
162			`.rst_n ( rst_n )`
163			`);`
164
165			`im #(.MN(MN), .NN(NN), .DW(DW), .SN(4))`
166			`LIM (`
167			`.do0 ( lim0 ),`
168			`.do1 ( lim1 ),`
169			`.do2 ( lim2 ),`
170			`.do3 ( lim3 ),`
171			`.deco ( limdec ),`
172			`.dia ( lia ),`
173			`.do4 ( lim4 ),`
174			`.di0 ( li0 ),`
175			`.di1 ( li1 ),`
176			`.di2 ( li2 ),`
177			`.di3 ( li3 ),`
178			`.deci ( ldec ),`
179			`.di4 ( li4 ),`
180			`.doa ( lima ),`
181			`ifndef ENABLE_CRRD
182			`.cms ( lims ),`
183			`endif
184			`.rst_n ( rst_n )`
185			`);`
186
187			`// data wire shuffle`
188			`// the CMs`
189			`generate`
190			`for(i=0; i<MN; i++) begin:CMSH`
191			`assign cmi0[i][0] = sim0[i];`
192			`assign cmi1[i][0] = sim1[i];`
193			`assign cmi2[i][0] = sim2[i];`
194			`assign cmi3[i][0] = sim3[i];`
195			`assign sima[i] = cmia[i][0];`
196			`assign sima4[i] = cmia[i][0];`
197
198			`assign cmi0[i][1] = wim0[i];`
199			`assign cmi1[i][1] = wim1[i];`
200			`assign cmi2[i][1] = wim2[i];`
201			`assign cmi3[i][1] = wim3[i];`
202			`assign wima[i] = cmia[i][1];`
203			`assign wima4[i] = cmia[i][1];`
204
205			`assign cmi0[i][2] = nim0[i];`
206			`assign cmi1[i][2] = nim1[i];`
207			`assign cmi2[i][2] = nim2[i];`
208			`assign cmi3[i][2] = nim3[i];`
209			`assign nima[i] = cmia[i][2];`
210			`assign nima4[i] = cmia[i][2];`
211
212			`assign cmi0[i][3] = eim0[i];`
213			`assign cmi1[i][3] = eim1[i];`
214			`assign cmi2[i][3] = eim2[i];`
215			`assign cmi3[i][3] = eim3[i];`
216			`assign eima[i] = cmia[i][3];`
217			`assign eima4[i] = cmia[i][3];`
218
219			`assign cmi0[i][4] = lim0[i];`
220			`assign cmi1[i][4] = lim1[i];`
221			`assign cmi2[i][4] = lim2[i];`
222			`assign cmi3[i][4] = lim3[i];`
223			`assign lima[i] = cmia[i][4];`
224			`assign lima4[i] = cmia[i][4];`
225
226			`cm #(.KN(5), .DW(DW))`
227			`CMSW (`
228			`.do0 ( cmo0[i] ),`
229			`.do1 ( cmo1[i] ),`
230			`.do2 ( cmo2[i] ),`
231			`.do3 ( cmo3[i] ),`
232			`.dia ( cmia[i] ),`
233			`.do4 ( cmo4[i] ),`
234			`.di0 ( cmi0[i] ),`
235			`.di1 ( cmi1[i] ),`
236			`.di2 ( cmi2[i] ),`
237			`.di3 ( cmi3[i] ),`
238			`.sdec ( sdec[i] ),`
239			`.ndec ( ndec[i] ),`
240			`.ldec ( ldec[i] ),`
241			`.wdec ( wdec[i] ),`
242			`.edec ( edec[i] ),`
243			`.di4 ( cmi4[i] ),`
244			`.doa ( cmoa[i] ),`
245			`.doa4 ( cmoa4[i] ),`
246			`ifndef ENABLE_CRRD
247			`.cms ( cms[i] ),`
248			`endif
249			`.rst_n ( rst_n )`
250			`);`
251
252	72	wsong0210	`assign so0[i] = cmo0[i][0];`
253			`assign so1[i] = cmo1[i][0];`
254			`assign so2[i] = cmo2[i][0];`
255			`assign so3[i] = cmo3[i][0];`
256			`assign cmoa[i][0] = soa[i];`
257			`assign cmoa[i][0] = soa4[i];`
258
259			`assign wo0[i] = cmo0[i][1];`
260			`assign wo1[i] = cmo1[i][1];`
261			`assign wo2[i] = cmo2[i][1];`
262			`assign wo3[i] = cmo3[i][1];`
263			`assign cmoa[i][1] = woa[i];`
264			`assign cmoa[i][1] = woa4[i];`
265
266			`assign no0[i] = cmo0[i][2];`
267			`assign no1[i] = cmo1[i][2];`
268			`assign no2[i] = cmo2[i][2];`
269			`assign no3[i] = cmo3[i][2];`
270			`assign cmoa[i][2] = noa[i];`
271			`assign cmoa[i][2] = noa4[i];`
272
273			`assign eo0[i] = cmo0[i][3];`
274			`assign eo1[i] = cmo1[i][3];`
275			`assign eo2[i] = cmo2[i][3];`
276			`assign eo3[i] = cmo3[i][3];`
277			`assign cmoa[i][3] = eoa[i];`
278			`assign cmoa[i][3] = eoa4[i];`
279
280			`assign lo0[i] = cmo0[i][4];`
281			`assign lo1[i] = cmo1[i][4];`
282			`assign lo2[i] = cmo2[i][4];`
283			`assign lo3[i] = cmo3[i][4];`
284			`assign cmoa[i][4] = loa[i];`
285			`assign cmoa[i][4] = loa4[i];`
286
287			`end`
288			`endgenerate`
289	71	wsong0210
290	72	wsong0210
291			`endmodule // clos`