URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [branches/] [clos_opt/] [clos_opt/] [src/] [cm.v] - Blame information for rev 78

Details | Compare with Previous | View Log


/*
 Asynchronous SDM NoC
 (C)2011 Wei Song
 Advanced Processor Technologies Group
 Computer Science, the Univ. of Manchester, UK
 
 Authors:
 Wei Song     wsong83@gmail.com
 
 License: LGPL 3.0 or later
 
 A CM of a buffered Clos for SDM-Clos routers
 *** SystemVerilog is used ***
 
 History:
 08/07/2011  Initial version. <wsong83@gmail.com>
 
*/
 
// the router structure definitions
`include "define.v"
 
module cm (
   // Outputs
   do0, do1, do2, do3, dia, do4,
   // Inputs
   di0, di1, di2, di3, sdec, ndec, ldec, wdec, edec, di4, doa, doa4,
`ifndef ENABLE_CRRD
   cms,
`endif
   rst_n
   );
 
   parameter KN = 5;           // dummy parameter, the number of IMs
   parameter DW = 8;           // the data width of each IP
   parameter SCN = DW/2;       // the number of sub-channels in one IP
 
   input [KN-1:0][SCN-1:0]    di0, di1, di2, di3;      // input data
   input [3:0]                 sdec, ndec, ldec;        // the decoded direction requests
   input [1:0]                 wdec, edec;              // the decoded direction requests
   output [KN-1:0][SCN-1:0]   do0, do1, do2, do3;      // output data
 
`ifdef ENABLE_CHANNEL_SLICING
   input [KN-1:0][SCN-1:0]    di4;                     // data input
   output [KN-1:0][SCN-1:0]   dia;                       // input ack
   output [KN-1:0][SCN-1:0]   do4;                       // data output
   input [KN-1:0][SCN-1:0]    doa, doa4;         // output ack
`else
   input [KN-1:0]              di4;                     // data input
   output [KN-1:0]             dia;                     // input ack
   output [KN-1:0]             do4;                     // data output
   input [KN-1:0]              doa, doa4;               // output ack
`endif // !`ifdef ENABLE_CHANNEL_SLICING
 
`ifndef ENABLE_CRRD
   output [KN-1:0]             cms; // the state feedback to IMs
`endif
 
   input                      rst_n; // global active low reset
 
   wire [3:0]                  wcfg, ecfg, lcfg; // switch configuration
   wire [1:0]                  scfg, ncfg;       // switch configuration
 
   genvar                     i, j;
 
   // data switch
   dcb_xy #(.VCN(1), .VCW(DW))
   CMDCB (
          .sia   ( dia[0]    ),
          .wia   ( dia[1]    ),
          .nia   ( dia[2]    ),
          .eia   ( dia[3]    ),
          .lia   ( dia[4]    ),
          .so0   ( do0[0]    ),
          .so1   ( do1[0]    ),
          .so2   ( do2[0]    ),
          .so3   ( do3[0]    ),
          .so4   ( do4[0]    ),
          .wo0   ( do0[1]    ),
          .wo1   ( do1[1]    ),
          .wo2   ( do2[1]    ),
          .wo3   ( do3[1]    ),
          .wo4   ( do4[1]    ),
          .no0   ( do0[2]    ),
          .no1   ( do1[2]    ),
          .no2   ( do2[2]    ),
          .no3   ( do3[2]    ),
          .no4   ( do4[2]    ),
          .eo0   ( do0[3]    ),
          .eo1   ( do1[3]    ),
          .eo2   ( do2[3]    ),
          .eo3   ( do3[3]    ),
          .eo4   ( do4[3]    ),
          .lo0   ( do0[4]    ),
          .lo1   ( do1[4]    ),
          .lo2   ( do2[4]    ),
          .lo3   ( do3[4]    ),
          .lo4   ( do4[4]    ),
          .si0   ( di0[0]    ),
          .si1   ( di1[0]    ),
          .si2   ( di2[0]    ),
          .si3   ( di3[0]    ),
          .si4   ( di4[0]    ),
          .wi0   ( di0[1]    ),
          .wi1   ( di1[1]    ),
          .wi2   ( di2[1]    ),
          .wi3   ( di3[1]    ),
          .wi4   ( di4[1]    ),
          .ni0   ( di0[2]    ),
          .ni1   ( di1[2]    ),
          .ni2   ( di2[2]    ),
          .ni3   ( di3[2]    ),
          .ni4   ( di4[2]    ),
          .ei0   ( di0[3]    ),
          .ei1   ( di1[3]    ),
          .ei2   ( di2[3]    ),
          .ei3   ( di3[3]    ),
          .ei4   ( di4[3]    ),
          .li0   ( di0[4]    ),
          .li1   ( di1[4]    ),
          .li2   ( di2[4]    ),
          .li3   ( di3[4]    ),
          .li4   ( di4[4]    ),
          .soa   ( doa[0]    ),
          .woa   ( doa[1]    ),
          .noa   ( doa[2]    ),
          .eoa   ( doa[3]    ),
          .loa   ( doa[4]    ),
          .soa4  ( doa4[0]   ),
          .woa4  ( doa4[1]   ),
          .noa4  ( doa4[2]   ),
          .eoa4  ( doa4[3]   ),
          .loa4  ( doa4[4]   ),
          .wcfg  ( wcfg      ),
          .ecfg  ( ecfg      ),
          .lcfg  ( lcfg      ),
          .scfg  ( scfg      ),
          .ncfg  ( ncfg      )
          );
 
   // the allocator
   cm_alloc CMD (
`ifndef ENABLE_CRRD
                 .s     ( cms   ),
`endif
                 .sra   (       ),
                 .wra   (       ),
                 .nra   (       ),
                 .era   (       ),
                 .lra   (       ),
                 .scfg  ( scfg  ),
                 .ncfg  ( ncfg  ),
                 .wcfg  ( wcfg  ),
                 .ecfg  ( ecfg  ),
                 .lcfg  ( lcfg  ),
                 .sr    ( sdec  ),
                 .wr    ( wdec  ),
                 .nr    ( ndec  ),
                 .er    ( edec  ),
                 .lr    ( ldec  )
                 );
 
endmodule // cm

Line No.	Rev	Author	Line
1	69	wsong0210	`/*`
2			`Asynchronous SDM NoC`
3			`(C)2011 Wei Song`
4			`Advanced Processor Technologies Group`
5			`Computer Science, the Univ. of Manchester, UK`
6
7			`Authors:`
8			`Wei Song wsong83@gmail.com`
9
10			`License: LGPL 3.0 or later`
11
12			`A CM of a buffered Clos for SDM-Clos routers`
13			`* SystemVerilog is used *`
14
15			`History:`
16			`08/07/2011 Initial version. <wsong83@gmail.com>`
17
18			`*/`
19
20			`// the router structure definitions`
21			`include "define.v"
22
23	70	wsong0210	`module cm (`
24	69	wsong0210	`// Outputs`
25			`do0, do1, do2, do3, dia, do4,`
26			`// Inputs`
27			`di0, di1, di2, di3, sdec, ndec, ldec, wdec, edec, di4, doa, doa4,`
28	70	wsong0210	`ifndef ENABLE_CRRD
29			`cms,`
30			`endif
31	69	wsong0210	`rst_n`
32			`);`
33
34			`parameter KN = 5; // dummy parameter, the number of IMs`
35			`parameter DW = 8; // the data width of each IP`
36			`parameter SCN = DW/2; // the number of sub-channels in one IP`
37
38			`input [KN-1:0][SCN-1:0] di0, di1, di2, di3; // input data`
39			`input [3:0] sdec, ndec, ldec; // the decoded direction requests`
40			`input [1:0] wdec, edec; // the decoded direction requests`
41			`output [KN-1:0][SCN-1:0] do0, do1, do2, do3; // output data`
42
43			`ifdef ENABLE_CHANNEL_SLICING
44			`input [KN-1:0][SCN-1:0] di4; // data input`
45			`output [KN-1:0][SCN-1:0] dia; // input ack`
46			`output [KN-1:0][SCN-1:0] do4; // data output`
47			`input [KN-1:0][SCN-1:0] doa, doa4; // output ack`
48			`else
49			`input [KN-1:0] di4; // data input`
50			`output [KN-1:0] dia; // input ack`
51			`output [KN-1:0] do4; // data output`
52			`input [KN-1:0] doa, doa4; // output ack`
53			`endif // !`ifdef ENABLE_CHANNEL_SLICING
54
55			`ifndef ENABLE_CRRD
56			`output [KN-1:0] cms; // the state feedback to IMs`
57			`endif
58
59			`input rst_n; // global active low reset`
60
61			`wire [3:0] wcfg, ecfg, lcfg; // switch configuration`
62			`wire [1:0] scfg, ncfg; // switch configuration`
63
64			`genvar i, j;`
65
66			`// data switch`
67			`dcb_xy #(.VCN(1), .VCW(DW))`
68	70	wsong0210	`CMDCB (`
69	78	wsong0210	`.sia ( dia[0] ),`
70			`.wia ( dia[1] ),`
71			`.nia ( dia[2] ),`
72			`.eia ( dia[3] ),`
73			`.lia ( dia[4] ),`
74			`.so0 ( do0[0] ),`
75			`.so1 ( do1[0] ),`
76			`.so2 ( do2[0] ),`
77			`.so3 ( do3[0] ),`
78			`.so4 ( do4[0] ),`
79			`.wo0 ( do0[1] ),`
80			`.wo1 ( do1[1] ),`
81			`.wo2 ( do2[1] ),`
82			`.wo3 ( do3[1] ),`
83			`.wo4 ( do4[1] ),`
84			`.no0 ( do0[2] ),`
85			`.no1 ( do1[2] ),`
86			`.no2 ( do2[2] ),`
87			`.no3 ( do3[2] ),`
88			`.no4 ( do4[2] ),`
89			`.eo0 ( do0[3] ),`
90			`.eo1 ( do1[3] ),`
91			`.eo2 ( do2[3] ),`
92			`.eo3 ( do3[3] ),`
93			`.eo4 ( do4[3] ),`
94			`.lo0 ( do0[4] ),`
95			`.lo1 ( do1[4] ),`
96			`.lo2 ( do2[4] ),`
97			`.lo3 ( do3[4] ),`
98			`.lo4 ( do4[4] ),`
99			`.si0 ( di0[0] ),`
100			`.si1 ( di1[0] ),`
101			`.si2 ( di2[0] ),`
102			`.si3 ( di3[0] ),`
103			`.si4 ( di4[0] ),`
104			`.wi0 ( di0[1] ),`
105			`.wi1 ( di1[1] ),`
106			`.wi2 ( di2[1] ),`
107			`.wi3 ( di3[1] ),`
108			`.wi4 ( di4[1] ),`
109			`.ni0 ( di0[2] ),`
110			`.ni1 ( di1[2] ),`
111			`.ni2 ( di2[2] ),`
112			`.ni3 ( di3[2] ),`
113			`.ni4 ( di4[2] ),`
114			`.ei0 ( di0[3] ),`
115			`.ei1 ( di1[3] ),`
116			`.ei2 ( di2[3] ),`
117			`.ei3 ( di3[3] ),`
118			`.ei4 ( di4[3] ),`
119			`.li0 ( di0[4] ),`
120			`.li1 ( di1[4] ),`
121			`.li2 ( di2[4] ),`
122			`.li3 ( di3[4] ),`
123			`.li4 ( di4[4] ),`
124			`.soa ( doa[0] ),`
125			`.woa ( doa[1] ),`
126			`.noa ( doa[2] ),`
127			`.eoa ( doa[3] ),`
128			`.loa ( doa[4] ),`
129			`.soa4 ( doa4[0] ),`
130			`.woa4 ( doa4[1] ),`
131			`.noa4 ( doa4[2] ),`
132			`.eoa4 ( doa4[3] ),`
133			`.loa4 ( doa4[4] ),`
134			`.wcfg ( wcfg ),`
135			`.ecfg ( ecfg ),`
136			`.lcfg ( lcfg ),`
137			`.scfg ( scfg ),`
138			`.ncfg ( ncfg )`
139	70	wsong0210	`);`
140	69	wsong0210
141			`// the allocator`
142			`cm_alloc CMD (`
143			`ifndef ENABLE_CRRD
144			`.s ( cms ),`
145			`endif
146			`.sra ( ),`
147			`.wra ( ),`
148			`.nra ( ),`
149			`.era ( ),`
150			`.lra ( ),`
151			`.scfg ( scfg ),`
152			`.ncfg ( ncfg ),`
153			`.wcfg ( wcfg ),`
154			`.ecfg ( ecfg ),`
155			`.lcfg ( lcfg ),`
156			`.sr ( sdec ),`
157			`.wr ( wdec ),`
158			`.nr ( ndec ),`
159			`.er ( edec ),`
160			`.lr ( ldec )`
161			`);`
162
163			`endmodule // cm`

Browse

Tools

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [branches/] [clos_opt/] [clos_opt/] [src/] [cm.v] - Blame information for rev 78