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/*
 Asynchronous SDM NoC
 (C)2011 Wei Song
 Advanced Processor Technologies Group
 Computer Science, the Univ. of Manchester, UK
 
 Authors:
 Wei Song     wsong83@gmail.com
 
 License: LGPL 3.0 or later
 
 A CM of a buffered Clos for SDM-Clos routers
 *** SystemVerilog is used ***
 
 History:
 08/07/2011  Initial version. <wsong83@gmail.com>
 
*/
 
// the router structure definitions
`include "define.v"
 
module cm (/*AUTOARG*/
   // Outputs
   do0, do1, do2, do3, dia, do4,
   // Inputs
   di0, di1, di2, di3, sdec, ndec, ldec, wdec, edec, di4, doa, doa4,
   rst_n
   );
 
   parameter KN = 5;           // dummy parameter, the number of IMs
   parameter DW = 8;           // the data width of each IP
   parameter SCN = DW/2;       // the number of sub-channels in one IP
 
   input [KN-1:0][SCN-1:0]    di0, di1, di2, di3;      // input data
   input [3:0]                 sdec, ndec, ldec;        // the decoded direction requests
   input [1:0]                 wdec, edec;              // the decoded direction requests
   output [KN-1:0][SCN-1:0]   do0, do1, do2, do3;      // output data
 
`ifdef ENABLE_CHANNEL_SLICING
   input [KN-1:0][SCN-1:0]    di4;                     // data input
   output [KN-1:0][SCN-1:0]   dia;                       // input ack
   output [KN-1:0][SCN-1:0]   do4;                       // data output
   input [KN-1:0][SCN-1:0]    doa, doa4;         // output ack
`else
   input [KN-1:0]              di4;                     // data input
   output [KN-1:0]             dia;                     // input ack
   output [KN-1:0]             do4;                     // data output
   input [KN-1:0]              doa, doa4;               // output ack
`endif // !`ifdef ENABLE_CHANNEL_SLICING
 
`ifndef ENABLE_CRRD
   output [KN-1:0]             cms; // the state feedback to IMs
`endif
 
   input                      rst_n; // global active low reset
 
   wire [KN-1:0][SCN-1:0]     cmo0, cmo1, cmo2, cmo3; // the data output of CM
`ifdef ENABLE_CHANNEL_SLICING
   wire [KN-1:0][SCN-1:0]     cmo4, cmoa, cmoa4; // data and ack wires
`else
   wire [KN-1:0]               cmo4, cmoa, cmoa4; // data and ack wires
`endif
   wire [3:0]                  wcfg, ecfg, lcfg; // switch configuration
   wire [1:0]                  scfg, ncfg;       // switch configuration
 
   genvar                     i, j;
 
   // data switch
   dcb_xy #(.VCN(1), .VCW(DW))
   CM (
       .sia   ( dia[i][0]    ),
       .wia   ( dia[i][1]    ),
       .nia   ( dia[i][2]    ),
       .eia   ( dia[i][3]    ),
       .lia   ( dia[i][4]    ),
       .so0   ( cmo0[i][0]   ),
       .so1   ( cmo1[i][0]   ),
       .so2   ( cmo2[i][0]   ),
       .so3   ( cmo3[i][0]   ),
       .so4   ( cmo4[i][0]   ),
       .wo0   ( cmo0[i][1]   ),
       .wo1   ( cmo1[i][1]   ),
       .wo2   ( cmo2[i][1]   ),
       .wo3   ( cmo3[i][1]   ),
       .wo4   ( cmo4[i][1]   ),
       .no0   ( cmo0[i][2]   ),
       .no1   ( cmo1[i][2]   ),
       .no2   ( cmo2[i][2]   ),
       .no3   ( cmo3[i][2]   ),
       .no4   ( cmo4[i][2]   ),
       .eo0   ( cmo0[i][3]   ),
       .eo1   ( cmo1[i][3]   ),
       .eo2   ( cmo2[i][3]   ),
       .eo3   ( cmo3[i][3]   ),
       .eo4   ( cmo4[i][3]   ),
       .lo0   ( cmo0[i][4]   ),
       .lo1   ( cmo1[i][4]   ),
       .lo2   ( cmo2[i][4]   ),
       .lo3   ( cmo3[i][4]   ),
       .lo4   ( cmo4[i][4]   ),
       .si0   ( di0[i][0]    ),
       .si1   ( di1[i][0]    ),
       .si2   ( di2[i][0]    ),
       .si3   ( di3[i][0]    ),
       .si4   ( di4[i][0]    ),
       .wi0   ( di0[i][1]    ),
       .wi1   ( di1[i][1]    ),
       .wi2   ( di2[i][1]    ),
       .wi3   ( di3[i][1]    ),
       .wi4   ( di4[i][1]    ),
       .ni0   ( di0[i][2]    ),
       .ni1   ( di1[i][2]    ),
       .ni2   ( di2[i][2]    ),
       .ni3   ( di3[i][2]    ),
       .ni4   ( di4[i][2]    ),
       .ei0   ( di0[i][3]    ),
       .ei1   ( di1[i][3]    ),
       .ei2   ( di2[i][3]    ),
       .ei3   ( di3[i][3]    ),
       .ei4   ( di4[i][3]    ),
       .li0   ( di0[i][4]    ),
       .li1   ( di1[i][4]    ),
       .li2   ( di2[i][4]    ),
       .li3   ( di3[i][4]    ),
       .li4   ( di4[i][4]    ),
       .soa   ( cmoa[i][0]   ),
       .woa   ( cmoa[i][1]   ),
       .noa   ( cmoa[i][2]   ),
       .eoa   ( cmoa[i][3]   ),
       .loa   ( cmoa[i][4]   ),
       .soa4  ( cmoa4[i][0]  ),
       .woa4  ( cmoa4[i][1]  ),
       .noa4  ( cmoa4[i][2]  ),
       .eoa4  ( cmoa4[i][3]  ),
       .loa4  ( cmoa4[i][4]  ),
       .wcfg  ( wcfg[i]      ),
       .ecfg  ( ecfg[i]      ),
       .lcfg  ( lcfg[i]      ),
       .scfg  ( scfg[i]      ),
       .ncfg  ( ncfg[i]      )
       );
 
   // the allocator
   cm_alloc CMD (
`ifndef ENABLE_CRRD
                 .s     ( cms   ),
`endif
                 .sra   (       ),
                 .wra   (       ),
                 .nra   (       ),
                 .era   (       ),
                 .lra   (       ),
                 .scfg  ( scfg  ),
                 .ncfg  ( ncfg  ),
                 .wcfg  ( wcfg  ),
                 .ecfg  ( ecfg  ),
                 .lcfg  ( lcfg  ),
                 .sr    ( sdec  ),
                 .wr    ( wdec  ),
                 .nr    ( ndec  ),
                 .er    ( edec  ),
                 .lr    ( ldec  )
                 );
 
 
 
endmodule // cm

Line No.	Rev	Author	Line
1	69	wsong0210	`/*`
2			`Asynchronous SDM NoC`
3			`(C)2011 Wei Song`
4			`Advanced Processor Technologies Group`
5			`Computer Science, the Univ. of Manchester, UK`
6
7			`Authors:`
8			`Wei Song wsong83@gmail.com`
9
10			`License: LGPL 3.0 or later`
11
12			`A CM of a buffered Clos for SDM-Clos routers`
13			`* SystemVerilog is used *`
14
15			`History:`
16			`08/07/2011 Initial version. <wsong83@gmail.com>`
17
18			`*/`
19
20			`// the router structure definitions`
21			`include "define.v"
22
23			`module cm (/AUTOARG/`
24			`// Outputs`
25			`do0, do1, do2, do3, dia, do4,`
26			`// Inputs`
27			`di0, di1, di2, di3, sdec, ndec, ldec, wdec, edec, di4, doa, doa4,`
28			`rst_n`
29			`);`
30
31			`parameter KN = 5; // dummy parameter, the number of IMs`
32			`parameter DW = 8; // the data width of each IP`
33			`parameter SCN = DW/2; // the number of sub-channels in one IP`
34
35			`input [KN-1:0][SCN-1:0] di0, di1, di2, di3; // input data`
36			`input [3:0] sdec, ndec, ldec; // the decoded direction requests`
37			`input [1:0] wdec, edec; // the decoded direction requests`
38			`output [KN-1:0][SCN-1:0] do0, do1, do2, do3; // output data`
39
40			`ifdef ENABLE_CHANNEL_SLICING
41			`input [KN-1:0][SCN-1:0] di4; // data input`
42			`output [KN-1:0][SCN-1:0] dia; // input ack`
43			`output [KN-1:0][SCN-1:0] do4; // data output`
44			`input [KN-1:0][SCN-1:0] doa, doa4; // output ack`
45			`else
46			`input [KN-1:0] di4; // data input`
47			`output [KN-1:0] dia; // input ack`
48			`output [KN-1:0] do4; // data output`
49			`input [KN-1:0] doa, doa4; // output ack`
50			`endif // !`ifdef ENABLE_CHANNEL_SLICING
51
52			`ifndef ENABLE_CRRD
53			`output [KN-1:0] cms; // the state feedback to IMs`
54			`endif
55
56			`input rst_n; // global active low reset`
57
58			`wire [KN-1:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3; // the data output of CM`
59			`ifdef ENABLE_CHANNEL_SLICING
60			`wire [KN-1:0][SCN-1:0] cmo4, cmoa, cmoa4; // data and ack wires`
61			`else
62			`wire [KN-1:0] cmo4, cmoa, cmoa4; // data and ack wires`
63			`endif
64			`wire [3:0] wcfg, ecfg, lcfg; // switch configuration`
65			`wire [1:0] scfg, ncfg; // switch configuration`
66
67			`genvar i, j;`
68
69			`// data switch`
70			`dcb_xy #(.VCN(1), .VCW(DW))`
71			`CM (`
72			`.sia ( dia[i][0] ),`
73			`.wia ( dia[i][1] ),`
74			`.nia ( dia[i][2] ),`
75			`.eia ( dia[i][3] ),`
76			`.lia ( dia[i][4] ),`
77			`.so0 ( cmo0[i][0] ),`
78			`.so1 ( cmo1[i][0] ),`
79			`.so2 ( cmo2[i][0] ),`
80			`.so3 ( cmo3[i][0] ),`
81			`.so4 ( cmo4[i][0] ),`
82			`.wo0 ( cmo0[i][1] ),`
83			`.wo1 ( cmo1[i][1] ),`
84			`.wo2 ( cmo2[i][1] ),`
85			`.wo3 ( cmo3[i][1] ),`
86			`.wo4 ( cmo4[i][1] ),`
87			`.no0 ( cmo0[i][2] ),`
88			`.no1 ( cmo1[i][2] ),`
89			`.no2 ( cmo2[i][2] ),`
90			`.no3 ( cmo3[i][2] ),`
91			`.no4 ( cmo4[i][2] ),`
92			`.eo0 ( cmo0[i][3] ),`
93			`.eo1 ( cmo1[i][3] ),`
94			`.eo2 ( cmo2[i][3] ),`
95			`.eo3 ( cmo3[i][3] ),`
96			`.eo4 ( cmo4[i][3] ),`
97			`.lo0 ( cmo0[i][4] ),`
98			`.lo1 ( cmo1[i][4] ),`
99			`.lo2 ( cmo2[i][4] ),`
100			`.lo3 ( cmo3[i][4] ),`
101			`.lo4 ( cmo4[i][4] ),`
102			`.si0 ( di0[i][0] ),`
103			`.si1 ( di1[i][0] ),`
104			`.si2 ( di2[i][0] ),`
105			`.si3 ( di3[i][0] ),`
106			`.si4 ( di4[i][0] ),`
107			`.wi0 ( di0[i][1] ),`
108			`.wi1 ( di1[i][1] ),`
109			`.wi2 ( di2[i][1] ),`
110			`.wi3 ( di3[i][1] ),`
111			`.wi4 ( di4[i][1] ),`
112			`.ni0 ( di0[i][2] ),`
113			`.ni1 ( di1[i][2] ),`
114			`.ni2 ( di2[i][2] ),`
115			`.ni3 ( di3[i][2] ),`
116			`.ni4 ( di4[i][2] ),`
117			`.ei0 ( di0[i][3] ),`
118			`.ei1 ( di1[i][3] ),`
119			`.ei2 ( di2[i][3] ),`
120			`.ei3 ( di3[i][3] ),`
121			`.ei4 ( di4[i][3] ),`
122			`.li0 ( di0[i][4] ),`
123			`.li1 ( di1[i][4] ),`
124			`.li2 ( di2[i][4] ),`
125			`.li3 ( di3[i][4] ),`
126			`.li4 ( di4[i][4] ),`
127			`.soa ( cmoa[i][0] ),`
128			`.woa ( cmoa[i][1] ),`
129			`.noa ( cmoa[i][2] ),`
130			`.eoa ( cmoa[i][3] ),`
131			`.loa ( cmoa[i][4] ),`
132			`.soa4 ( cmoa4[i][0] ),`
133			`.woa4 ( cmoa4[i][1] ),`
134			`.noa4 ( cmoa4[i][2] ),`
135			`.eoa4 ( cmoa4[i][3] ),`
136			`.loa4 ( cmoa4[i][4] ),`
137			`.wcfg ( wcfg[i] ),`
138			`.ecfg ( ecfg[i] ),`
139			`.lcfg ( lcfg[i] ),`
140			`.scfg ( scfg[i] ),`
141			`.ncfg ( ncfg[i] )`
142			`);`
143
144			`// the allocator`
145			`cm_alloc CMD (`
146			`ifndef ENABLE_CRRD
147			`.s ( cms ),`
148			`endif
149			`.sra ( ),`
150			`.wra ( ),`
151			`.nra ( ),`
152			`.era ( ),`
153			`.lra ( ),`
154			`.scfg ( scfg ),`
155			`.ncfg ( ncfg ),`
156			`.wcfg ( wcfg ),`
157			`.ecfg ( ecfg ),`
158			`.lcfg ( lcfg ),`
159			`.sr ( sdec ),`
160			`.wr ( wdec ),`
161			`.nr ( ndec ),`
162			`.er ( edec ),`
163			`.lr ( ldec )`
164			`);`
165
166
167
168			`endmodule // cm`

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