OpenCores
URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [branches/] [clos_opt/] [clos_opt/] [src/] [im.v] - Blame information for rev 70

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 68 wsong0210 
/*
2 
 Asynchronous SDM NoC
3 
 (C)2011 Wei Song
4 
 Advanced Processor Technologies Group
5 
 Computer Science, the Univ. of Manchester, UK
6 
 
7 
 Authors:
8 
 Wei Song     wsong83@gmail.com
9 
 
10 
 License: LGPL 3.0 or later
11 
 
12 
 An IM of a buffered Clos for SDM-Clos routers
13 
 *** SystemVerilog is used ***
14 
 
15 
 History:
16 
 07/07/2011  Initial version. <wsong83@gmail.com>
17 
 
18 
*/
19 
 
20 
// the router structure definitions
21 
`include "define.v"
22 
 
23 
module im (/*AUTOARG*/
24 
   // Outputs
25 
   do0, do1, do2, do3, deco, dia, do4,
26 
   // Inputs
27 70 wsong0210 
   di0, di1, di2, di3, deci, di4, doa,
28 69 wsong0210 
`ifndef ENABLE_CRRD
29 70 wsong0210 
   cms,
30 69 wsong0210 
`endif
31 70 wsong0210 
   rst_n
32 68 wsong0210 
   );
33 69 wsong0210 
 
34 68 wsong0210 
   parameter MN = 2;            // the number of CMs
35 
   parameter NN = 2;            // the number of IPs in one IM
36 
   parameter DW = 8;            // the data width of a single IP
37 
   parameter SN = 2;            // the number of possible output directions
38 
   parameter SCN = DW/2;        // the number of sub-channels in one IP
39 
 
40 
   input [NN-1:0][SCN-1:0]      di0, di1, di2, di3; // data input
41 
   input [NN-1:0][SN-1:0]       deci;                 // decoded dir input
42 
   output [MN-1:0][SCN-1:0]       do0, do1, do2, do3; // data output
43 
   output [MN-1:0][SN-1:0]        deco;               // decoded dir output
44 
 
45 
   // eof bits and ack lines
46 
`ifdef ENABLE_CHANNEL_SLICING
47 
   input [NN-1:0][SCN-1:0]        di4; // data input
48 
   output [NN-1:0][SCN-1:0]     dia; // input ack
49 
   output [MN-1:0][SCN-1:0]       do4; // data output
50 70 wsong0210 
   input [MN-1:0][SCN-1:0]        doa; // output ack
51 68 wsong0210 
`else
52 
   input [NN-1:0]                di4; // data input
53 
   output [NN-1:0]               dia; // input ack
54 
   output [MN-1:0]               do4; // data output
55 70 wsong0210 
   input [MN-1:0]                doa; // output ack
56 68 wsong0210 
`endif // !`ifdef ENABLE_CHANNEL_SLICING
57 
 
58 
`ifndef ENABLE_CRRD
59 
   input [MN-1:0][SN-1:0]         cms; // the states from CMs
60 
`endif
61 
 
62 
   input rst_n;                 // global active low reset
63 
 
64 69 wsong0210 
   wire [MN-1:0][NN-1:0]        cfg;                      // the configuration for the IM
65 68 wsong0210 
   wire [MN-1:0][SCN-1:0]       imo0, imo1, imo2, imo3; // the IM output data
66 
   wire [MN-1:0][SN-1:0]        imodec;                   // the IM output dec
67 
`ifdef ENABLE_CHANNEL_SLICING
68 
   wire [MN-1:0][SCN-1:0]         imo4;        // IM output data
69 
   wire [MN-1:0][SCN-1:0]         imoa, imoa4; // IM output ack
70 69 wsong0210 
   wire [MN-1:0][SCN-1:0]         eofan, doan, deca; // stage control acks
71 68 wsong0210 
`else
72 
   wire [MN-1:0]                 imo4;        // IM data output
73 
   wire [MN-1:0]                 imoa, imoa4; // IM output ack
74 69 wsong0210 
   wire [MN-1:0]                eofan, doan, deca; // stage control acks
75 68 wsong0210 
`endif // !`ifdef ENABLE_CHANNEL_SLICING
76 69 wsong0210 
   wire [MN-1:0]                 decan;
77 
 
78 
   genvar                       i, j;
79 68 wsong0210 
 
80 
   // the data crossbar
81 
   dcb #(.NN(NN), .MN(MN), .DW(DW))
82 
   IMDCB (
83 
        .o0  ( imo0    ),
84 
        .o1  ( imo1    ),
85 
        .o2  ( imo2    ),
86 
        .o3  ( imo3    ),
87 
        .o4  ( imo4    ),
88 
        .ia  ( dia     ),
89 
        .i0  ( di0     ),
90 
        .i1  ( di1     ),
91 
        .i2  ( di2     ),
92 
        .i3  ( di3     ),
93 
        .i4  ( di4     ),
94 
        .oa  ( imoa    ),
95 
        .oa4 ( imoa4   ),
96 
        .cfg ( cfg     )
97 
        );
98 
 
99 
   // the crossbar for decoded direction
100 
   cb  #(.NN(NN), .MN(MN), .DW(SN))
101 
   IMDECCB (
102 
            .data_in   ( deci   ),
103 
            .data_out  ( imodec ),
104 
            .cfg       ( cfg    )
105 
            );
106 
 
107 
   // the IM dispatcher
108 
   im_alloc #(.VCN(NN), .CMN(MN), .SN(SN))
109 
   IMD (
110 
        .IMr   ( deci      ),
111 
        .IMa   (           ),
112 
`ifndef ENABLE_CRRD
113 
        .CMs   ( cms       ),
114 
`endif
115 
        .cfg   ( cfg       ),
116 
        .rst_n ( rst_n     )
117 
        );
118 
 
119 
   // the buffer stage for data
120 
   generate
121 
      for(i=0; i<MN; i++) begin: OPD
122 
`ifdef ENABLE_CHANNEL_SLICING
123 
         for(j=0; j<SCN; j++) begin:SC
124 
            pipe4 #(.DW(2))
125 
            P (
126 
               .o0 ( do0[i][j]  ),
127 
               .o1 ( do1[i][j]  ),
128 
               .o2 ( do2[i][j]  ),
129 
               .o3 ( do3[i][j]  ),
130 
               .ia ( imoa[i][j] ),
131 
               .i0 ( imo0[i][j] ),
132 
               .i1 ( imo1[i][j] ),
133 
               .i2 ( imo2[i][j] ),
134 
               .i3 ( imo3[i][j] ),
135 
               .oa ( doan[i][j] )
136 
               );
137 
 
138 
            pipen #(.DW(1))
139 
            PEoF (
140 
                  .d_in_a  (             ),
141 
                  .d_out   ( do4[i][j]   ),
142 
                  .d_in    ( imo4[i][j]  ),
143 69 wsong0210 
                  .d_out_a ( eofan[i][j] ),
144 68 wsong0210 
                  );
145 
 
146 
            ppc PCTL (
147 69 wsong0210 
                      .deca   ( deca[i][j]  ),
148 
                      .dia    ( imoa4[i][j] ),
149 
                      .eof    ( do4[i][j]   ),
150 
                      .doa    ( doa[i][j]   ),
151 
                      .dec    ( |deco[i]    )
152 
                      );
153 68 wsong0210 
 
154 69 wsong0210 
            assign doan[i][j] = (~doa[i][j])&rst_n;
155 
            assign eofan[i][j] = (~deca[i][j])&rst_n;
156 
         end // block: SC
157 
 
158 
         assign decan[i] = (~&deca[i])&rst_n;
159 
 
160 
`else // !`ifdef ENABLE_CHANNEL_SLICING
161 
         pipe4 #(.DW(DW))
162 
         P (
163 
            .o0 ( do0[i]  ),
164 
            .o1 ( do1[i]  ),
165 
            .o2 ( do2[i]  ),
166 
            .o3 ( do3[i]  ),
167 
            .ia ( imoa[i] ),
168 
            .i0 ( imo0[i] ),
169 
            .i1 ( imo1[i] ),
170 
            .i2 ( imo2[i] ),
171 
            .i3 ( imo3[i] ),
172 
            .oa ( doan[i] )
173 
            );
174 
 
175 
         pipen #(.DW(1))
176 
         PEoF (
177 
               .d_in_a  (          ),
178 
               .d_out   ( do4[i]   ),
179 
               .d_in    ( imo4[i]  ),
180 
               .d_out_a ( eofan[i] )
181 
               );
182 
 
183 
         ppc PCTL (
184 
                   .deca   ( deca[i]  ),
185 
                   .dia    ( imoa4[i] ),
186 
                   .eof    ( do4[i]   ),
187 
                   .doa    ( doa[i]   ),
188 
                   .dec    ( |deco[i] )
189 
                   );
190 
 
191 
         assign doan[i] = (~doa[i])&rst_n;
192 
         assign eofan[i] = (~deca[i])&rst_n;
193 
 
194 
         assign decan[i] = (~deca[i])&rst_n;
195 
 
196 
`endif // !`ifdef ENABLE_CHANNEL_SLICING
197 
 
198 
         pipen #(.DW(SN))
199 
         PDEC (
200 
               .d_in_a   (           ),
201 
               .d_out    ( deco[i]   ),
202 
               .d_in     ( imodec[i] ),
203 
               .d_out_a  ( decan[i]  )
204 
               );
205 
      end // block: OPD
206 
   endgenerate
207 
 
208 68 wsong0210 
endmodule // im

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.