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1 68 wsong0210 
/*
2 
 Asynchronous SDM NoC
3 
 (C)2011 Wei Song
4 
 Advanced Processor Technologies Group
5 
 Computer Science, the Univ. of Manchester, UK
6 
 
7 
 Authors:
8 
 Wei Song     wsong83@gmail.com
9 
 
10 
 License: LGPL 3.0 or later
11 
 
12 
 An IM of a buffered Clos for SDM-Clos routers
13 
 *** SystemVerilog is used ***
14 
 
15 
 History:
16 
 07/07/2011  Initial version. <wsong83@gmail.com>
17 
 
18 
*/
19 
 
20 
// the router structure definitions
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`include "define.v"
22 
 
23 
module im (/*AUTOARG*/
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   // Outputs
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   do0, do1, do2, do3, deco, dia, do4,
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   // Inputs
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   di0, di1, di2, di3, deci, di4, doa,
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`ifndef ENABLE_CRRD
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   cms,
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`endif
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   rst_n
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   );
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34 68 wsong0210 
   parameter MN = 2;            // the number of CMs
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   parameter NN = 2;            // the number of IPs in one IM
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   parameter DW = 8;            // the data width of a single IP
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   parameter SN = 2;            // the number of possible output directions
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   parameter SCN = DW/2;        // the number of sub-channels in one IP
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40 
   input [NN-1:0][SCN-1:0]      di0, di1, di2, di3; // data input
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   input [NN-1:0][SN-1:0]       deci;                 // decoded dir input
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   output [MN-1:0][SCN-1:0]       do0, do1, do2, do3; // data output
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   output [MN-1:0][SN-1:0]        deco;               // decoded dir output
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45 
   // eof bits and ack lines
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`ifdef ENABLE_CHANNEL_SLICING
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   input [NN-1:0][SCN-1:0]        di4; // data input
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   output [NN-1:0][SCN-1:0]     dia; // input ack
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   output [MN-1:0][SCN-1:0]       do4; // data output
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   input [MN-1:0][SCN-1:0]        doa; // output ack
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`else
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   input [NN-1:0]                di4; // data input
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   output [NN-1:0]               dia; // input ack
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   output [MN-1:0]               do4; // data output
55 70 wsong0210 
   input [MN-1:0]                doa; // output ack
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
57 
 
58 
`ifndef ENABLE_CRRD
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   input [MN-1:0][SN-1:0]         cms; // the states from CMs
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`endif
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62 
   input rst_n;                 // global active low reset
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   wire [MN-1:0][NN-1:0]        cfg;                      // the configuration for the IM
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   wire [MN-1:0][SCN-1:0]       imo0, imo1, imo2, imo3; // the IM output data
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   wire [MN-1:0][SN-1:0]        imodec;                   // the IM output dec
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`ifdef ENABLE_CHANNEL_SLICING
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   wire [MN-1:0][SCN-1:0]         imo4;        // IM output data
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   wire [MN-1:0][SCN-1:0]         imoa, imoa4; // IM output ack
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   wire [MN-1:0][SCN-1:0]         eofan, doan, deca; // stage control acks
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`else
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   wire [MN-1:0]                 imo4;        // IM data output
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   wire [MN-1:0]                 imoa, imoa4; // IM output ack
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   wire [MN-1:0]                eofan, doan, deca; // stage control acks
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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   wire [MN-1:0]                 decan;
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   genvar                       i, j;
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   // the data crossbar
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   dcb #(.NN(NN), .MN(MN), .DW(DW))
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   IMDCB (
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        .o0  ( imo0    ),
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        .o1  ( imo1    ),
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        .o2  ( imo2    ),
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        .o3  ( imo3    ),
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        .o4  ( imo4    ),
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        .ia  ( dia     ),
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        .i0  ( di0     ),
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        .i1  ( di1     ),
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        .i2  ( di2     ),
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        .i3  ( di3     ),
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        .i4  ( di4     ),
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        .oa  ( imoa    ),
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        .oa4 ( imoa4   ),
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        .cfg ( cfg     )
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        );
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   // the crossbar for decoded direction
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   cb  #(.NN(NN), .MN(MN), .DW(SN))
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   IMDECCB (
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            .data_in   ( deci   ),
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            .data_out  ( imodec ),
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            .cfg       ( cfg    )
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            );
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   // the IM dispatcher
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   im_alloc #(.VCN(NN), .CMN(MN), .SN(SN))
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   IMD (
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        .IMr   ( deci      ),
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        .IMa   (           ),
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`ifndef ENABLE_CRRD
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        .CMs   ( cms       ),
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`endif
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        .cfg   ( cfg       ),
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        .rst_n ( rst_n     )
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        );
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   // the buffer stage for data
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   generate
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      for(i=0; i<MN; i++) begin: OPD
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`ifdef ENABLE_CHANNEL_SLICING
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         for(j=0; j<SCN; j++) begin:SC
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            pipe4 #(.DW(2))
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            P (
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               .o0 ( do0[i][j]  ),
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               .o1 ( do1[i][j]  ),
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               .o2 ( do2[i][j]  ),
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               .o3 ( do3[i][j]  ),
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               .ia ( imoa[i][j] ),
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               .i0 ( imo0[i][j] ),
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               .i1 ( imo1[i][j] ),
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               .i2 ( imo2[i][j] ),
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               .i3 ( imo3[i][j] ),
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               .oa ( doan[i][j] )
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               );
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            pipen #(.DW(1))
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            PEoF (
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                  .d_in_a  (             ),
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                  .d_out   ( do4[i][j]   ),
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                  .d_in    ( imo4[i][j]  ),
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                  .d_out_a ( eofan[i][j] ),
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                  );
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146 
            ppc PCTL (
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                      .deca   ( deca[i][j]  ),
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                      .dia    ( imoa4[i][j] ),
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                      .eof    ( do4[i][j]   ),
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                      .doa    ( doa[i][j]   ),
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                      .dec    ( |deco[i]    )
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                      );
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154 69 wsong0210 
            assign doan[i][j] = (~doa[i][j])&rst_n;
155 
            assign eofan[i][j] = (~deca[i][j])&rst_n;
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         end // block: SC
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         assign decan[i] = (~&deca[i])&rst_n;
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160 
`else // !`ifdef ENABLE_CHANNEL_SLICING
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         pipe4 #(.DW(DW))
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         P (
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            .o0 ( do0[i]  ),
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            .o1 ( do1[i]  ),
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            .o2 ( do2[i]  ),
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            .o3 ( do3[i]  ),
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            .ia ( imoa[i] ),
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            .i0 ( imo0[i] ),
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            .i1 ( imo1[i] ),
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            .i2 ( imo2[i] ),
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            .i3 ( imo3[i] ),
172 
            .oa ( doan[i] )
173 
            );
174 
 
175 
         pipen #(.DW(1))
176 
         PEoF (
177 
               .d_in_a  (          ),
178 
               .d_out   ( do4[i]   ),
179 
               .d_in    ( imo4[i]  ),
180 
               .d_out_a ( eofan[i] )
181 
               );
182 
 
183 
         ppc PCTL (
184 
                   .deca   ( deca[i]  ),
185 
                   .dia    ( imoa4[i] ),
186 
                   .eof    ( do4[i]   ),
187 
                   .doa    ( doa[i]   ),
188 
                   .dec    ( |deco[i] )
189 
                   );
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191 
         assign doan[i] = (~doa[i])&rst_n;
192 
         assign eofan[i] = (~deca[i])&rst_n;
193 
 
194 
         assign decan[i] = (~deca[i])&rst_n;
195 
 
196 
`endif // !`ifdef ENABLE_CHANNEL_SLICING
197 
 
198 
         pipen #(.DW(SN))
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         PDEC (
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               .d_in_a   (           ),
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               .d_out    ( deco[i]   ),
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               .d_in     ( imodec[i] ),
203 
               .d_out_a  ( decan[i]  )
204 
               );
205 
      end // block: OPD
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   endgenerate
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endmodule // im

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