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/*
 Asynchronous SDM NoC
 (C)2011 Wei Song
 Advanced Processor Technologies Group
 Computer Science, the Univ. of Manchester, UK
 
 Authors:
 Wei Song     wsong83@gmail.com
 
 License: LGPL 3.0 or later
 
 Wormhole/SDM router top level module
 *** SystemVerilog is used ***
 
 History:
 28/05/2009  Initial version. <wsong83@gmail.com>
 23/09/2010  Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
 22/10/2010  Parameterize the number of pipelines in output buffers. <wsong83@gmail.com>
 25/05/2011  Clean up for opensource. <wsong83@gmail.com>
 21/07/2011  Preparation for the buffered Clos switch. <wsong83@gmail.com>
 
*/
 
// the router structure definitions
`include "define.v"
 
module router(/*AUTOARG*/
   // Outputs
   so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
   eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
   wia, nia, eia, lia,
   // Inputs
   si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
   ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
   woa, noa, eoa, loa, addrx, addry, rst_n
   );
 
   parameter VCN = 1;           // number of virtual circuits in each direction. When VCN == 1, it is a wormhole router
   parameter DW = 32;           // the datawidth of a single virtual circuit, the total data width of the router is DW*VCN
   parameter IPD = 1;           // the number of half-buffer stages in input buffers
   parameter OPD = 2;           // the number of half-buffer stages in output buffers
   parameter SCN = DW/2;        // the number of 1-of-4 sub-channel in each virtual circuit
 
   input [VCN-1:0][SCN-1:0]      si0, si1, si2, si3; // south input [0], X+1
   input [VCN-1:0][SCN-1:0]        wi0, wi1, wi2, wi3; // west input [1], Y-1
   input [VCN-1:0][SCN-1:0]        ni0, ni1, ni2, ni3; // north input [2], X-1
   input [VCN-1:0][SCN-1:0]        ei0, ei1, ei2, ei3; // east input [3], Y+1
   input [VCN-1:0][SCN-1:0]        li0, li1, li2, li3; // local input
   output [VCN-1:0][SCN-1:0]       so0, so1, so2, so3; // south output
   output [VCN-1:0][SCN-1:0]       wo0, wo1, wo2, wo3; // west output
   output [VCN-1:0][SCN-1:0]       no0, no1, no2, no3; // north output
   output [VCN-1:0][SCN-1:0]       eo0, eo1, eo2, eo3; // east output
   output [VCN-1:0][SCN-1:0]       lo0, lo1, lo2, lo3; // local output
 
   // eof bits and ack lines
`ifdef ENABLE_CHANNEL_SLICING
   input [VCN-1:0][SCN-1:0]        si4, wi4, ni4, ei4, li4;
   output [VCN-1:0][SCN-1:0]       so4, wo4, no4, eo4, lo4;
   output [VCN-1:0][SCN-1:0]       sia, wia, nia, eia, lia;
   input [VCN-1:0][SCN-1:0]        soa, woa, noa, eoa, loa;
`else
   input [VCN-1:0]                si4, wi4, ni4, ei4, li4;
   output [VCN-1:0]               so4, wo4, no4, eo4, lo4;
   output [VCN-1:0]               sia, wia, nia, eia, lia;
   input [VCN-1:0]                soa, woa, noa, eoa, loa;
`endif // !`ifdef ENABLE_CHANNEL_SLICING
 
   input [7:0]                    addrx, addry; // the local address of the router, coded in 1-of-4 coding
   input                         rst_n;        // active low reset signal
 
   // internal wires, input buffers to switches (crossbar): [dir]2[cb][1-of-4 index]
   wire [VCN-1:0][SCN-1:0]         s2c0, s2c1, s2c2, s2c3; // south input to switch data
   wire [VCN-1:0][SCN-1:0]         w2c0, w2c1, w2c2, w2c3;
   wire [VCN-1:0][SCN-1:0]         n2c0, n2c1, n2c2, n2c3;
   wire [VCN-1:0][SCN-1:0]         e2c0, e2c1, e2c2, e2c3;
   wire [VCN-1:0][SCN-1:0]         l2c0, l2c1, l2c2, l2c3;
   // internal wires, switches (crossbar) to output buffers: [cb]2[dir][1-of-4 index]
   wire [VCN-1:0][SCN-1:0]         c2s0, c2s1, c2s2, c2s3;
   wire [VCN-1:0][SCN-1:0]         c2w0, c2w1, c2w2, c2w3;
   wire [VCN-1:0][SCN-1:0]         c2n0, c2n1, c2n2, c2n3; // switch to north output
   wire [VCN-1:0][SCN-1:0]         c2e0, c2e1, c2e2, c2e3;
   wire [VCN-1:0][SCN-1:0]         c2l0, c2l1, c2l2, c2l3;
 
   // internal wires for ack and eof bits
`ifdef ENABLE_CHANNEL_SLICING
   wire [VCN-1:0][SCN-1:0]         s2c4, w2c4, n2c4, e2c4, l2c4;
   wire [VCN-1:0][SCN-1:0]         c2s4, c2w4, c2n4, c2e4, c2l4;
   wire [VCN-1:0][SCN-1:0]         s2ca, w2ca, n2ca, e2ca, l2ca;
   wire [VCN-1:0][SCN-1:0]         c2sa, c2wa, c2na, c2ea, c2la;
   wire [VCN-1:0][SCN-1:0]         c2sa4, c2wa4, c2na4, c2ea4, c2la4;
`else
   wire [VCN-1:0]                 s2c4, w2c4, n2c4, e2c4, l2c4;
   wire [VCN-1:0]                 c2s4, c2w4, c2n4, c2e4, c2l4;
   wire [VCN-1:0]                 s2ca, w2ca, n2ca, e2ca, l2ca;
   wire [VCN-1:0]                 c2sa, c2wa, c2na, c2ea, c2la;
   wire [VCN-1:0]                 c2sa4, c2wa4, c2na4, c2ea4, c2la4;
`endif // !`ifdef ENABLE_CHANNEL_SLICING
 
   // the requests/acks from/to input buffers to switch allocators
   wire [VCN-1:0][3:0]             sreq, nreq, lreq;
   wire [VCN-1:0][1:0]             wreq, ereq;
   wire [VCN-1:0]                 sack, wack, nack, eack, lack;
 
   // configuration bits for the switches
`ifdef ENABLE_CLOS
   wire [4:0][VCN-1:0][VCN-1:0]  imcfg;
   wire [VCN-1:0][1:0]             scfg, ncfg;
   wire [VCN-1:0][3:0]             wcfg, ecfg, lcfg;
`else // normal crossbar based SDM
   wire [VCN-1:0][2*VCN-1:0]       scfg, ncfg;
   wire [VCN-1:0][4*VCN-1:0]       wcfg, ecfg, lcfg;
`endif
 
 
   genvar                 i;
 
   generate
      for (i=0; i<VCN; i++) begin: SC
 
         // --------------- input buffers ------------------- //
 
         inp_buf #(.DIR(0), .RN(4), .DW(DW), .PD(IPD))
         SIB (
              .o0     ( s2c0[i]  ),
              .o1     ( s2c1[i]  ),
              .o2     ( s2c2[i]  ),
              .o3     ( s2c3[i]  ),
              .o4     ( s2c4[i]  ),
              .ia     ( sia[i]   ),
              .deco   ( sreq[i]  ),
              .rst_n  ( rst_n    ),
              .i0     ( si0[i]   ),
              .i1     ( si1[i]   ),
              .i2     ( si2[i]   ),
              .i3     ( si3[i]   ),
              .i4     ( si4[i]   ),
              .oa     ( s2ca[i]  ),
              .addrx  ( addrx    ),
              .addry  ( addry    )
              );
 
         inp_buf #(.DIR(1), .RN(2), .DW(DW), .PD(IPD))
         WIB (
              .o0     ( w2c0[i]  ),
              .o1     ( w2c1[i]  ),
              .o2     ( w2c2[i]  ),
              .o3     ( w2c3[i]  ),
              .o4     ( w2c4[i]  ),
              .ia     ( wia[i]   ),
              .deco   ( wreq[i]  ),
              .rst_n  ( rst_n    ),
              .i0     ( wi0[i]   ),
              .i1     ( wi1[i]   ),
              .i2     ( wi2[i]   ),
              .i3     ( wi3[i]   ),
              .i4     ( wi4[i]   ),
              .oa     ( w2ca[i]  ),
              .addrx  ( addrx    ),
              .addry  ( addry    )
              );
 
         inp_buf #(.DIR(2), .RN(4), .DW(DW), .PD(IPD))
         NIB (
              .o0     ( n2c0[i]  ),
              .o1     ( n2c1[i]  ),
              .o2     ( n2c2[i]  ),
              .o3     ( n2c3[i]  ),
              .o4     ( n2c4[i]  ),
              .ia     ( nia[i]   ),
              .deco   ( nreq[i]  ),
              .rst_n  ( rst_n    ),
              .i0     ( ni0[i]   ),
              .i1     ( ni1[i]   ),
              .i2     ( ni2[i]   ),
              .i3     ( ni3[i]   ),
              .i4     ( ni4[i]   ),
              .oa     ( n2ca[i]  ),
              .addrx  ( addrx    ),
              .addry  ( addry    )
              );
 
         inp_buf #(.DIR(3), .RN(2), .DW(DW), .PD(IPD))
         EIB (
              .o0     ( e2c0[i]  ),
              .o1     ( e2c1[i]  ),
              .o2     ( e2c2[i]  ),
              .o3     ( e2c3[i]  ),
              .o4     ( e2c4[i]  ),
              .ia     ( eia[i]   ),
              .deco   ( ereq[i]  ),
              .rst_n  ( rst_n    ),
              .i0     ( ei0[i]   ),
              .i1     ( ei1[i]   ),
              .i2     ( ei2[i]   ),
              .i3     ( ei3[i]   ),
              .i4     ( ei4[i]   ),
              .oa     ( e2ca[i]  ),
              .addrx  ( addrx    ),
              .addry  ( addry    )
              );
 
         inp_buf #(.DIR(4), .RN(4), .DW(DW), .PD(IPD))
         LIB (
              .o0     ( l2c0[i]  ),
              .o1     ( l2c1[i]  ),
              .o2     ( l2c2[i]  ),
              .o3     ( l2c3[i]  ),
              .o4     ( l2c4[i]  ),
              .ia     ( lia[i]   ),
              .deco   ( lreq[i]  ),
              .rst_n  ( rst_n    ),
              .i0     ( li0[i]   ),
              .i1     ( li1[i]   ),
              .i2     ( li2[i]   ),
              .i3     ( li3[i]   ),
              .i4     ( li4[i]   ),
              .oa     ( l2ca[i]  ),
              .addrx  ( addrx    ),
              .addry  ( addry    )
              );
 
         // --------------------- output buffers ---------------- //
         outp_buf #(.DW(DW), .PD(OPD))
         SOB (
              .o0     ( so0[i]   ),
              .o1     ( so1[i]   ),
              .o2     ( so2[i]   ),
              .o3     ( so3[i]   ),
              .o4     ( so4[i]   ),
              .oa     ( soa[i]   ),
              .i0     ( c2s0[i]  ),
              .i1     ( c2s1[i]  ),
              .i2     ( c2s2[i]  ),
              .i3     ( c2s3[i]  ),
              .i4     ( c2s4[i]  ),
              .ia     ( c2sa[i]  ),
              .ia4    ( c2sa4[i] ),
              .rst_n  ( rst_n    )
              );
 
         outp_buf #(.DW(DW), .PD(OPD))
         WOB (
              .o0     ( wo0[i]   ),
              .o1     ( wo1[i]   ),
              .o2     ( wo2[i]   ),
              .o3     ( wo3[i]   ),
              .o4     ( wo4[i]   ),
              .oa     ( woa[i]   ),
              .i0     ( c2w0[i]  ),
              .i1     ( c2w1[i]  ),
              .i2     ( c2w2[i]  ),
              .i3     ( c2w3[i]  ),
              .i4     ( c2w4[i]  ),
              .ia     ( c2wa[i]  ),
              .ia4    ( c2wa4[i] ),
              .rst_n  ( rst_n    )
              );
 
         outp_buf #(.DW(DW), .PD(OPD))
         NOB (
              .o0     ( no0[i]   ),
              .o1     ( no1[i]   ),
              .o2     ( no2[i]   ),
              .o3     ( no3[i]   ),
              .o4     ( no4[i]   ),
              .oa     ( noa[i]   ),
              .i0     ( c2n0[i]  ),
              .i1     ( c2n1[i]  ),
              .i2     ( c2n2[i]  ),
              .i3     ( c2n3[i]  ),
              .i4     ( c2n4[i]  ),
              .ia     ( c2na[i]  ),
              .ia4    ( c2na4[i] ),
              .rst_n  ( rst_n    )
              );
 
         outp_buf #(.DW(DW), .PD(OPD))
         EOB (
              .o0     ( eo0[i]   ),
              .o1     ( eo1[i]   ),
              .o2     ( eo2[i]   ),
              .o3     ( eo3[i]   ),
              .o4     ( eo4[i]   ),
              .oa     ( eoa[i]   ),
              .i0     ( c2e0[i]  ),
              .i1     ( c2e1[i]  ),
              .i2     ( c2e2[i]  ),
              .i3     ( c2e3[i]  ),
              .i4     ( c2e4[i]  ),
              .ia     ( c2ea[i]  ),
              .ia4    ( c2ea4[i] ),
              .rst_n  ( rst_n    )
              );
 
         outp_buf #(.DW(DW), .PD(OPD))
         LOB (
              .o0     ( lo0[i]   ),
              .o1     ( lo1[i]   ),
              .o2     ( lo2[i]   ),
              .o3     ( lo3[i]   ),
              .o4     ( lo4[i]   ),
              .oa     ( loa[i]   ),
              .i0     ( c2l0[i]  ),
              .i1     ( c2l1[i]  ),
              .i2     ( c2l2[i]  ),
              .i3     ( c2l3[i]  ),
              .i4     ( c2l4[i]  ),
              .ia     ( c2la[i]  ),
              .ia4    ( c2la4[i] ),
              .rst_n  ( rst_n    )
              );
 
      end // block: SC
   endgenerate
 
`ifdef ENABLE_CLOS
   clos #(.MN(VCN), .NN(VCN), .DW(DW))
   CB (
       .so0     ( c2s0      ),
       .so1     ( c2s1      ),
       .so2     ( c2s2      ),
       .so3     ( c2s3      ),
       .so4     ( c2s4      ),
       .soa     ( c2sa      ),
       .soa4    ( c2sa4     ),
       .wo0     ( c2w0      ),
       .wo1     ( c2w1      ),
       .wo2     ( c2w2      ),
       .wo3     ( c2w3      ),
       .wo4     ( c2w4      ),
       .woa     ( c2wa      ),
       .woa4    ( c2wa4     ),
       .no0     ( c2n0      ),
       .no1     ( c2n1      ),
       .no2     ( c2n2      ),
       .no3     ( c2n3      ),
       .no4     ( c2n4      ),
       .noa     ( c2na      ),
       .noa4    ( c2na4     ),
       .eo0     ( c2e0      ),
       .eo1     ( c2e1      ),
       .eo2     ( c2e2      ),
       .eo3     ( c2e3      ),
       .eo4     ( c2e4      ),
       .eoa     ( c2ea      ),
       .eoa4    ( c2ea4     ),
       .lo0     ( c2l0      ),
       .lo1     ( c2l1      ),
       .lo2     ( c2l2      ),
       .lo3     ( c2l3      ),
       .lo4     ( c2l4      ),
       .loa     ( c2la      ),
       .loa4    ( c2la4     ),
       .si0     ( s2c0      ),
       .si1     ( s2c1      ),
       .si2     ( s2c2      ),
       .si3     ( s2c3      ),
       .si4     ( s2c4      ),
       .sia     ( s2ca      ),
       .wi0     ( w2c0      ),
       .wi1     ( w2c1      ),
       .wi2     ( w2c2      ),
       .wi3     ( w2c3      ),
       .wi4     ( w2c4      ),
       .wia     ( w2ca      ),
       .ni0     ( n2c0      ),
       .ni1     ( n2c1      ),
       .ni2     ( n2c2      ),
       .ni3     ( n2c3      ),
       .ni4     ( n2c4      ),
       .nia     ( n2ca      ),
       .ei0     ( e2c0      ),
       .ei1     ( e2c1      ),
       .ei2     ( e2c2      ),
       .ei3     ( e2c3      ),
       .ei4     ( e2c4      ),
       .eia     ( e2ca      ),
       .li0     ( l2c0      ),
       .li1     ( l2c1      ),
       .li2     ( l2c2      ),
       .li3     ( l2c3      ),
       .li4     ( l2c4      ),
       .lia     ( l2ca      ),
       .rst_n   ( rst_n     )
       ) ;
 
`else  // Crossbar based SDM
 
   dcb_xy #(.VCN(VCN), .VCW(DW))
   CB (
       .so0     ( c2s0      ),
       .so1     ( c2s1      ),
       .so2     ( c2s2      ),
       .so3     ( c2s3      ),
       .so4     ( c2s4      ),
       .soa     ( c2sa      ),
       .wo0     ( c2w0      ),
       .wo1     ( c2w1      ),
       .wo2     ( c2w2      ),
       .wo3     ( c2w3      ),
       .wo4     ( c2w4      ),
       .woa     ( c2wa      ),
       .no0     ( c2n0      ),
       .no1     ( c2n1      ),
       .no2     ( c2n2      ),
       .no3     ( c2n3      ),
       .no4     ( c2n4      ),
       .noa     ( c2na      ),
       .eo0     ( c2e0      ),
       .eo1     ( c2e1      ),
       .eo2     ( c2e2      ),
       .eo3     ( c2e3      ),
       .eo4     ( c2e4      ),
       .eoa     ( c2ea      ),
       .lo0     ( c2l0      ),
       .lo1     ( c2l1      ),
       .lo2     ( c2l2      ),
       .lo3     ( c2l3      ),
       .lo4     ( c2l4      ),
       .loa     ( c2la      ),
       .si0     ( s2c0      ),
       .si1     ( s2c1      ),
       .si2     ( s2c2      ),
       .si3     ( s2c3      ),
       .si4     ( s2c4      ),
       .sia     ( s2ca      ),
       .wi0     ( w2c0      ),
       .wi1     ( w2c1      ),
       .wi2     ( w2c2      ),
       .wi3     ( w2c3      ),
       .wi4     ( w2c4      ),
       .wia     ( w2ca      ),
       .ni0     ( n2c0      ),
       .ni1     ( n2c1      ),
       .ni2     ( n2c2      ),
       .ni3     ( n2c3      ),
       .ni4     ( n2c4      ),
       .nia     ( n2ca      ),
       .ei0     ( e2c0      ),
       .ei1     ( e2c1      ),
       .ei2     ( e2c2      ),
       .ei3     ( e2c3      ),
       .ei4     ( e2c4      ),
       .eia     ( e2ca      ),
       .li0     ( l2c0      ),
       .li1     ( l2c1      ),
       .li2     ( l2c2      ),
       .li3     ( l2c3      ),
       .li4     ( l2c4      ),
       .lia     ( l2ca      ),
       .wcfg    ( wcfg      ),
       .ecfg    ( ecfg      ),
       .lcfg    ( lcfg      ),
       .scfg    ( scfg      ),
       .ncfg    ( ncfg      )
       ) ;
 
 
   sdm_sch #(.VCN(VCN))
   ALLOC (
          .sack  ( sack    ),
          .wack  ( wack    ),
          .nack  ( nack    ),
          .eack  ( eack    ),
          .lack  ( lack    ),
          .scfg  ( scfg    ),
          .ncfg  ( ncfg    ),
          .wcfg  ( wcfg    ),
          .ecfg  ( ecfg    ),
          .lcfg  ( lcfg    ),
          .sreq  ( sreq    ),
          .nreq  ( nreq    ),
          .lreq  ( lreq    ),
          .wreq  ( wreq    ),
          .ereq  ( ereq    ),
          .rst_n ( rst_n   )
          );
`endif
 
endmodule // router

Line No.	Rev	Author	Line
1	13	wsong0210	`/*`
2			`Asynchronous SDM NoC`
3			`(C)2011 Wei Song`
4			`Advanced Processor Technologies Group`
5			`Computer Science, the Univ. of Manchester, UK`
6
7			`Authors:`
8			`Wei Song wsong83@gmail.com`
9
10			`License: LGPL 3.0 or later`
11
12			`Wormhole/SDM router top level module`
13			`* SystemVerilog is used *`
14
15			`History:`
16			`28/05/2009 Initial version. <wsong83@gmail.com>`
17			`23/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>`
18			`22/10/2010 Parameterize the number of pipelines in output buffers. <wsong83@gmail.com>`
19	19	wsong0210	`25/05/2011 Clean up for opensource. <wsong83@gmail.com>`
20	75	wsong0210	`21/07/2011 Preparation for the buffered Clos switch. <wsong83@gmail.com>`
21	13	wsong0210
22			`*/`
23
24			`// the router structure definitions`
25			`include "define.v"
26
27			`module router(/AUTOARG/`
28			`// Outputs`
29			`so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,`
30			`eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,`
31			`wia, nia, eia, lia,`
32			`// Inputs`
33			`si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,`
34			`ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,`
35			`woa, noa, eoa, loa, addrx, addry, rst_n`
36			`);`
37
38			`parameter VCN = 1; // number of virtual circuits in each direction. When VCN == 1, it is a wormhole router`
39			`parameter DW = 32; // the datawidth of a single virtual circuit, the total data width of the router is DW*VCN`
40			`parameter IPD = 1; // the number of half-buffer stages in input buffers`
41			`parameter OPD = 2; // the number of half-buffer stages in output buffers`
42			`parameter SCN = DW/2; // the number of 1-of-4 sub-channel in each virtual circuit`
43
44			`input [VCN-1:0][SCN-1:0] si0, si1, si2, si3; // south input [0], X+1`
45			`input [VCN-1:0][SCN-1:0] wi0, wi1, wi2, wi3; // west input [1], Y-1`
46			`input [VCN-1:0][SCN-1:0] ni0, ni1, ni2, ni3; // north input [2], X-1`
47			`input [VCN-1:0][SCN-1:0] ei0, ei1, ei2, ei3; // east input [3], Y+1`
48			`input [VCN-1:0][SCN-1:0] li0, li1, li2, li3; // local input`
49			`output [VCN-1:0][SCN-1:0] so0, so1, so2, so3; // south output`
50			`output [VCN-1:0][SCN-1:0] wo0, wo1, wo2, wo3; // west output`
51			`output [VCN-1:0][SCN-1:0] no0, no1, no2, no3; // north output`
52			`output [VCN-1:0][SCN-1:0] eo0, eo1, eo2, eo3; // east output`
53			`output [VCN-1:0][SCN-1:0] lo0, lo1, lo2, lo3; // local output`
54
55			`// eof bits and ack lines`
56			`ifdef ENABLE_CHANNEL_SLICING
57			`input [VCN-1:0][SCN-1:0] si4, wi4, ni4, ei4, li4;`
58			`output [VCN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4;`
59			`output [VCN-1:0][SCN-1:0] sia, wia, nia, eia, lia;`
60			`input [VCN-1:0][SCN-1:0] soa, woa, noa, eoa, loa;`
61			`else
62			`input [VCN-1:0] si4, wi4, ni4, ei4, li4;`
63			`output [VCN-1:0] so4, wo4, no4, eo4, lo4;`
64			`output [VCN-1:0] sia, wia, nia, eia, lia;`
65			`input [VCN-1:0] soa, woa, noa, eoa, loa;`
66			`endif // !`ifdef ENABLE_CHANNEL_SLICING
67
68			`input [7:0] addrx, addry; // the local address of the router, coded in 1-of-4 coding`
69			`input rst_n; // active low reset signal`
70
71			`// internal wires, input buffers to switches (crossbar): [dir]2[cb][1-of-4 index]`
72			`wire [VCN-1:0][SCN-1:0] s2c0, s2c1, s2c2, s2c3; // south input to switch data`
73			`wire [VCN-1:0][SCN-1:0] w2c0, w2c1, w2c2, w2c3;`
74			`wire [VCN-1:0][SCN-1:0] n2c0, n2c1, n2c2, n2c3;`
75			`wire [VCN-1:0][SCN-1:0] e2c0, e2c1, e2c2, e2c3;`
76			`wire [VCN-1:0][SCN-1:0] l2c0, l2c1, l2c2, l2c3;`
77			`// internal wires, switches (crossbar) to output buffers: [cb]2[dir][1-of-4 index]`
78			`wire [VCN-1:0][SCN-1:0] c2s0, c2s1, c2s2, c2s3;`
79			`wire [VCN-1:0][SCN-1:0] c2w0, c2w1, c2w2, c2w3;`
80			`wire [VCN-1:0][SCN-1:0] c2n0, c2n1, c2n2, c2n3; // switch to north output`
81			`wire [VCN-1:0][SCN-1:0] c2e0, c2e1, c2e2, c2e3;`
82			`wire [VCN-1:0][SCN-1:0] c2l0, c2l1, c2l2, c2l3;`
83
84			`// internal wires for ack and eof bits`
85			`ifdef ENABLE_CHANNEL_SLICING
86			`wire [VCN-1:0][SCN-1:0] s2c4, w2c4, n2c4, e2c4, l2c4;`
87			`wire [VCN-1:0][SCN-1:0] c2s4, c2w4, c2n4, c2e4, c2l4;`
88			`wire [VCN-1:0][SCN-1:0] s2ca, w2ca, n2ca, e2ca, l2ca;`
89			`wire [VCN-1:0][SCN-1:0] c2sa, c2wa, c2na, c2ea, c2la;`
90	77	wsong0210	`wire [VCN-1:0][SCN-1:0] c2sa4, c2wa4, c2na4, c2ea4, c2la4;`
91	13	wsong0210	`else
92			`wire [VCN-1:0] s2c4, w2c4, n2c4, e2c4, l2c4;`
93			`wire [VCN-1:0] c2s4, c2w4, c2n4, c2e4, c2l4;`
94			`wire [VCN-1:0] s2ca, w2ca, n2ca, e2ca, l2ca;`
95			`wire [VCN-1:0] c2sa, c2wa, c2na, c2ea, c2la;`
96	77	wsong0210	`wire [VCN-1:0] c2sa4, c2wa4, c2na4, c2ea4, c2la4;`
97	13	wsong0210	`endif // !`ifdef ENABLE_CHANNEL_SLICING
98
99			`// the requests/acks from/to input buffers to switch allocators`
100			`wire [VCN-1:0][3:0] sreq, nreq, lreq;`
101			`wire [VCN-1:0][1:0] wreq, ereq;`
102			`wire [VCN-1:0] sack, wack, nack, eack, lack;`
103
104			`// configuration bits for the switches`
105			`ifdef ENABLE_CLOS
106			`wire [4:0][VCN-1:0][VCN-1:0] imcfg;`
107			`wire [VCN-1:0][1:0] scfg, ncfg;`
108			`wire [VCN-1:0][3:0] wcfg, ecfg, lcfg;`
109			`else // normal crossbar based SDM
110			`wire [VCN-1:0][2*VCN-1:0] scfg, ncfg;`
111			`wire [VCN-1:0][4*VCN-1:0] wcfg, ecfg, lcfg;`
112			`endif
113
114
115			`genvar i;`
116
117			`generate`
118			`for (i=0; i<VCN; i++) begin: SC`
119
120			`// --------------- input buffers ------------------- //`
121
122			`inp_buf #(.DIR(0), .RN(4), .DW(DW), .PD(IPD))`
123			`SIB (`
124			`.o0 ( s2c0[i] ),`
125			`.o1 ( s2c1[i] ),`
126			`.o2 ( s2c2[i] ),`
127			`.o3 ( s2c3[i] ),`
128			`.o4 ( s2c4[i] ),`
129			`.ia ( sia[i] ),`
130	75	wsong0210	`.deco ( sreq[i] ),`
131	13	wsong0210	`.rst_n ( rst_n ),`
132			`.i0 ( si0[i] ),`
133			`.i1 ( si1[i] ),`
134			`.i2 ( si2[i] ),`
135			`.i3 ( si3[i] ),`
136			`.i4 ( si4[i] ),`
137			`.oa ( s2ca[i] ),`
138			`.addrx ( addrx ),`
139	75	wsong0210	`.addry ( addry )`
140	13	wsong0210	`);`
141
142			`inp_buf #(.DIR(1), .RN(2), .DW(DW), .PD(IPD))`
143			`WIB (`
144			`.o0 ( w2c0[i] ),`
145			`.o1 ( w2c1[i] ),`
146			`.o2 ( w2c2[i] ),`
147			`.o3 ( w2c3[i] ),`
148			`.o4 ( w2c4[i] ),`
149			`.ia ( wia[i] ),`
150	75	wsong0210	`.deco ( wreq[i] ),`
151	13	wsong0210	`.rst_n ( rst_n ),`
152			`.i0 ( wi0[i] ),`
153			`.i1 ( wi1[i] ),`
154			`.i2 ( wi2[i] ),`
155			`.i3 ( wi3[i] ),`
156			`.i4 ( wi4[i] ),`
157			`.oa ( w2ca[i] ),`
158			`.addrx ( addrx ),`
159	75	wsong0210	`.addry ( addry )`
160	13	wsong0210	`);`
161
162			`inp_buf #(.DIR(2), .RN(4), .DW(DW), .PD(IPD))`
163			`NIB (`
164			`.o0 ( n2c0[i] ),`
165			`.o1 ( n2c1[i] ),`
166			`.o2 ( n2c2[i] ),`
167			`.o3 ( n2c3[i] ),`
168			`.o4 ( n2c4[i] ),`
169			`.ia ( nia[i] ),`
170	75	wsong0210	`.deco ( nreq[i] ),`
171	13	wsong0210	`.rst_n ( rst_n ),`
172			`.i0 ( ni0[i] ),`
173			`.i1 ( ni1[i] ),`
174			`.i2 ( ni2[i] ),`
175			`.i3 ( ni3[i] ),`
176			`.i4 ( ni4[i] ),`
177			`.oa ( n2ca[i] ),`
178			`.addrx ( addrx ),`
179	75	wsong0210	`.addry ( addry )`
180	13	wsong0210	`);`
181
182			`inp_buf #(.DIR(3), .RN(2), .DW(DW), .PD(IPD))`
183			`EIB (`
184			`.o0 ( e2c0[i] ),`
185			`.o1 ( e2c1[i] ),`
186			`.o2 ( e2c2[i] ),`
187			`.o3 ( e2c3[i] ),`
188			`.o4 ( e2c4[i] ),`
189			`.ia ( eia[i] ),`
190	75	wsong0210	`.deco ( ereq[i] ),`
191	13	wsong0210	`.rst_n ( rst_n ),`
192			`.i0 ( ei0[i] ),`
193			`.i1 ( ei1[i] ),`
194			`.i2 ( ei2[i] ),`
195			`.i3 ( ei3[i] ),`
196			`.i4 ( ei4[i] ),`
197			`.oa ( e2ca[i] ),`
198			`.addrx ( addrx ),`
199	75	wsong0210	`.addry ( addry )`
200	13	wsong0210	`);`
201
202			`inp_buf #(.DIR(4), .RN(4), .DW(DW), .PD(IPD))`
203			`LIB (`
204			`.o0 ( l2c0[i] ),`
205			`.o1 ( l2c1[i] ),`
206			`.o2 ( l2c2[i] ),`
207			`.o3 ( l2c3[i] ),`
208			`.o4 ( l2c4[i] ),`
209			`.ia ( lia[i] ),`
210	75	wsong0210	`.deco ( lreq[i] ),`
211	13	wsong0210	`.rst_n ( rst_n ),`
212			`.i0 ( li0[i] ),`
213			`.i1 ( li1[i] ),`
214			`.i2 ( li2[i] ),`
215			`.i3 ( li3[i] ),`
216			`.i4 ( li4[i] ),`
217			`.oa ( l2ca[i] ),`
218			`.addrx ( addrx ),`
219	75	wsong0210	`.addry ( addry )`
220	13	wsong0210	`);`
221
222			`// --------------------- output buffers ---------------- //`
223			`outp_buf #(.DW(DW), .PD(OPD))`
224			`SOB (`
225			`.o0 ( so0[i] ),`
226			`.o1 ( so1[i] ),`
227			`.o2 ( so2[i] ),`
228			`.o3 ( so3[i] ),`
229			`.o4 ( so4[i] ),`
230			`.oa ( soa[i] ),`
231			`.i0 ( c2s0[i] ),`
232			`.i1 ( c2s1[i] ),`
233			`.i2 ( c2s2[i] ),`
234			`.i3 ( c2s3[i] ),`
235			`.i4 ( c2s4[i] ),`
236			`.ia ( c2sa[i] ),`
237	75	wsong0210	`.ia4 ( c2sa4[i] ),`
238	13	wsong0210	`.rst_n ( rst_n )`
239			`);`
240
241			`outp_buf #(.DW(DW), .PD(OPD))`
242			`WOB (`
243			`.o0 ( wo0[i] ),`
244			`.o1 ( wo1[i] ),`
245			`.o2 ( wo2[i] ),`
246			`.o3 ( wo3[i] ),`
247			`.o4 ( wo4[i] ),`
248			`.oa ( woa[i] ),`
249			`.i0 ( c2w0[i] ),`
250			`.i1 ( c2w1[i] ),`
251			`.i2 ( c2w2[i] ),`
252			`.i3 ( c2w3[i] ),`
253			`.i4 ( c2w4[i] ),`
254			`.ia ( c2wa[i] ),`
255	75	wsong0210	`.ia4 ( c2wa4[i] ),`
256	13	wsong0210	`.rst_n ( rst_n )`
257			`);`
258
259			`outp_buf #(.DW(DW), .PD(OPD))`
260			`NOB (`
261			`.o0 ( no0[i] ),`
262			`.o1 ( no1[i] ),`
263			`.o2 ( no2[i] ),`
264			`.o3 ( no3[i] ),`
265			`.o4 ( no4[i] ),`
266			`.oa ( noa[i] ),`
267			`.i0 ( c2n0[i] ),`
268			`.i1 ( c2n1[i] ),`
269			`.i2 ( c2n2[i] ),`
270			`.i3 ( c2n3[i] ),`
271			`.i4 ( c2n4[i] ),`
272			`.ia ( c2na[i] ),`
273	75	wsong0210	`.ia4 ( c2na4[i] ),`
274	13	wsong0210	`.rst_n ( rst_n )`
275			`);`
276
277			`outp_buf #(.DW(DW), .PD(OPD))`
278			`EOB (`
279			`.o0 ( eo0[i] ),`
280			`.o1 ( eo1[i] ),`
281			`.o2 ( eo2[i] ),`
282			`.o3 ( eo3[i] ),`
283			`.o4 ( eo4[i] ),`
284			`.oa ( eoa[i] ),`
285			`.i0 ( c2e0[i] ),`
286			`.i1 ( c2e1[i] ),`
287			`.i2 ( c2e2[i] ),`
288			`.i3 ( c2e3[i] ),`
289			`.i4 ( c2e4[i] ),`
290			`.ia ( c2ea[i] ),`
291	75	wsong0210	`.ia4 ( c2ea4[i] ),`
292	13	wsong0210	`.rst_n ( rst_n )`
293			`);`
294
295			`outp_buf #(.DW(DW), .PD(OPD))`
296			`LOB (`
297			`.o0 ( lo0[i] ),`
298			`.o1 ( lo1[i] ),`
299			`.o2 ( lo2[i] ),`
300			`.o3 ( lo3[i] ),`
301			`.o4 ( lo4[i] ),`
302			`.oa ( loa[i] ),`
303			`.i0 ( c2l0[i] ),`
304			`.i1 ( c2l1[i] ),`
305			`.i2 ( c2l2[i] ),`
306			`.i3 ( c2l3[i] ),`
307			`.i4 ( c2l4[i] ),`
308			`.ia ( c2la[i] ),`
309	75	wsong0210	`.ia4 ( c2la4[i] ),`
310	13	wsong0210	`.rst_n ( rst_n )`
311			`);`
312
313			`end // block: SC`
314			`endgenerate`
315
316			`ifdef ENABLE_CLOS
317	75	wsong0210	`clos #(.MN(VCN), .NN(VCN), .DW(DW))`
318	13	wsong0210	`CB (`
319			`.so0 ( c2s0 ),`
320			`.so1 ( c2s1 ),`
321			`.so2 ( c2s2 ),`
322			`.so3 ( c2s3 ),`
323			`.so4 ( c2s4 ),`
324			`.soa ( c2sa ),`
325	75	wsong0210	`.soa4 ( c2sa4 ),`
326	13	wsong0210	`.wo0 ( c2w0 ),`
327			`.wo1 ( c2w1 ),`
328			`.wo2 ( c2w2 ),`
329			`.wo3 ( c2w3 ),`
330			`.wo4 ( c2w4 ),`
331			`.woa ( c2wa ),`
332	75	wsong0210	`.woa4 ( c2wa4 ),`
333	13	wsong0210	`.no0 ( c2n0 ),`
334			`.no1 ( c2n1 ),`
335			`.no2 ( c2n2 ),`
336			`.no3 ( c2n3 ),`
337			`.no4 ( c2n4 ),`
338			`.noa ( c2na ),`
339	75	wsong0210	`.noa4 ( c2na4 ),`
340	13	wsong0210	`.eo0 ( c2e0 ),`
341			`.eo1 ( c2e1 ),`
342			`.eo2 ( c2e2 ),`
343			`.eo3 ( c2e3 ),`
344			`.eo4 ( c2e4 ),`
345			`.eoa ( c2ea ),`
346	75	wsong0210	`.eoa4 ( c2ea4 ),`
347	13	wsong0210	`.lo0 ( c2l0 ),`
348			`.lo1 ( c2l1 ),`
349			`.lo2 ( c2l2 ),`
350			`.lo3 ( c2l3 ),`
351			`.lo4 ( c2l4 ),`
352			`.loa ( c2la ),`
353	75	wsong0210	`.loa4 ( c2la4 ),`
354	13	wsong0210	`.si0 ( s2c0 ),`
355			`.si1 ( s2c1 ),`
356			`.si2 ( s2c2 ),`
357			`.si3 ( s2c3 ),`
358			`.si4 ( s2c4 ),`
359			`.sia ( s2ca ),`
360			`.wi0 ( w2c0 ),`
361			`.wi1 ( w2c1 ),`
362			`.wi2 ( w2c2 ),`
363			`.wi3 ( w2c3 ),`
364			`.wi4 ( w2c4 ),`
365			`.wia ( w2ca ),`
366			`.ni0 ( n2c0 ),`
367			`.ni1 ( n2c1 ),`
368			`.ni2 ( n2c2 ),`
369			`.ni3 ( n2c3 ),`
370			`.ni4 ( n2c4 ),`
371			`.nia ( n2ca ),`
372			`.ei0 ( e2c0 ),`
373			`.ei1 ( e2c1 ),`
374			`.ei2 ( e2c2 ),`
375			`.ei3 ( e2c3 ),`
376			`.ei4 ( e2c4 ),`
377			`.eia ( e2ca ),`
378			`.li0 ( l2c0 ),`
379			`.li1 ( l2c1 ),`
380			`.li2 ( l2c2 ),`
381			`.li3 ( l2c3 ),`
382			`.li4 ( l2c4 ),`
383			`.lia ( l2ca ),`
384	75	wsong0210	`.rst_n ( rst_n )`
385	13	wsong0210	`) ;`
386
387			`else // Crossbar based SDM
388
389	28	wsong0210	`dcb_xy #(.VCN(VCN), .VCW(DW))`
390	13	wsong0210	`CB (`
391			`.so0 ( c2s0 ),`
392			`.so1 ( c2s1 ),`
393			`.so2 ( c2s2 ),`
394			`.so3 ( c2s3 ),`
395			`.so4 ( c2s4 ),`
396			`.soa ( c2sa ),`
397			`.wo0 ( c2w0 ),`
398			`.wo1 ( c2w1 ),`
399			`.wo2 ( c2w2 ),`
400			`.wo3 ( c2w3 ),`
401			`.wo4 ( c2w4 ),`
402			`.woa ( c2wa ),`
403			`.no0 ( c2n0 ),`
404			`.no1 ( c2n1 ),`
405			`.no2 ( c2n2 ),`
406			`.no3 ( c2n3 ),`
407			`.no4 ( c2n4 ),`
408			`.noa ( c2na ),`
409			`.eo0 ( c2e0 ),`
410			`.eo1 ( c2e1 ),`
411			`.eo2 ( c2e2 ),`
412			`.eo3 ( c2e3 ),`
413			`.eo4 ( c2e4 ),`
414			`.eoa ( c2ea ),`
415			`.lo0 ( c2l0 ),`
416			`.lo1 ( c2l1 ),`
417			`.lo2 ( c2l2 ),`
418			`.lo3 ( c2l3 ),`
419			`.lo4 ( c2l4 ),`
420			`.loa ( c2la ),`
421			`.si0 ( s2c0 ),`
422			`.si1 ( s2c1 ),`
423			`.si2 ( s2c2 ),`
424			`.si3 ( s2c3 ),`
425			`.si4 ( s2c4 ),`
426			`.sia ( s2ca ),`
427			`.wi0 ( w2c0 ),`
428			`.wi1 ( w2c1 ),`
429			`.wi2 ( w2c2 ),`
430			`.wi3 ( w2c3 ),`
431			`.wi4 ( w2c4 ),`
432			`.wia ( w2ca ),`
433			`.ni0 ( n2c0 ),`
434			`.ni1 ( n2c1 ),`
435			`.ni2 ( n2c2 ),`
436			`.ni3 ( n2c3 ),`
437			`.ni4 ( n2c4 ),`
438			`.nia ( n2ca ),`
439			`.ei0 ( e2c0 ),`
440			`.ei1 ( e2c1 ),`
441			`.ei2 ( e2c2 ),`
442			`.ei3 ( e2c3 ),`
443			`.ei4 ( e2c4 ),`
444			`.eia ( e2ca ),`
445			`.li0 ( l2c0 ),`
446			`.li1 ( l2c1 ),`
447			`.li2 ( l2c2 ),`
448			`.li3 ( l2c3 ),`
449			`.li4 ( l2c4 ),`
450			`.lia ( l2ca ),`
451			`.wcfg ( wcfg ),`
452			`.ecfg ( ecfg ),`
453			`.lcfg ( lcfg ),`
454			`.scfg ( scfg ),`
455			`.ncfg ( ncfg )`
456			`) ;`
457
458
459			`sdm_sch #(.VCN(VCN))`
460			`ALLOC (`
461			`.sack ( sack ),`
462			`.wack ( wack ),`
463			`.nack ( nack ),`
464			`.eack ( eack ),`
465			`.lack ( lack ),`
466			`.scfg ( scfg ),`
467			`.ncfg ( ncfg ),`
468			`.wcfg ( wcfg ),`
469			`.ecfg ( ecfg ),`
470			`.lcfg ( lcfg ),`
471			`.sreq ( sreq ),`
472			`.nreq ( nreq ),`
473			`.lreq ( lreq ),`
474			`.wreq ( wreq ),`
475	19	wsong0210	`.ereq ( ereq ),`
476			`.rst_n ( rst_n )`
477	13	wsong0210	`);`
478			`endif
479
480			`endmodule // router`

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