Subversion Repositories async_sdm_noc

# the STG for the controller of the last stage of input buffers

# eofa- is intentionally postponed after doa- for simplier circuit

# it is assumed dec+ happen before hdd(do+) already in realy circuits they can occure simultaneously

# However, this assumption simplify the STG and do not cause any malfunction in real circuit

# the control circuit generated by Petrify is ibctl.v

# using command: petrify ibctl.g -vl ibctl.v -rst0 -topt -icsc5 -fr10 -o ibctl.g.csc

#

# Wei Song, 16/06/2011 

.model ibctl

.inputs dec do doa eof

.outputs dia eofa deca

.dummy hdd data_data

.initial state eofa deca

.graph

Data do+/1

do+/1 dia+/1

do+/1 doa+/1

dia+/1 do-/1

doa+/1 do-/1

do-/1 dia-/1

do-/1 doa-/1

dia-/1 data_data

doa-/1 data_data

data_data Data

Data eof+

eof+ dia+/2

eof+ doa+/2

doa+/2 deca-

deca- dec-

dec- doa-/2

doa+/2 eofa-

eofa- eof-

dia+/2 eof-

eof- doa-/2

eof- dia-/2

dec- dia-/2

doa-/2 deca+

doa-/2 eofa+

dia-/2 dec+

deca+ dec+

dec+ hdd

eofa+ hdd

hdd Data

.marking {  }

.end