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// Verilog model for ibctl 

// Generated by petrify 4.2 (compiled 15-Oct-03 at 3:06 PM)

// CPU time for synthesis (host <unknown>): 0.11 seconds

// Estimated area = 11.00

// The circuit is self-resetting and does not need reset pin.

module ibctl_net (

    dec,

    do,

    doa,

    eof,

    dia,

    eofa,

    deca

);

input dec;

input do;

input doa;

input eof;

output dia;

output eofa;

output deca;

// Functions not mapped into library gates:

// ----------------------------------------

// Equation: dia = dia eofa' dec + eof + do

not _U0 (_X0, eofa);

and _U1 (_X1, dia, _X0, dec);

or _U2 (dia, do, eof, _X1);

// Equation: eofa = eof' eofa + doa'

not _U3 (_X2, doa);

not _U4 (_X3, eof);

and _U5 (_X4, _X3, eofa);

or _U6 (eofa, _X2, _X4);

// Equation: deca = eof' eofa + doa'

not _U7 (_X5, doa);

not _U8 (_X6, eof);

and _U9 (_X7, _X6, eofa);

or _U10 (deca, _X5, _X7);

// signal values at the initial state:

//     !dec !do !doa !eof !dia eofa deca

endmodule