| 1 |
10 |
wsong0210 |
# Asynchronous SDM NoC
|
| 2 |
|
|
# (C)2011 Wei Song
|
| 3 |
|
|
# Advanced Processor Technologies Group
|
| 4 |
|
|
# Computer Science, the Univ. of Manchester, UK
|
| 5 |
|
|
#
|
| 6 |
|
|
# Authors:
|
| 7 |
|
|
# Wei Song wsong83@gmail.com
|
| 8 |
|
|
#
|
| 9 |
|
|
# License: LGPL 3.0 or later
|
| 10 |
|
|
#
|
| 11 |
|
|
# Disable the timing loops in asynchronous cells
|
| 12 |
|
|
# currently using the Nangate 45nm cell lib.
|
| 13 |
|
|
#
|
| 14 |
|
|
# History:
|
| 15 |
|
|
# 03/07/2009 Initial version. <wsong83@gmail.com>
|
| 16 |
28 |
wsong0210 |
# 27/05/2011 Change to the Nangate cell library. <wsong83@gmail.com>
|
| 17 |
10 |
wsong0210 |
|
| 18 |
28 |
wsong0210 |
set_dont_touch mutex2
|
| 19 |
10 |
wsong0210 |
set_dont_touch delay
|
| 20 |
28 |
wsong0210 |
# It is not a problem if there is no delay cells in the design.
|
| 21 |
10 |
wsong0210 |
|
| 22 |
|
|
uniquify -force
|
| 23 |
|
|
|
| 24 |
|
|
# C-gates on control path
|
| 25 |
|
|
foreach_in_collection celln [get_references -hierarchical c2_*] {
|
| 26 |
|
|
set_disable_timing [get_object_name $celln]/U2 -from B -to Z
|
| 27 |
|
|
set_disable_timing [get_object_name $celln]/U3 -from B -to Z
|
| 28 |
|
|
}
|
| 29 |
|
|
|
| 30 |
|
|
# C-gates on data path, feedback and data input are disabled from timing analysis
|
| 31 |
|
|
foreach_in_collection celln [get_references -hierarchical dc2_*] {
|
| 32 |
|
|
set_disable_timing [get_object_name $celln]/U1 -from B -to Z
|
| 33 |
|
|
set_disable_timing [get_object_name $celln]/U2 -from A -to Z
|
| 34 |
|
|
set_disable_timing [get_object_name $celln]/U2 -from B -to Z
|
| 35 |
|
|
set_disable_timing [get_object_name $celln]/U3 -from B -to Z
|
| 36 |
|
|
}
|
| 37 |
|
|
|
| 38 |
|
|
# c2n gates
|
| 39 |
|
|
foreach_in_collection celln [get_references -hierarchical c2n_*] {
|
| 40 |
|
|
set_disable_timing [get_object_name $celln]/U1 -from B -to Z
|
| 41 |
|
|
}
|
| 42 |
28 |
wsong0210 |
# It is not a problem if there is no c2n cells in the design.
|
| 43 |
10 |
wsong0210 |
|
| 44 |
|
|
# c2p gates
|
| 45 |
|
|
foreach_in_collection celln [get_references -hierarchical c2p_*] {
|
| 46 |
28 |
wsong0210 |
set_disable_timing [get_object_name $celln]/U1 -from B -to Z
|
| 47 |
10 |
wsong0210 |
}
|
| 48 |
28 |
wsong0210 |
# It is not a problem if there is no c2p cells in the design.
|
| 49 |
10 |
wsong0210 |
|
| 50 |
|
|
# mutex gates
|
| 51 |
28 |
wsong0210 |
foreach_in_collection celln [get_references -hierarchical mutex2_*] {
|
| 52 |
10 |
wsong0210 |
set_disable_timing [get_object_name $celln]/U1 -from A2 -to ZN
|
| 53 |
|
|
set_disable_timing [get_object_name $celln]/U4 -from A2 -to ZN
|
| 54 |
|
|
set_dont_touch [get_object_name $celln]/U2
|
| 55 |
|
|
set_dont_touch [get_object_name $celln]/U3
|
| 56 |
|
|
}
|
| 57 |
|
|
|
| 58 |
|
|
# c2p1 gates
|
| 59 |
|
|
foreach_in_collection celln [get_references -hierarchical c2p1_*] {
|
| 60 |
|
|
set_disable_timing [get_object_name $celln]/U2 -from B -to Z
|
| 61 |
|
|
set_disable_timing [get_object_name $celln]/U3 -from B -to Z
|
| 62 |
|
|
}
|
| 63 |
28 |
wsong0210 |
# It is not a problem if MRMA is not used in the design.
|
| 64 |
10 |
wsong0210 |
|
| 65 |
|
|
# tarb
|
| 66 |
|
|
foreach_in_collection celln [get_references -hierarchical tarb_*] {
|
| 67 |
|
|
set_disable_timing [get_object_name $celln]/U2 -from A -to Z
|
| 68 |
|
|
set_disable_timing [get_object_name $celln]/U3 -from A -to Z
|
| 69 |
|
|
}
|
| 70 |
28 |
wsong0210 |
# It is not a problem if tree arbiter is not used in the design.
|
| 71 |
10 |
wsong0210 |
|
| 72 |
|
|
# cr_blk
|
| 73 |
|
|
foreach_in_collection celln [get_references -hierarchical cr_blk_*] {
|
| 74 |
|
|
set_disable_timing [get_object_name $celln]/XG/U1 -from C -to Z
|
| 75 |
|
|
}
|
| 76 |
28 |
wsong0210 |
# It is not a problem if MRMA is not used in the design.
|
| 77 |
10 |
wsong0210 |
|
| 78 |
28 |
wsong0210 |
# mrma multi-resource match arbiter
|
| 79 |
|
|
foreach_in_collection celln [get_references -hierarchical mrma_*] {
|
| 80 |
|
|
set_disable_timing [get_object_name $celln]/*.AND_*G* -from B -to Z
|
| 81 |
|
|
set_disable_timing [get_object_name $celln]/*.AND_RG* -from A -to Z
|
| 82 |
|
|
}
|
| 83 |
|
|
# It is not a problem if MRMA is not used in the design.
|
| 84 |
|
|
|
| 85 |
|
|
# dcb data crossbar
|
| 86 |
|
|
foreach_in_collection celln [get_references -hierarchical dcb_*] {
|
| 87 |
|
|
set_disable_timing [get_object_name $celln]/*.A* -from B -to Z
|
| 88 |
|
|
}
|
| 89 |
|
|
|
| 90 |
|
|
# dcb data crossbar
|
| 91 |
|
|
foreach_in_collection celln [get_references -hierarchical rcb_*] {
|
| 92 |
|
|
set_disable_timing [get_object_name $celln]/*.A* -from B -to Z
|
| 93 |
|
|
}
|
| 94 |
|
|
#It is not a problem if there is no rcb modules in the design.
|
| 95 |
|
|
|
| 96 |
|
|
# mnmr m-n match allocator
|
| 97 |
|
|
foreach_in_collection celln [get_references -hierarchical mnma_*] {
|
| 98 |
|
|
set_disable_timing [get_object_name $celln]/*.AND_OPRen* -from B -to Z
|
| 99 |
|
|
}
|
| 100 |
|
|
#It is not a problem if MNMA is not used in the design.
|
