OpenCores
URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [branches/] [clos_opt/] [common/] [src/] [cb_xy.v] - Blame information for rev 70

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 wsong0210
/*
2
 Asynchronous SDM NoC
3
 (C)2011 Wei Song
4
 Advanced Processor Technologies Group
5
 Computer Science, the Univ. of Manchester, UK
6
 
7
 Authors:
8
 Wei Song     wsong83@gmail.com
9
 
10
 License: LGPL 3.0 or later
11
 
12 70 wsong0210
 Unidirectional crossbar using the XY routing algorithm.
13 12 wsong0210
 *** SystemVerilog is used ***
14
 
15
 History:
16 70 wsong0210
 09/07/2009  Initial version. <wsong83@gmail.com>
17 63 wsong0210
 
18 12 wsong0210
*/
19
 
20
// the router structure definitions
21
 
22 70 wsong0210
module cb_xy (/*AUTOARG*/
23 12 wsong0210
   // Outputs
24 70 wsong0210
   so, wo, no, eo, lo,
25 12 wsong0210
   // Inputs
26 70 wsong0210
   si, wi, ni, ei, li, scfg, ncfg, wcfg, ecfg, lcfg
27 12 wsong0210
   ) ;
28
 
29 70 wsong0210
   parameter DW = 8;            // the wire count of the crossbar
30 12 wsong0210
 
31 70 wsong0210
   input [DW-1:0]      si, wi, ni, ei, li; // data input
32
   output [DW-1:0]     so, wo, no, eo, lo; // data output
33
   input [1:0]          scfg, ncfg;         // configuration
34
   input [3:0]          wcfg, ecfg, lcfg;   // configuration
35 12 wsong0210
 
36
   // ANDed wires
37 70 wsong0210
   wire [DW-1:0][1:0]  tos, ton;
38
   wire [DW-1:0][3:0]  tow, toe, tol;
39
 
40 12 wsong0210
   // generate
41 70 wsong0210
   genvar                     i, j;
42 12 wsong0210
 
43 70 wsong0210
   generate for (i=0; i<DW; i=i+1)
44
     begin:OPA
45
        and AN2S (tos[i][0], ni[i], scfg[0]);
46
        and AL2S (tos[i][1], li[i], scfg[1]);
47
        assign so[i] = |tos[i];
48 12 wsong0210
 
49 70 wsong0210
        and AS2W (tow[i][0], si[i], wcfg[0]);
50
        and AN2W (tow[i][1], ni[i], wcfg[1]);
51
        and AE2W (tow[i][2], ei[i], wcfg[2]);
52
        and AL2W (tow[i][3], li[i], wcfg[3]);
53
        assign wo[i] = |tow[i];
54 12 wsong0210
 
55 70 wsong0210
        and AS2N (ton[i][0], si[i], ncfg[0]);
56
        and AL2N (ton[i][1], li[i], ncfg[1]);
57
        assign no[i] = |ton[i];
58 12 wsong0210
 
59 70 wsong0210
        and AS2E (toe[i][0], si[i], ecfg[0]);
60
        and AW2E (toe[i][1], wi[i], ecfg[1]);
61
        and AN2E (toe[i][2], ni[i], ecfg[2]);
62
        and AL2E (toe[i][3], li[i], ecfg[3]);
63
        assign eo[i] = |toe[i];
64 12 wsong0210
 
65 70 wsong0210
        and AS2L (tol[i][0], si[i], lcfg[0]);
66
        and AW2L (tol[i][1], wi[i], lcfg[1]);
67
        and AN2L (tol[i][2], ni[i], lcfg[2]);
68
        and AE2L (tol[i][3], ei[i], lcfg[3]);
69
        assign lo[i] = |tol[i];
70
     end // block: OPA
71
   endgenerate
72 12 wsong0210
 
73 70 wsong0210
endmodule // cb_xy
74 12 wsong0210
 
75
 
76
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.