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1 11 wsong0210
/*
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 Asynchronous SDM NoC
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 (C)2011 Wei Song
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 Advanced Processor Technologies Group
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 Computer Science, the Univ. of Manchester, UK
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 Authors:
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 Wei Song     wsong83@gmail.com
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 License: LGPL 3.0 or later
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 C-element tree, usually for common ack generation.
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 *** SystemVerilog is used ***
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 History:
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 17/04/2011  Initial version. <wsong83@gmail.com>
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 23/05/2011  Clean up for opensource. <wsong83@gmail.com>
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*/
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module ctree (/*AUTOARG*/
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   // Outputs
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   co,
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   // Inputs
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   ci
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   );
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   parameter DW = 2;            // the total number of leaves of the C-element tree
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   input [DW-1:0] ci;            // all input leaves
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   output         co;           // the combined output
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   wire [2*DW-2:0] dat;
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   genvar          i;
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   assign dat[DW-1:0] = ci;
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   generate for (i=0; i<DW-1; i=i+1) begin:AT
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       c2 CT (.a0(dat[i*2]), .a1(dat[i*2+1]), .q(dat[i+DW]));
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   end endgenerate
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   assign co = dat[2*DW-2];
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endmodule // ctree
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