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1 12 wsong0210 
/*
2 
 Asynchronous SDM NoC
3 
 (C)2011 Wei Song
4 
 Advanced Processor Technologies Group
5 
 Computer Science, the Univ. of Manchester, UK
6 
 
7 
 Authors:
8 
 Wei Song     wsong83@gmail.com
9 
 
10 
 License: LGPL 3.0 or later
11 
 
12 
 Data crossbar for wormhole and SDM routers.
13 
 Optimized by removing disabled turn models according to the XY routing algorithm.
14 
 *** SystemVerilog is used ***
15 
 
16 
 History:
17 
 21/08/2009  Initial version. <wsong83@gmail.com>
18 
 20/09/2010  Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
19 
 23/05/2011  Clean up for opensource. <wsong83@gmail.com>
20 63 wsong0210 
 22/06/2011  Prepare to support buffered Clos. <wsong83@gmail.com>
21 
 
22 12 wsong0210 
*/
23 
 
24 
// the router structure definitions
25 
`include "define.v"
26 
 
27 63 wsong0210 
module dcb_xy (
28 12 wsong0210 
   // Outputs
29 
   so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
30 
   eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, sia, wo4, wia, no4, nia,
31 
   eo4, eia, lo4, lia,
32 
   // Inputs
33 
   si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
34 
   ei1, ei2, ei3, li0, li1, li2, li3, si4, soa, wi4, woa, ni4, noa,
35 
   ei4, eoa, li4, loa, scfg, ncfg, wcfg, ecfg, lcfg
36 63 wsong0210 
`ifdef ENABLE_BUFFERED_CLOS
37 
   , soa4, woa4, noa4, eoa4, loa4
38 
`endif
39 12 wsong0210 
   ) ;
40 
 
41 
   parameter VCN = 1;           // number of virtual circuits per port
42 
   parameter VCW = 8;           // the datawidth of a single virtual circuit
43 
   parameter SCN = VCW/2;       // number of 1-of-4 sub-channels in one virtual circuit
44 
 
45 
   input [VCN-1:0][SCN-1:0]    si0, si1, si2, si3; // south input, X+1
46 
   output [VCN-1:0][SCN-1:0]   so0, so1, so2, so3; // south output
47 
   input [VCN-1:0][SCN-1:0]    wi0, wi1, wi2, wi3; // west input, Y-1
48 
   output [VCN-1:0][SCN-1:0]   wo0, wo1, wo2, wo3; // west output
49 
   input [VCN-1:0][SCN-1:0]    ni0, ni1, ni2, ni3; // north input, X-1
50 
   output [VCN-1:0][SCN-1:0]   no0, no1, no2, no3; // north output
51 
   input [VCN-1:0][SCN-1:0]    ei0, ei1, ei2, ei3; // east input, Y+1
52 
   output [VCN-1:0][SCN-1:0]   eo0, eo1, eo2, eo3; // east output
53 
   input [VCN-1:0][SCN-1:0]    li0, li1, li2, li3; // local input
54 
   output [VCN-1:0][SCN-1:0]   lo0, lo1, lo2, lo3; // local output
55 
 
56 
   // ack and eof bits
57 
`ifdef ENABLE_CHANNEL_SLICING
58 
   input [VCN-1:0][SCN-1:0]    si4, soa;
59 
   output [VCN-1:0][SCN-1:0]   so4, sia;
60 
   input [VCN-1:0][SCN-1:0]    wi4, woa;
61 
   output [VCN-1:0][SCN-1:0]   wo4, wia;
62 
   input [VCN-1:0][SCN-1:0]    ni4, noa;
63 
   output [VCN-1:0][SCN-1:0]   no4, nia;
64 
   input [VCN-1:0][SCN-1:0]    ei4, eoa;
65 
   output [VCN-1:0][SCN-1:0]   eo4, eia;
66 
   input [VCN-1:0][SCN-1:0]    li4, loa;
67 
   output [VCN-1:0][SCN-1:0]   lo4, lia;
68 63 wsong0210 
 `ifdef ENABLE_BUFFERED_CLOS
69 
   input [VCN-1:0][SCN-1:0]    soa4, woa4, noa4, eoa4, loa4;
70 
 `endif
71 12 wsong0210 
`else // !`ifdef ENABLE_CHANNEL_SLICING
72 
   input [VCN-1:0]              si4, soa;
73 
   output [VCN-1:0]             so4, sia;
74 
   input [VCN-1:0]              wi4, woa;
75 
   output [VCN-1:0]             wo4, wia;
76 
   input [VCN-1:0]              ni4, noa;
77 
   output [VCN-1:0]             no4, nia;
78 
   input [VCN-1:0]              ei4, eoa;
79 
   output [VCN-1:0]             eo4, eia;
80 
   input [VCN-1:0]              li4, loa;
81 
   output [VCN-1:0]             lo4, lia;
82 63 wsong0210 
 `ifdef ENABLE_BUFFERED_CLOS
83 
   input [VCN-1:0]              soa4, woa4, noa4, eoa4, loa4;
84 
 `endif
85 12 wsong0210 
`endif
86 
 
87 
   // configurations
88 
   input [VCN-1:0][1:0][VCN-1:0]        scfg, ncfg;
89 
   input [VCN-1:0][3:0][VCN-1:0]        wcfg, ecfg, lcfg;
90 
 
91 
   // ANDed wires
92 
   wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] tos0, tos1, tos2, tos3;     // the wires to the south output port
93 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] tow0, tow1, tow2, tow3;     // the wires to the west output port
94 
   wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] ton0, ton1, ton2, ton3;     // the wires to the north output port
95 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] toe0, toe1, toe2, toe3;     // the wires to the east output port
96 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] tol0, tol1, tol2, tol3;     // the wires to the local output port
97 
 
98 
`ifdef ENABLE_CHANNEL_SLICING
99 
   wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] tos4, tosa;                 // the wires to the south output port
100 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] tow4, towa;                 // the wires to the west output port
101 
   wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] ton4, tona;                 // the wires to the north output port
102 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] toe4, toea;                 // the wires to the east output port
103 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] tol4, tola;                 // the wires to the local output port
104 
 
105 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] isa;                        // ack back to south
106 
   wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] iwa;                        // ack back to west
107 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] ina;                        // ack back to north
108 
   wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] iea;                        // ack back to east
109 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] ila;                        // ack back to local
110 63 wsong0210 
 `ifdef ENABLE_BUFFERED_CLOS
111 
   wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] tosad, tosa4, tonad, tona4;
112 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] towad, towa4, toead, toea4, tolad, tola4;
113 
 `endif
114 12 wsong0210 
`else // !`ifdef ENABLE_CHANNEL_SLICING
115 
   wire [VCN-1:0][1:0][VCN-1:0] tos4, tosa;                 // the wires to the south output port
116 
   wire [VCN-1:0][3:0][VCN-1:0] tow4, towa;                 // the wires to the west output port
117 
   wire [VCN-1:0][1:0][VCN-1:0] ton4, tona;                 // the wires to the north output port
118 
   wire [VCN-1:0][3:0][VCN-1:0] toe4, toea;                 // the wires to the east output port
119 
   wire [VCN-1:0][3:0][VCN-1:0] tol4, tola;                 // the wires to the local output port
120 
 
121 
   wire [VCN-1:0][3:0][VCN-1:0] isa;                        // ack back to south
122 
   wire [VCN-1:0][1:0][VCN-1:0] iwa;                        // ack back to west
123 
   wire [VCN-1:0][3:0][VCN-1:0] ina;                        // ack back to north
124 
   wire [VCN-1:0][1:0][VCN-1:0] iea;                        // ack back to east
125 
   wire [VCN-1:0][3:0][VCN-1:0] ila;                        // ack back to local
126 
 
127 63 wsong0210 
 `ifdef ENABLE_BUFFERED_CLOS
128 
   wire [VCN-1:0][1:0][VCN-1:0] tosad, tosa4, tonad, tona4;
129 
   wire [VCN-1:0][3:0][VCN-1:0] towad, towa4, toead, toea4, tolad, tola4;
130 
 `endif
131 12 wsong0210 
`endif // !`ifdef ENABLE_CHANNEL_SLICING
132 
 
133 
   // generate
134 
   genvar                     i, j, k;
135 
 
136 
 
137 
   /*---------------------------- SOUTH OUPUT -------------------------------------*/
138 
   generate for (i=0; i<VCN; i=i+1)
139 
     begin:SOP
140 
        for(j=0; j<VCN; j++) begin: V
141 
           for(k=0; k<SCN; k++) begin: SC
142 
              and AN0 (tos0[i][k][0][j], ni0[j][k], scfg[i][0][j]);
143 
              and AN1 (tos1[i][k][0][j], ni1[j][k], scfg[i][0][j]);
144 
              and AN2 (tos2[i][k][0][j], ni2[j][k], scfg[i][0][j]);
145 
              and AN3 (tos3[i][k][0][j], ni3[j][k], scfg[i][0][j]);
146 
              and AL0 (tos0[i][k][1][j], li0[j][k], scfg[i][1][j]);
147 
              and AL1 (tos1[i][k][1][j], li1[j][k], scfg[i][1][j]);
148 
              and AL2 (tos2[i][k][1][j], li2[j][k], scfg[i][1][j]);
149 
              and AL3 (tos3[i][k][1][j], li3[j][k], scfg[i][1][j]);
150 
`ifdef ENABLE_CHANNEL_SLICING
151 
              and AN4 (tos4[i][k][0][j], ni4[j][k], scfg[i][0][j]);
152 
              and AL4 (tos4[i][k][1][j], li4[j][k], scfg[i][1][j]);
153 63 wsong0210 
 `ifdef ENABLE_BUFFERED_CLOS
154 
              and ALAd (tosad[i][k][1][j], soa[i][k], scfg[i][1][j]);
155 
              and ANAd (tosad[i][k][0][j], soa[i][k], scfg[i][0][j]);
156 
              c2 ALA4 (.q(tosa4[i][k][1][j]), .a0(soa4[i][k]), .a1(scfg[i][1][j]));
157 
              c2 ANA4 (.q(tosa4[i][k][0][j]), .a0(soa4[i][k]), .a1(scfg[i][0][j]));
158 
              assign tosa[i][k][1][j] = tosad[i][k][1][j] | tosa4[i][k][1][j];
159 
              assign tosa[i][k][0][j] = tosad[i][k][0][j] | tosa4[i][k][0][j];
160 
 `else
161 12 wsong0210 
              and ALA (tosa[i][k][1][j], soa[i][k], scfg[i][1][j]);
162 63 wsong0210 
              and ANA (tosa[i][k][0][j], soa[i][k], scfg[i][0][j]);
163 
 `endif
164 12 wsong0210 
`endif
165 
           end // block: SC
166 
`ifndef ENABLE_CHANNEL_SLICING
167 
           and AN4 (tos4[i][0][j], ni4[j], scfg[i][0][j]);
168 63 wsong0210 
           and AL4 (tos4[i][1][j], li4[j], scfg[i][1][j]);
169 
 `ifdef ENABLE_BUFFERED_CLOS
170 
           and ANAd (tosad[i][0][j], soa[i], scfg[i][0][j]);
171 
           and ALAd (tosad[i][1][j], soa[i], scfg[i][1][j]);
172 
           c2 ANA4 (.q(tosa4[i][0][j]), .a0(soa4[i]), .a1(scfg[i][0][j]));
173 
           c2 ALA4 (.q(tosa4[i][1][j]), .a0(soa4[i]), .a1(scfg[i][1][j]));
174 
           assign tosa[i][0][j] = tosad[i][0][j] | tosa4[i][0][j];
175 
           assign tosa[i][1][j] = tosad[i][0][j] | tosa4[i][1][j];
176 
 `else
177 12 wsong0210 
           and ANA (tosa[i][0][j], soa[i], scfg[i][0][j]);
178 
           and ALA (tosa[i][1][j], soa[i], scfg[i][1][j]);
179 63 wsong0210 
 `endif
180 12 wsong0210 
`endif
181 
        end // block: V
182 
 
183 
        for(k=0; k<SCN; k++) begin: SCOR
184 
           assign so0[i][k] = |(tos0[i][k][0]|tos0[i][k][1]);
185 
           assign so1[i][k] = |(tos1[i][k][0]|tos1[i][k][1]);
186 
           assign so2[i][k] = |(tos2[i][k][0]|tos2[i][k][1]);
187 
           assign so3[i][k] = |(tos3[i][k][0]|tos3[i][k][1]);
188 
`ifdef ENABLE_CHANNEL_SLICING
189 
           assign so4[i][k] = |(tos4[i][k][0]|tos4[i][k][1]);
190 
`endif
191 
        end
192 
`ifndef ENABLE_CHANNEL_SLICING
193 
        assign so4[i] = |(tos4[i][0]|tos4[i][1]);
194 
`endif
195 
     end
196 
   endgenerate
197 
 
198 
   /*---------------------------- WEST OUPUT -------------------------------------*/
199 
   generate for (i=0; i<VCN; i=i+1)
200 
     begin:WOP
201 
        for(j=0; j<VCN; j++) begin: V
202 
           for(k=0; k<SCN; k++) begin: SC
203 
              and AS0 (tow0[i][k][0][j], si0[j][k], wcfg[i][0][j]);
204 
              and AS1 (tow1[i][k][0][j], si1[j][k], wcfg[i][0][j]);
205 
              and AS2 (tow2[i][k][0][j], si2[j][k], wcfg[i][0][j]);
206 
              and AS3 (tow3[i][k][0][j], si3[j][k], wcfg[i][0][j]);
207 
              and AN0 (tow0[i][k][1][j], ni0[j][k], wcfg[i][1][j]);
208 
              and AN1 (tow1[i][k][1][j], ni1[j][k], wcfg[i][1][j]);
209 
              and AN2 (tow2[i][k][1][j], ni2[j][k], wcfg[i][1][j]);
210 
              and AN3 (tow3[i][k][1][j], ni3[j][k], wcfg[i][1][j]);
211 
              and AE0 (tow0[i][k][2][j], ei0[j][k], wcfg[i][2][j]);
212 
              and AE1 (tow1[i][k][2][j], ei1[j][k], wcfg[i][2][j]);
213 
              and AE2 (tow2[i][k][2][j], ei2[j][k], wcfg[i][2][j]);
214 
              and AE3 (tow3[i][k][2][j], ei3[j][k], wcfg[i][2][j]);
215 
              and AL0 (tow0[i][k][3][j], li0[j][k], wcfg[i][3][j]);
216 
              and AL1 (tow1[i][k][3][j], li1[j][k], wcfg[i][3][j]);
217 
              and AL2 (tow2[i][k][3][j], li2[j][k], wcfg[i][3][j]);
218 
              and AL3 (tow3[i][k][3][j], li3[j][k], wcfg[i][3][j]);
219 
`ifdef ENABLE_CHANNEL_SLICING
220 
              and AS4 (tow4[i][k][0][j], si4[j][k], wcfg[i][0][j]);
221 63 wsong0210 
              and AN4 (tow4[i][k][1][j], ni4[j][k], wcfg[i][1][j]);
222 
              and AE4 (tow4[i][k][2][j], ei4[j][k], wcfg[i][2][j]);
223 
              and AL4 (tow4[i][k][3][j], li4[j][k], wcfg[i][3][j]);
224 
 `ifdef ENABLE_BUFFERED_CLOS
225 
              and ASAd (towad[i][k][0][j], woa[i][k], wcfg[i][0][j]);
226 
              and ANAd (towad[i][k][1][j], woa[i][k], wcfg[i][1][j]);
227 
              and AEAd (towad[i][k][2][j], woa[i][k], wcfg[i][2][j]);
228 
              and ALAd (towad[i][k][3][j], woa[i][k], wcfg[i][3][j]);
229 
              c2 ASA4 (.q(towa4[i][k][0][j]), .a0(woa4[i][k]), .a1(wcfg[i][0][j]));
230 
              c2 ANA4 (.q(towa4[i][k][1][j]), .a0(woa4[i][k]), .a1(wcfg[i][1][j]));
231 
              c2 AEA4 (.q(towa4[i][k][2][j]), .a0(woa4[i][k]), .a1(wcfg[i][2][j]));
232 
              c2 ALA4 (.q(towa4[i][k][3][j]), .a0(woa4[i][k]), .a1(wcfg[i][3][j]));
233 
              assign towa[i][k][0][j] = towad[i][k][0][j] | towa4[i][k][0][j];
234 
              assign towa[i][k][1][j] = towad[i][k][1][j] | towa4[i][k][1][j];
235 
              assign towa[i][k][2][j] = towad[i][k][2][j] | towa4[i][k][2][j];
236 
              assign towa[i][k][3][j] = towad[i][k][3][j] | towa4[i][k][3][j];
237 
 `else
238 12 wsong0210 
              and ASA (towa[i][k][0][j], woa[i][k], wcfg[i][0][j]);
239 
              and ANA (towa[i][k][1][j], woa[i][k], wcfg[i][1][j]);
240 
              and AEA (towa[i][k][2][j], woa[i][k], wcfg[i][2][j]);
241 
              and ALA (towa[i][k][3][j], woa[i][k], wcfg[i][3][j]);
242 63 wsong0210 
 `endif
243 12 wsong0210 
`endif
244 
           end // block: SC
245 
`ifndef ENABLE_CHANNEL_SLICING
246 
           and AS4 (tow4[i][0][j], si4[j], wcfg[i][0][j]);
247 63 wsong0210 
           and AN4 (tow4[i][1][j], ni4[j], wcfg[i][1][j]);
248 
           and AE4 (tow4[i][2][j], ei4[j], wcfg[i][2][j]);
249 
           and AL4 (tow4[i][3][j], li4[j], wcfg[i][3][j]);
250 
 `ifdef ENABLE_BUFFERED_CLOS
251 
           and ASAd (towad[i][0][j], woa[i], wcfg[i][0][j]);
252 
           and ANAd (towad[i][1][j], woa[i], wcfg[i][1][j]);
253 
           and AEAd (towad[i][2][j], woa[i], wcfg[i][2][j]);
254 
           and ALAd (towad[i][3][j], woa[i], wcfg[i][3][j]);
255 
           c2 ASA4 (.q(towa4[i][0][j]), .a0(woa4[i]), .a1(wcfg[i][0][j]));
256 
           c2 ANA4 (.q(towa4[i][1][j]), .a0(woa4[i]), .a1(wcfg[i][1][j]));
257 
           c2 AEA4 (.q(towa4[i][2][j]), .a0(woa4[i]), .a1(wcfg[i][2][j]));
258 
           c2 ALA4 (.q(towa4[i][3][j]), .a0(woa4[i]), .a1(wcfg[i][3][j]));
259 
           assign towa[i][0][j] = towad[i][0][j] | towa4[i][0][j];
260 
           assign towa[i][1][j] = towad[i][1][j] | towa4[i][1][j];
261 
           assign towa[i][2][j] = towad[i][2][j] | towa4[i][2][j];
262 
           assign towa[i][3][j] = towad[i][3][j] | towa4[i][3][j];
263 
 `else
264 12 wsong0210 
           and ASA (towa[i][0][j], woa[i], wcfg[i][0][j]);
265 
           and ANA (towa[i][1][j], woa[i], wcfg[i][1][j]);
266 
           and AEA (towa[i][2][j], woa[i], wcfg[i][2][j]);
267 
           and ALA (towa[i][3][j], woa[i], wcfg[i][3][j]);
268 63 wsong0210 
 `endif
269 12 wsong0210 
`endif
270 
        end // block: V
271 
 
272 
        for(k=0; k<SCN; k++) begin: SCOR
273 
           assign wo0[i][k] = |(tow0[i][k][0]|tow0[i][k][1]|tow0[i][k][2]|tow0[i][k][3]);
274 
           assign wo1[i][k] = |(tow1[i][k][0]|tow1[i][k][1]|tow1[i][k][2]|tow1[i][k][3]);
275 
           assign wo2[i][k] = |(tow2[i][k][0]|tow2[i][k][1]|tow2[i][k][2]|tow2[i][k][3]);
276 
           assign wo3[i][k] = |(tow3[i][k][0]|tow3[i][k][1]|tow3[i][k][2]|tow3[i][k][3]);
277 
`ifdef ENABLE_CHANNEL_SLICING
278 
           assign wo4[i][k] = |(tow4[i][k][0]|tow4[i][k][1]|tow4[i][k][2]|tow4[i][k][3]);
279 
`endif
280 
        end
281 
`ifndef ENABLE_CHANNEL_SLICING
282 
        assign wo4[i] = |(tow4[i][0]|tow4[i][1]|tow4[i][2]|tow4[i][3]);
283 
`endif
284 
     end
285 
   endgenerate
286 
 
287 
   /*---------------------------- NORTH OUPUT -------------------------------------*/
288 
   generate for (i=0; i<VCN; i=i+1)
289 
     begin:NOP
290 
        for(j=0; j<VCN; j++) begin: V
291 
           for(k=0; k<SCN; k++) begin: SC
292 
              and AS0 (ton0[i][k][0][j], si0[j][k], ncfg[i][0][j]);
293 
              and AS1 (ton1[i][k][0][j], si1[j][k], ncfg[i][0][j]);
294 
              and AS2 (ton2[i][k][0][j], si2[j][k], ncfg[i][0][j]);
295 
              and AS3 (ton3[i][k][0][j], si3[j][k], ncfg[i][0][j]);
296 
              and AL0 (ton0[i][k][1][j], li0[j][k], ncfg[i][1][j]);
297 
              and AL1 (ton1[i][k][1][j], li1[j][k], ncfg[i][1][j]);
298 
              and AL2 (ton2[i][k][1][j], li2[j][k], ncfg[i][1][j]);
299 
              and AL3 (ton3[i][k][1][j], li3[j][k], ncfg[i][1][j]);
300 
`ifdef ENABLE_CHANNEL_SLICING
301 
              and AS4 (ton4[i][k][0][j], si4[j][k], ncfg[i][0][j]);
302 63 wsong0210 
              and AL4 (ton4[i][k][1][j], li4[j][k], ncfg[i][1][j]);
303 
 `ifdef ENABLE_BUFFERED_CLOS
304 
              and ASAd (tonad[i][k][0][j], noa[i][k], ncfg[i][0][j]);
305 
              and ALAd (tonad[i][k][1][j], noa[i][k], ncfg[i][1][j]);
306 
              c2 ASA4 (.q(tona4[i][k][0][j]), .a0(noa4[i][k]), .a1(ncfg[i][0][j]));
307 
              c2 ALA4 (.q(tona4[i][k][1][j]), .a0(noa4[i][k]), .a1(ncfg[i][1][j]));
308 
              assign tona[i][k][0][j] = tonad[i][k][0][j] | tona4[i][k][0][j];
309 
              assign tona[i][k][1][j] = tonad[i][k][1][j] | tona4[i][k][1][j];
310 
 `else
311 12 wsong0210 
              and ASA (tona[i][k][0][j], noa[i][k], ncfg[i][0][j]);
312 
              and ALA (tona[i][k][1][j], noa[i][k], ncfg[i][1][j]);
313 63 wsong0210 
 `endif
314 12 wsong0210 
`endif
315 
           end // block: SC
316 
`ifndef ENABLE_CHANNEL_SLICING
317 
           and AS4 (ton4[i][0][j], si4[j], ncfg[i][0][j]);
318 63 wsong0210 
           and AL4 (ton4[i][1][j], li4[j], ncfg[i][1][j]);
319 
 `ifdef ENABLE_BUFFERED_CLOS
320 
           and ASAd (tonad[i][0][j], noa[i], ncfg[i][0][j]);
321 
           and ALAd (tonad[i][1][j], noa[i], ncfg[i][1][j]);
322 
           c2 ASA4 (.q(tona4[i][0][j]), .a0(noa4[i]), .a1(ncfg[i][0][j]));
323 
           c2 ALA4 (.q(tona4[i][1][j]), .a0(noa4[i]), .a1(ncfg[i][1][j]));
324 
           assign tona[i][0][j] = tonad[i][0][j] | tona4[i][0][j];
325 
           assign tona[i][1][j] = tonad[i][1][j] | tona4[i][1][j];
326 
 `else
327 12 wsong0210 
           and ASA (tona[i][0][j], noa[i], ncfg[i][0][j]);
328 
           and ALA (tona[i][1][j], noa[i], ncfg[i][1][j]);
329 63 wsong0210 
 `endif
330 12 wsong0210 
`endif
331 
        end // block: V
332 
 
333 
        for(k=0; k<SCN; k++) begin: SCOR
334 
           assign no0[i][k] = |(ton0[i][k][0]|ton0[i][k][1]);
335 
           assign no1[i][k] = |(ton1[i][k][0]|ton1[i][k][1]);
336 
           assign no2[i][k] = |(ton2[i][k][0]|ton2[i][k][1]);
337 
           assign no3[i][k] = |(ton3[i][k][0]|ton3[i][k][1]);
338 
`ifdef ENABLE_CHANNEL_SLICING
339 
           assign no4[i][k] = |(ton4[i][k][0]|ton4[i][k][1]);
340 
`endif
341 
        end
342 
`ifndef ENABLE_CHANNEL_SLICING
343 
        assign no4[i] = |(ton4[i][0]|ton4[i][1]);
344 
`endif
345 
     end
346 
   endgenerate
347 
 
348 
   /*---------------------------- EAST OUPUT -------------------------------------*/
349 
   generate for (i=0; i<VCN; i=i+1)
350 
     begin:EOP
351 
        for(j=0; j<VCN; j++) begin: V
352 
           for(k=0; k<SCN; k++) begin: SC
353 
              and AS0 (toe0[i][k][0][j], si0[j][k], ecfg[i][0][j]);
354 
              and AS1 (toe1[i][k][0][j], si1[j][k], ecfg[i][0][j]);
355 
              and AS2 (toe2[i][k][0][j], si2[j][k], ecfg[i][0][j]);
356 
              and AS3 (toe3[i][k][0][j], si3[j][k], ecfg[i][0][j]);
357 
              and AW0 (toe0[i][k][1][j], wi0[j][k], ecfg[i][1][j]);
358 
              and AW1 (toe1[i][k][1][j], wi1[j][k], ecfg[i][1][j]);
359 
              and AW2 (toe2[i][k][1][j], wi2[j][k], ecfg[i][1][j]);
360 
              and AW3 (toe3[i][k][1][j], wi3[j][k], ecfg[i][1][j]);
361 
              and AN0 (toe0[i][k][2][j], ni0[j][k], ecfg[i][2][j]);
362 
              and AN1 (toe1[i][k][2][j], ni1[j][k], ecfg[i][2][j]);
363 
              and AN2 (toe2[i][k][2][j], ni2[j][k], ecfg[i][2][j]);
364 
              and AN3 (toe3[i][k][2][j], ni3[j][k], ecfg[i][2][j]);
365 
              and AL0 (toe0[i][k][3][j], li0[j][k], ecfg[i][3][j]);
366 
              and AL1 (toe1[i][k][3][j], li1[j][k], ecfg[i][3][j]);
367 
              and AL2 (toe2[i][k][3][j], li2[j][k], ecfg[i][3][j]);
368 
              and AL3 (toe3[i][k][3][j], li3[j][k], ecfg[i][3][j]);
369 
`ifdef ENABLE_CHANNEL_SLICING
370 
              and AS4 (toe4[i][k][0][j], si4[j][k], ecfg[i][0][j]);
371 63 wsong0210 
              and AW4 (toe4[i][k][1][j], wi4[j][k], ecfg[i][1][j]);
372 
              and AN4 (toe4[i][k][2][j], ni4[j][k], ecfg[i][2][j]);
373 
              and AL4 (toe4[i][k][3][j], li4[j][k], ecfg[i][3][j]);
374 
 `ifdef ENABLE_BUFFERED_CLOS
375 
              and ASAd (toead[i][k][0][j], eoa[i][k], ecfg[i][0][j]);
376 
              and AWAd (toead[i][k][1][j], eoa[i][k], ecfg[i][1][j]);
377 
              and ANAd (toead[i][k][2][j], eoa[i][k], ecfg[i][2][j]);
378 
              and ALAd (toead[i][k][3][j], eoa[i][k], ecfg[i][3][j]);
379 
              c2 ASA4 (.q(toea4[i][k][0][j]), .a0(eoa4[i][k]), .a1(ecfg[i][0][j]));
380 
              c2 AWA4 (.q(toea4[i][k][1][j]), .a0(eoa4[i][k]), .a1(ecfg[i][1][j]));
381 
              c2 ANA4 (.q(toea4[i][k][2][j]), .a0(eoa4[i][k]), .a1(ecfg[i][2][j]));
382 
              c2 ALA4 (.q(toea4[i][k][3][j]), .a0(eoa4[i][k]), .a1(ecfg[i][3][j]));
383 
              assign toea[i][k][0][j] = toead[i][k][0][j] | toea4[i][k][0][j];
384 
              assign toea[i][k][1][j] = toead[i][k][1][j] | toea4[i][k][1][j];
385 
              assign toea[i][k][2][j] = toead[i][k][2][j] | toea4[i][k][2][j];
386 
              assign toea[i][k][3][j] = toead[i][k][3][j] | toea4[i][k][3][j];
387 
 `else
388 12 wsong0210 
              and ASA (toea[i][k][0][j], eoa[i][k], ecfg[i][0][j]);
389 
              and AWA (toea[i][k][1][j], eoa[i][k], ecfg[i][1][j]);
390 
              and ANA (toea[i][k][2][j], eoa[i][k], ecfg[i][2][j]);
391 
              and ALA (toea[i][k][3][j], eoa[i][k], ecfg[i][3][j]);
392 63 wsong0210 
 `endif
393 12 wsong0210 
`endif
394 
           end // block: SC
395 
`ifndef ENABLE_CHANNEL_SLICING
396 
           and AS4 (toe4[i][0][j], si4[j], ecfg[i][0][j]);
397 63 wsong0210 
           and AW4 (toe4[i][1][j], wi4[j], ecfg[i][1][j]);
398 
           and AN4 (toe4[i][2][j], ni4[j], ecfg[i][2][j]);
399 
           and AL4 (toe4[i][3][j], li4[j], ecfg[i][3][j]);
400 
 `ifdef ENABLE_BUFFERED_CLOS
401 
           and ASAd (toead[i][0][j], eoa[i], ecfg[i][0][j]);
402 
           and AWAd (toead[i][1][j], eoa[i], ecfg[i][1][j]);
403 
           and ANAd (toead[i][2][j], eoa[i], ecfg[i][2][j]);
404 
           and ALAd (toead[i][3][j], eoa[i], ecfg[i][3][j]);
405 
           c2 ASA4 (.q(toea4[i][0][j]), .a0(eoa4[i]), .a1(ecfg[i][0][j]));
406 
           c2 AWA4 (.q(toea4[i][1][j]), .a0(eoa4[i]), .a1(ecfg[i][1][j]));
407 
           c2 ANA4 (.q(toea4[i][2][j]), .a0(eoa4[i]), .a1(ecfg[i][2][j]));
408 
           c2 ALA4 (.q(toea4[i][3][j]), .a0(eoa4[i]), .a1(ecfg[i][3][j]));
409 
           assign toea[i][0][j] = toead[i][0][j] | toea4[i][0][j];
410 
           assign toea[i][1][j] = toead[i][1][j] | toea4[i][1][j];
411 
           assign toea[i][2][j] = toead[i][2][j] | toea4[i][2][j];
412 
           assign toea[i][3][j] = toead[i][3][j] | toea4[i][3][j];
413 
 `else
414 12 wsong0210 
           and ASA (toea[i][0][j], eoa[i], ecfg[i][0][j]);
415 
           and AWA (toea[i][1][j], eoa[i], ecfg[i][1][j]);
416 
           and ANA (toea[i][2][j], eoa[i], ecfg[i][2][j]);
417 
           and ALA (toea[i][3][j], eoa[i], ecfg[i][3][j]);
418 63 wsong0210 
 `endif
419 12 wsong0210 
`endif
420 
        end // block: V
421 
 
422 
        for(k=0; k<SCN; k++) begin: SCOR
423 
           assign eo0[i][k] = |(toe0[i][k][0]|toe0[i][k][1]|toe0[i][k][2]|toe0[i][k][3]);
424 
           assign eo1[i][k] = |(toe1[i][k][0]|toe1[i][k][1]|toe1[i][k][2]|toe1[i][k][3]);
425 
           assign eo2[i][k] = |(toe2[i][k][0]|toe2[i][k][1]|toe2[i][k][2]|toe2[i][k][3]);
426 
           assign eo3[i][k] = |(toe3[i][k][0]|toe3[i][k][1]|toe3[i][k][2]|toe3[i][k][3]);
427 
`ifdef ENABLE_CHANNEL_SLICING
428 
           assign eo4[i][k] = |(toe4[i][k][0]|toe4[i][k][1]|toe4[i][k][2]|toe4[i][k][3]);
429 
`endif
430 
        end
431 
`ifndef ENABLE_CHANNEL_SLICING
432 
        assign eo4[i] = |(toe4[i][0]|toe4[i][1]|toe4[i][2]|toe4[i][3]);
433 
`endif
434 
     end
435 
   endgenerate
436 
 
437 
 
438 
   /*---------------------------- LOCAL OUPUT -------------------------------------*/
439 
   generate for (i=0; i<VCN; i=i+1)
440 
     begin:LOP
441 
        for(j=0; j<VCN; j++) begin: V
442 
           for(k=0; k<SCN; k++) begin: SC
443 
              and AS0 (tol0[i][k][0][j], si0[j][k], lcfg[i][0][j]);
444 
              and AS1 (tol1[i][k][0][j], si1[j][k], lcfg[i][0][j]);
445 
              and AS2 (tol2[i][k][0][j], si2[j][k], lcfg[i][0][j]);
446 
              and AS3 (tol3[i][k][0][j], si3[j][k], lcfg[i][0][j]);
447 
              and AW0 (tol0[i][k][1][j], wi0[j][k], lcfg[i][1][j]);
448 
              and AW1 (tol1[i][k][1][j], wi1[j][k], lcfg[i][1][j]);
449 
              and AW2 (tol2[i][k][1][j], wi2[j][k], lcfg[i][1][j]);
450 
              and AW3 (tol3[i][k][1][j], wi3[j][k], lcfg[i][1][j]);
451 
              and AN0 (tol0[i][k][2][j], ni0[j][k], lcfg[i][2][j]);
452 
              and AN1 (tol1[i][k][2][j], ni1[j][k], lcfg[i][2][j]);
453 
              and AN2 (tol2[i][k][2][j], ni2[j][k], lcfg[i][2][j]);
454 
              and AN3 (tol3[i][k][2][j], ni3[j][k], lcfg[i][2][j]);
455 
              and AE0 (tol0[i][k][3][j], ei0[j][k], lcfg[i][3][j]);
456 
              and AE1 (tol1[i][k][3][j], ei1[j][k], lcfg[i][3][j]);
457 
              and AE2 (tol2[i][k][3][j], ei2[j][k], lcfg[i][3][j]);
458 
              and AE3 (tol3[i][k][3][j], ei3[j][k], lcfg[i][3][j]);
459 
`ifdef ENABLE_CHANNEL_SLICING
460 
              and AS4 (tol4[i][k][0][j], si4[j][k], lcfg[i][0][j]);
461 63 wsong0210 
              and AW4 (tol4[i][k][1][j], wi4[j][k], lcfg[i][1][j]);
462 
              and AN4 (tol4[i][k][2][j], ni4[j][k], lcfg[i][2][j]);
463 
              and AE4 (tol4[i][k][3][j], ei4[j][k], lcfg[i][3][j]);
464 
 `ifdef ENABLE_BUFFERED_CLOS
465 
              and ASAd (tolad[i][k][0][j], loa[i][k], lcfg[i][0][j]);
466 
              and AWAd (tolad[i][k][1][j], loa[i][k], lcfg[i][1][j]);
467 
              and ANAd (tolad[i][k][2][j], loa[i][k], lcfg[i][2][j]);
468 
              and AEAd (tolad[i][k][3][j], loa[i][k], lcfg[i][3][j]);
469 
              c2 ASA4 (.q(tola4[i][k][0][j]), .a0(loa4[i][k]), .a1(lcfg[i][0][j]));
470 
              c2 AWA4 (.q(tola4[i][k][1][j]), .a0(loa4[i][k]), .a1(lcfg[i][1][j]));
471 
              c2 ANA4 (.q(tola4[i][k][2][j]), .a0(loa4[i][k]), .a1(lcfg[i][2][j]));
472 
              c2 AEA4 (.q(tola4[i][k][3][j]), .a0(loa4[i][k]), .a1(lcfg[i][3][j]));
473 
              assign tola[i][k][0][j] = tolad[i][k][0][j] | tola4[i][k][0][j];
474 
              assign tola[i][k][1][j] = tolad[i][k][1][j] | tola4[i][k][1][j];
475 
              assign tola[i][k][2][j] = tolad[i][k][2][j] | tola4[i][k][2][j];
476 
              assign tola[i][k][3][j] = tolad[i][k][3][j] | tola4[i][k][3][j];
477 
 `else
478 12 wsong0210 
              and ASA (tola[i][k][0][j], loa[i][k], lcfg[i][0][j]);
479 
              and AWA (tola[i][k][1][j], loa[i][k], lcfg[i][1][j]);
480 
              and ANA (tola[i][k][2][j], loa[i][k], lcfg[i][2][j]);
481 
              and AEA (tola[i][k][3][j], loa[i][k], lcfg[i][3][j]);
482 63 wsong0210 
 `endif
483 12 wsong0210 
`endif
484 
           end // block: SC
485 
`ifndef ENABLE_CHANNEL_SLICING
486 
           and AS4 (tol4[i][0][j], si4[j], lcfg[i][0][j]);
487 63 wsong0210 
           and AW4 (tol4[i][1][j], wi4[j], lcfg[i][1][j]);
488 
           and AN4 (tol4[i][2][j], ni4[j], lcfg[i][2][j]);
489 
           and AE4 (tol4[i][3][j], ei4[j], lcfg[i][3][j]);
490 
 `ifdef ENABLE_BUFFERED_CLOS
491 
           and ASAd (tolad[i][0][j], loa[i], lcfg[i][0][j]);
492 
           and AWAd (tolad[i][1][j], loa[i], lcfg[i][1][j]);
493 
           and ANAd (tolad[i][2][j], loa[i], lcfg[i][2][j]);
494 
           and AEAd (tolad[i][3][j], loa[i], lcfg[i][3][j]);
495 
           c2 ASA4 (.q(tola4[i][0][j]), .a0(loa4[i]), .a1(lcfg[i][0][j]));
496 
           c2 AWA4 (.q(tola4[i][1][j]), .a0(loa4[i]), .a1(lcfg[i][1][j]));
497 
           c2 ANA4 (.q(tola4[i][2][j]), .a0(loa4[i]), .a1(lcfg[i][2][j]));
498 
           c2 AEA4 (.q(tola4[i][3][j]), .a0(loa4[i]), .a1(lcfg[i][3][j]));
499 
           assign tola[i][0][j] = tolad[i][0][j] | tola4[i][0][j];
500 
           assign tola[i][1][j] = tolad[i][1][j] | tola4[i][1][j];
501 
           assign tola[i][2][j] = tolad[i][2][j] | tola4[i][2][j];
502 
           assign tola[i][3][j] = tolad[i][3][j] | tola4[i][3][j];
503 
 `else
504 12 wsong0210 
           and ASA (tola[i][0][j], loa[i], lcfg[i][0][j]);
505 
           and AWA (tola[i][1][j], loa[i], lcfg[i][1][j]);
506 
           and ANA (tola[i][2][j], loa[i], lcfg[i][2][j]);
507 
           and AEA (tola[i][3][j], loa[i], lcfg[i][3][j]);
508 63 wsong0210 
 `endif
509 12 wsong0210 
`endif
510 
        end // block: V
511 
 
512 
        for(k=0; k<SCN; k++) begin: SCOR
513 
           assign lo0[i][k] = |(tol0[i][k][0]|tol0[i][k][1]|tol0[i][k][2]|tol0[i][k][3]);
514 
           assign lo1[i][k] = |(tol1[i][k][0]|tol1[i][k][1]|tol1[i][k][2]|tol1[i][k][3]);
515 
           assign lo2[i][k] = |(tol2[i][k][0]|tol2[i][k][1]|tol2[i][k][2]|tol2[i][k][3]);
516 
           assign lo3[i][k] = |(tol3[i][k][0]|tol3[i][k][1]|tol3[i][k][2]|tol3[i][k][3]);
517 
`ifdef ENABLE_CHANNEL_SLICING
518 
           assign lo4[i][k] = |(tol4[i][k][0]|tol4[i][k][1]|tol4[i][k][2]|tol4[i][k][3]);
519 
`endif
520 
        end
521 
`ifndef ENABLE_CHANNEL_SLICING
522 
        assign lo4[i] = |(tol4[i][0]|tol4[i][1]|tol4[i][2]|tol4[i][3]);
523 
`endif
524 
     end
525 
   endgenerate
526 
 
527 
   generate for(i=0; i<VCN; i++) begin: IACK
528 
`ifdef ENABLE_CHANNEL_SLICING
529 
      for(k=0; k<SCN; k++) begin: SC
530 
         for(j=0; j<VCN; j++) begin: SHUFFLE
531 
            assign isa[i][k][0][j] = towa[j][k][0][i];
532 
            assign isa[i][k][1][j] = tona[j][k][0][i];
533 
            assign isa[i][k][2][j] = toea[j][k][0][i];
534 
            assign isa[i][k][3][j] = tola[j][k][0][i];
535 
            assign iwa[i][k][0][j] = toea[j][k][1][i];
536 
            assign iwa[i][k][1][j] = tola[j][k][1][i];
537 
            assign ina[i][k][0][j] = tosa[j][k][0][i];
538 
            assign ina[i][k][1][j] = towa[j][k][1][i];
539 
            assign ina[i][k][2][j] = toea[j][k][2][i];
540 
            assign ina[i][k][3][j] = tola[j][k][2][i];
541 
            assign iea[i][k][0][j] = towa[j][k][2][i];
542 
            assign iea[i][k][1][j] = tola[j][k][3][i];
543 
            assign ila[i][k][0][j] = tosa[j][k][1][i];
544 
            assign ila[i][k][1][j] = towa[j][k][3][i];
545 
            assign ila[i][k][2][j] = tona[j][k][1][i];
546 
            assign ila[i][k][3][j] = toea[j][k][3][i];
547 
         end // block: SHUFFLE
548 
         assign sia[i][k] = |{isa[i][k][0]|isa[i][k][1]|isa[i][k][2]|isa[i][k][3]};
549 
         assign wia[i][k] = |{iwa[i][k][0]|iwa[i][k][1]};
550 
         assign nia[i][k] = |{ina[i][k][0]|ina[i][k][1]|ina[i][k][2]|ina[i][k][3]};
551 
         assign eia[i][k] = |{iea[i][k][0]|iea[i][k][1]};
552 
         assign lia[i][k] = |{ila[i][k][0]|ila[i][k][1]|ila[i][k][2]|ila[i][k][3]};
553 
      end // block: SC
554 
`else // !`ifdef ENABLE_CHANNEL_SLICING
555 
      for(j=0; j<VCN; j++) begin: SHUFFLE
556 
         assign isa[i][0][j] = towa[j][0][i];
557 
         assign isa[i][1][j] = tona[j][0][i];
558 
         assign isa[i][2][j] = toea[j][0][i];
559 
         assign isa[i][3][j] = tola[j][0][i];
560 
         assign iwa[i][0][j] = toea[j][1][i];
561 
         assign iwa[i][1][j] = tola[j][1][i];
562 
         assign ina[i][0][j] = tosa[j][0][i];
563 
         assign ina[i][1][j] = towa[j][1][i];
564 
         assign ina[i][2][j] = toea[j][2][i];
565 
         assign ina[i][3][j] = tola[j][2][i];
566 
         assign iea[i][0][j] = towa[j][2][i];
567 
         assign iea[i][1][j] = tola[j][3][i];
568 
         assign ila[i][0][j] = tosa[j][1][i];
569 
         assign ila[i][1][j] = towa[j][3][i];
570 
         assign ila[i][2][j] = tona[j][1][i];
571 
         assign ila[i][3][j] = toea[j][3][i];
572 
      end // block: SHUFFLE
573 
      assign sia[i] = |{isa[i][0]|isa[i][1]|isa[i][2]|isa[i][3]};
574 
      assign wia[i] = |{iwa[i][0]|iwa[i][1]};
575 
      assign nia[i] = |{ina[i][0]|ina[i][1]|ina[i][2]|ina[i][3]};
576 
      assign eia[i] = |{iea[i][0]|iea[i][1]};
577 
      assign lia[i] = |{ila[i][0]|ila[i][1]|ila[i][2]|ila[i][3]};
578 
`endif
579 
   end // block: IACK
580 
   endgenerate
581 
 
582 
endmodule // dcb_xy
583 
 
584 
 
585 
 

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