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/*
 Asynchronous SDM NoC
 (C)2011 Wei Song
 Advanced Processor Technologies Group
 Computer Science, the Univ. of Manchester, UK
 
 Authors:
 Wei Song     wsong83@gmail.com
 
 License: LGPL 3.0 or later
 
 Data Clos network.
 *** SystemVerilog is used ***
 
 History:
 17/07/2010  Initial version. <wsong83@gmail.com>
 20/09/2010  Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
 23/05/2011  Clean up for opensource. <wsong83@gmail.com>
 21/06/2011  Prepare to support buffered Clos. <wsong83@gmail.com>
 
*/
 
// the router structure definitions
`include "define.v"
 
module dclos (
   // Outputs
   so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
   eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
   wia, nia, eia, lia,
   // Inputs
   si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
   ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
   woa, noa, eoa, loa, imcfg, scfg, ncfg, wcfg, ecfg, lcfg
`ifdef ENABLE_BUFFERED_CLOS
   , soa4, woa4, noa4, eoa4, loa4
`endif
   );
 
   parameter MN = 2;            // number of CMs
   parameter NN = 2;            // number of ports in an IM or OM, equ. to number of virtual circuits
   parameter DW = 8;            // datawidth of a single virtual circuit/port
   parameter SCN = DW/2;        // number of 1-of-4 sub-channels in one port
 
   input [NN-1:0][SCN-1:0]     si0, si1, si2, si3; // south input [0], X+1
   input [NN-1:0][SCN-1:0]     wi0, wi1, wi2, wi3; // west input [1], Y-1
   input [NN-1:0][SCN-1:0]     ni0, ni1, ni2, ni3; // north input [2], X-1
   input [NN-1:0][SCN-1:0]     ei0, ei1, ei2, ei3; // east input [3], Y+1
   input [NN-1:0][SCN-1:0]     li0, li1, li2, li3; // local input
   output [NN-1:0][SCN-1:0]    so0, so1, so2, so3; // south output
   output [NN-1:0][SCN-1:0]    wo0, wo1, wo2, wo3; // west output
   output [NN-1:0][SCN-1:0]    no0, no1, no2, no3; // north output
   output [NN-1:0][SCN-1:0]    eo0, eo1, eo2, eo3; // east output
   output [NN-1:0][SCN-1:0]    lo0, lo1, lo2, lo3; // local output
 
   // eof bits and ack lines
`ifdef ENABLE_CHANNEL_SLICING
   input [NN-1:0][SCN-1:0]     si4, wi4, ni4, ei4, li4;
   output [NN-1:0][SCN-1:0]    so4, wo4, no4, eo4, lo4;
   output [NN-1:0][SCN-1:0]    sia, wia, nia, eia, lia;
   input [NN-1:0][SCN-1:0]     soa, woa, noa, eoa, loa;
 `ifdef ENABLE_BUFFERED_CLOS
   input [NN-1:0][SCN-1:0]     soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
 `endif
`else
   input [NN-1:0]               si4, wi4, ni4, ei4, li4;
   output [NN-1:0]              so4, wo4, no4, eo4, lo4;
   output [NN-1:0]              sia, wia, nia, eia, lia;
   input [NN-1:0]               soa, woa, noa, eoa, loa;
 `ifdef ENABLE_BUFFERED_CLOS
   input [NN-1:0]               soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
 `endif
`endif // !`ifdef ENABLE_CHANNEL_SLICING
 
   input [4:0][MN-1:0][NN-1:0] imcfg; // configuration for IMs
   // configuration for CMs
   input [MN-1:0][1:0]           scfg, ncfg;
   input [MN-1:0][3:0]           wcfg, ecfg, lcfg;
   // no OMs
 
   // output of IMs
   wire [MN-1:0][SCN-1:0]      imos0, imos1, imos2, imos3;
   wire [MN-1:0][SCN-1:0]      imow0, imow1, imow2, imow3;
   wire [MN-1:0][SCN-1:0]      imon0, imon1, imon2, imon3;
   wire [MN-1:0][SCN-1:0]      imoe0, imoe1, imoe2, imoe3;
   wire [MN-1:0][SCN-1:0]      imol0, imol1, imol2, imol3;
`ifdef ENABLE_CHANNEL_SLICING
   wire [MN-1:0][SCN-1:0]      imos4, imow4, imon4, imoe4, imol4;
   wire [MN-1:0][SCN-1:0]      imosa, imowa, imona, imoea, imola;
 `ifdef ENABLE_BUFFERED_CLOS
   wire [MN-1:0][SCN-1:0]      imosa4, imowa4, imona4, imoea4, imola4;
 `endif
`else
   wire [MN-1:0]                imos4, imow4, imon4, imoe4, imol4;
   wire [MN-1:0]                imosa, imowa, imona, imoea, imola;
 `ifdef ENABLE_BUFFERED_CLOS
   wire [MN-1:0]                imosa4, imowa4, imona4, imoea4, imola4;
 `endif
`endif
 
   // input of CMs
   wire [MN-1:0][4:0][SCN-1:0] cmi0, cmi1, cmi2, cmi3;
`ifdef ENABLE_CHANNEL_SLICING
   wire [MN-1:0][4:0][SCN-1:0] cmi4, cmia;
`else
   wire [MN-1:0][4:0]            cmi4, cmia;
`endif
 
   // output of CMs
   wire [MN-1:0][4:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3;
`ifdef ENABLE_CHANNEL_SLICING
   wire [MN-1:0][4:0][SCN-1:0] cmo4, cmoa;
 `ifdef ENABLE_BUFFERED_CLOS
   wire [MN-1:0][4:0][SCN-1:0] cmoa4;
 `endif
`else
   wire [MN-1:0][4:0]            cmo4, cmoa;
 `ifdef ENABLE_BUFFERED_CLOS
   wire [MN-1:0][4:0]            cmoa4;
 `endif
`endif
 
   genvar                      i,j,k;
 
   dcb #(.NN(NN), .MN(MN), .DW(DW))
   SIM (
        .o0  ( imos0    ),
        .o1  ( imos1    ),
        .o2  ( imos2    ),
        .o3  ( imos3    ),
        .o4  ( imos4    ),
        .ia  ( sia      ),
        .i0  ( si0      ),
        .i1  ( si1      ),
        .i2  ( si2      ),
        .i3  ( si3      ),
        .i4  ( si4      ),
        .oa  ( imosa    ),
`ifdef ENABLE_BUFFERED_CLOS
        .oa4 ( imosa4   ),
`endif
        .cfg ( imcfg[0] )
        );
 
   dcb #(.NN(NN), .MN(MN), .DW(DW))
   WIM (
        .o0  ( imow0    ),
        .o1  ( imow1    ),
        .o2  ( imow2    ),
        .o3  ( imow3    ),
        .o4  ( imow4    ),
        .ia  ( wia      ),
        .i0  ( wi0      ),
        .i1  ( wi1      ),
        .i2  ( wi2      ),
        .i3  ( wi3      ),
        .i4  ( wi4      ),
        .oa  ( imowa    ),
`ifdef ENABLE_BUFFERED_CLOS
        .oa4 ( imowa4   ),
`endif
        .cfg ( imcfg[1] )
        );
 
   dcb #(.NN(NN), .MN(MN), .DW(DW))
   NIM (
        .o0  ( imon0    ),
        .o1  ( imon1    ),
        .o2  ( imon2    ),
        .o3  ( imon3    ),
        .o4  ( imon4    ),
        .ia  ( nia      ),
        .i0  ( ni0      ),
        .i1  ( ni1      ),
        .i2  ( ni2      ),
        .i3  ( ni3      ),
        .i4  ( ni4      ),
        .oa  ( imona    ),
`ifdef ENABLE_BUFFERED_CLOS
        .oa4 ( imona4   ),
`endif
        .cfg ( imcfg[2] )
       );
 
   dcb #(.NN(NN), .MN(MN), .DW(DW))
   EIM (
        .o0  ( imoe0    ),
        .o1  ( imoe1    ),
        .o2  ( imoe2    ),
        .o3  ( imoe3    ),
        .o4  ( imoe4    ),
        .ia  ( eia      ),
        .i0  ( ei0      ),
        .i1  ( ei1      ),
        .i2  ( ei2      ),
        .i3  ( ei3      ),
        .i4  ( ei4      ),
        .oa  ( imoea    ),
`ifdef ENABLE_BUFFERED_CLOS
        .oa4 ( imoea4   ),
`endif
        .cfg ( imcfg[3] )
        );
 
   dcb #(.NN(NN), .MN(MN), .DW(DW))
   LIM (
        .o0  ( imol0    ),
        .o1  ( imol1    ),
        .o2  ( imol2    ),
        .o3  ( imol3    ),
        .o4  ( imol4    ),
        .ia  ( lia      ),
        .i0  ( li0      ),
        .i1  ( li1      ),
        .i2  ( li2      ),
        .i3  ( li3      ),
        .i4  ( li4      ),
        .oa  ( imola    ),
`ifdef ENABLE_BUFFERED_CLOS
        .oa4 ( imola4   ),
`endif
        .cfg ( imcfg[4] )
        );
 
   generate for(i=0; i<MN; i++) begin: IMSHF
`ifdef ENABLE_BUFFERED_CLOS
      // the buffer stage between IM and CM
 `ifdef ENABLE_CHANNEL_SLICING
      for(j=0; j<SCN; j++) begin:SC
         pipe4 #(.DW(2))
         P (
            .o0 ( cmi0[i][0]  ),
            .o1 ( cmi1[i][0]  ),
            .o2 ( cmi2[i][0]  ),
            .o3 ( cmi3[i][0]  ),
            .ia ( imosa[i]    ),
            .i0 ( imos0[i]    ),
            .i1 ( imos1[i]    ),
            .i2 ( imos3[i]    ),
            .i3 ( imos4[i]    ),
            .oa ( cmian[i][0]  )
            );
 
         pipen #(.DW(1))
         PEoF (
               .d_in_a  ( imosa4[i]   ),
               .d_out   ( cmi4[i][0]  ),
               .d_in    ( imos4[i]    ),
               .d_out_a ( cmian[i][0] ),
               );
 
 
 
`else
      // shuffle the interconnects between IMs and CMs
      assign cmi0[i][0] = imos0[i];
      assign cmi1[i][0] = imos1[i];
      assign cmi2[i][0] = imos2[i];
      assign cmi3[i][0] = imos3[i];
      assign cmi4[i][0] = imos4[i];
      assign imosa[i] = cmia[i][0];
 
      assign cmi0[i][1] = imow0[i];
      assign cmi1[i][1] = imow1[i];
      assign cmi2[i][1] = imow2[i];
      assign cmi3[i][1] = imow3[i];
      assign cmi4[i][1] = imow4[i];
      assign imowa[i] = cmia[i][1];
 
      assign cmi0[i][2] = imon0[i];
      assign cmi1[i][2] = imon1[i];
      assign cmi2[i][2] = imon2[i];
      assign cmi3[i][2] = imon3[i];
      assign cmi4[i][2] = imon4[i];
      assign imona[i] = cmia[i][2];
 
      assign cmi0[i][3] = imoe0[i];
      assign cmi1[i][3] = imoe1[i];
      assign cmi2[i][3] = imoe2[i];
      assign cmi3[i][3] = imoe3[i];
      assign cmi4[i][3] = imoe4[i];
      assign imoea[i] = cmia[i][3];
 
      assign cmi0[i][4] = imol0[i];
      assign cmi1[i][4] = imol1[i];
      assign cmi2[i][4] = imol2[i];
      assign cmi3[i][4] = imol3[i];
      assign cmi4[i][4] = imol4[i];
      assign imola[i] = cmia[i][4];
`endif // !`ifdef ENABLE_BUFFERED_CLOS
 
      // CM modules
      dcb_xy #(.VCN(1), .VCW(DW))
      CM (
          .sia   ( cmia[i][0]   ),
          .wia   ( cmia[i][1]   ),
          .nia   ( cmia[i][2]   ),
          .eia   ( cmia[i][3]   ),
          .lia   ( cmia[i][4]   ),
          .so0   ( cmo0[i][0]   ),
          .so1   ( cmo1[i][0]   ),
          .so2   ( cmo2[i][0]   ),
          .so3   ( cmo3[i][0]   ),
          .so4   ( cmo4[i][0]   ),
          .wo0   ( cmo0[i][1]   ),
          .wo1   ( cmo1[i][1]   ),
          .wo2   ( cmo2[i][1]   ),
          .wo3   ( cmo3[i][1]   ),
          .wo4   ( cmo4[i][1]   ) ,
          .no0   ( cmo0[i][2]   ),
          .no1   ( cmo1[i][2]   ),
          .no2   ( cmo2[i][2]   ),
          .no3   ( cmo3[i][2]   ),
          .no4   ( cmo4[i][2]   ),
          .eo0   ( cmo0[i][3]   ),
          .eo1   ( cmo1[i][3]   ),
          .eo2   ( cmo2[i][3]   ),
          .eo3   ( cmo3[i][3]   ),
          .eo4   ( cmo4[i][3]   ),
          .lo0   ( cmo0[i][4]   ),
          .lo1   ( cmo1[i][4]   ),
          .lo2   ( cmo2[i][4]   ),
          .lo3   ( cmo3[i][4]   ),
          .lo4   ( cmo4[i][4]   ),
          .si0   ( cmi0[i][0]   ),
          .si1   ( cmi1[i][0]   ),
          .si2   ( cmi2[i][0]   ),
          .si3   ( cmi3[i][0]   ),
          .si4   ( cmi4[i][0]   ),
          .wi0   ( cmi0[i][1]   ),
          .wi1   ( cmi1[i][1]   ),
          .wi2   ( cmi2[i][1]   ),
          .wi3   ( cmi3[i][1]   ),
          .wi4   ( cmi4[i][1]   ),
          .ni0   ( cmi0[i][2]   ),
          .ni1   ( cmi1[i][2]   ),
          .ni2   ( cmi2[i][2]   ),
          .ni3   ( cmi3[i][2]   ),
          .ni4   ( cmi4[i][2]   ),
          .ei0   ( cmi0[i][3]   ),
          .ei1   ( cmi1[i][3]   ),
          .ei2   ( cmi2[i][3]   ),
          .ei3   ( cmi3[i][3]   ),
          .ei4   ( cmi4[i][3]   ),
          .li0   ( cmi0[i][4]   ),
          .li1   ( cmi1[i][4]   ),
          .li2   ( cmi2[i][4]   ),
          .li3   ( cmi3[i][4]   ),
          .li4   ( cmi4[i][4]   ),
          .soa   ( cmoa[i][0]   ),
          .woa   ( cmoa[i][1]   ),
          .noa   ( cmoa[i][2]   ),
          .eoa   ( cmoa[i][3]   ),
          .loa   ( cmoa[i][4]   ),
`ifdef ENABLE_BUFFERED_CLOS
          .soa4  ( cmoa4[i][0]  ),
          .woa4  ( cmoa4[i][1]  ),
          .noa4  ( cmoa4[i][2]  ),
          .eoa4  ( cmoa4[i][3]  ),
          .loa4  ( cmoa4[i][4]  ),
`endif
          .wcfg  ( wcfg[i]      ),
          .ecfg  ( ecfg[i]      ),
          .lcfg  ( lcfg[i]      ),
          .scfg  ( scfg[i]      ),
          .ncfg  ( ncfg[i]      )
          );
 
      // shuffle between CMs and OMs(OPs)
      assign so0[i] = cmo0[i][0];
      assign so1[i] = cmo1[i][0];
      assign so2[i] = cmo2[i][0];
      assign so3[i] = cmo3[i][0];
      assign so4[i] = cmo4[i][0];
      assign cmoa[i][0] = soa[i];
 
      assign wo0[i] = cmo0[i][1];
      assign wo1[i] = cmo1[i][1];
      assign wo2[i] = cmo2[i][1];
      assign wo3[i] = cmo3[i][1];
      assign wo4[i] = cmo4[i][1];
      assign cmoa[i][1] = woa[i];
 
      assign no0[i] = cmo0[i][2];
      assign no1[i] = cmo1[i][2];
      assign no2[i] = cmo2[i][2];
      assign no3[i] = cmo3[i][2];
      assign no4[i] = cmo4[i][2];
      assign cmoa[i][2] = noa[i];
 
      assign eo0[i] = cmo0[i][3];
      assign eo1[i] = cmo1[i][3];
      assign eo2[i] = cmo2[i][3];
      assign eo3[i] = cmo3[i][3];
      assign eo4[i] = cmo4[i][3];
      assign cmoa[i][3] = eoa[i];
 
      assign lo0[i] = cmo0[i][4];
      assign lo1[i] = cmo1[i][4];
      assign lo2[i] = cmo2[i][4];
      assign lo3[i] = cmo3[i][4];
      assign lo4[i] = cmo4[i][4];
      assign cmoa[i][4] = loa[i];
 
`ifdef ENABLE_BUFFERED_CLOS
      assign cmoa4[i][0] = soa4[i];
      assign cmoa4[i][1] = woa4[i];
      assign cmoa4[i][2] = noa4[i];
      assign cmoa4[i][3] = eoa4[i];
      assign cmoa4[i][4] = loa4[i];
`endif
   end // block: IMSHF
 
   endgenerate
 
 
endmodule // dclos
 
 
 
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	12	wsong0210	`/*`
2			`Asynchronous SDM NoC`
3			`(C)2011 Wei Song`
4			`Advanced Processor Technologies Group`
5			`Computer Science, the Univ. of Manchester, UK`
6
7			`Authors:`
8			`Wei Song wsong83@gmail.com`
9
10			`License: LGPL 3.0 or later`
11
12			`Data Clos network.`
13			`* SystemVerilog is used *`
14
15			`History:`
16			`17/07/2010 Initial version. <wsong83@gmail.com>`
17			`20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>`
18			`23/05/2011 Clean up for opensource. <wsong83@gmail.com>`
19	62	wsong0210	`21/06/2011 Prepare to support buffered Clos. <wsong83@gmail.com>`
20	12	wsong0210
21			`*/`
22
23			`// the router structure definitions`
24			`include "define.v"
25
26	62	wsong0210	`module dclos (`
27	12	wsong0210	`// Outputs`
28			`so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,`
29			`eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,`
30			`wia, nia, eia, lia,`
31			`// Inputs`
32			`si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,`
33			`ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,`
34			`woa, noa, eoa, loa, imcfg, scfg, ncfg, wcfg, ecfg, lcfg`
35	62	wsong0210	`ifdef ENABLE_BUFFERED_CLOS
36			`, soa4, woa4, noa4, eoa4, loa4`
37			`endif
38	12	wsong0210	`);`
39
40			`parameter MN = 2; // number of CMs`
41			`parameter NN = 2; // number of ports in an IM or OM, equ. to number of virtual circuits`
42			`parameter DW = 8; // datawidth of a single virtual circuit/port`
43			`parameter SCN = DW/2; // number of 1-of-4 sub-channels in one port`
44
45			`input [NN-1:0][SCN-1:0] si0, si1, si2, si3; // south input [0], X+1`
46			`input [NN-1:0][SCN-1:0] wi0, wi1, wi2, wi3; // west input [1], Y-1`
47			`input [NN-1:0][SCN-1:0] ni0, ni1, ni2, ni3; // north input [2], X-1`
48			`input [NN-1:0][SCN-1:0] ei0, ei1, ei2, ei3; // east input [3], Y+1`
49			`input [NN-1:0][SCN-1:0] li0, li1, li2, li3; // local input`
50			`output [NN-1:0][SCN-1:0] so0, so1, so2, so3; // south output`
51			`output [NN-1:0][SCN-1:0] wo0, wo1, wo2, wo3; // west output`
52			`output [NN-1:0][SCN-1:0] no0, no1, no2, no3; // north output`
53			`output [NN-1:0][SCN-1:0] eo0, eo1, eo2, eo3; // east output`
54			`output [NN-1:0][SCN-1:0] lo0, lo1, lo2, lo3; // local output`
55
56			`// eof bits and ack lines`
57			`ifdef ENABLE_CHANNEL_SLICING
58			`input [NN-1:0][SCN-1:0] si4, wi4, ni4, ei4, li4;`
59			`output [NN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4;`
60			`output [NN-1:0][SCN-1:0] sia, wia, nia, eia, lia;`
61			`input [NN-1:0][SCN-1:0] soa, woa, noa, eoa, loa;`
62	62	wsong0210	`ifdef ENABLE_BUFFERED_CLOS
63			`input [NN-1:0][SCN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers`
64			`endif
65	12	wsong0210	`else
66			`input [NN-1:0] si4, wi4, ni4, ei4, li4;`
67			`output [NN-1:0] so4, wo4, no4, eo4, lo4;`
68			`output [NN-1:0] sia, wia, nia, eia, lia;`
69			`input [NN-1:0] soa, woa, noa, eoa, loa;`
70	62	wsong0210	`ifdef ENABLE_BUFFERED_CLOS
71			`input [NN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers`
72			`endif
73	12	wsong0210	`endif // !`ifdef ENABLE_CHANNEL_SLICING
74
75			`input [4:0][MN-1:0][NN-1:0] imcfg; // configuration for IMs`
76			`// configuration for CMs`
77			`input [MN-1:0][1:0] scfg, ncfg;`
78			`input [MN-1:0][3:0] wcfg, ecfg, lcfg;`
79			`// no OMs`
80
81			`// output of IMs`
82			`wire [MN-1:0][SCN-1:0] imos0, imos1, imos2, imos3;`
83			`wire [MN-1:0][SCN-1:0] imow0, imow1, imow2, imow3;`
84			`wire [MN-1:0][SCN-1:0] imon0, imon1, imon2, imon3;`
85			`wire [MN-1:0][SCN-1:0] imoe0, imoe1, imoe2, imoe3;`
86			`wire [MN-1:0][SCN-1:0] imol0, imol1, imol2, imol3;`
87			`ifdef ENABLE_CHANNEL_SLICING
88			`wire [MN-1:0][SCN-1:0] imos4, imow4, imon4, imoe4, imol4;`
89			`wire [MN-1:0][SCN-1:0] imosa, imowa, imona, imoea, imola;`
90	62	wsong0210	`ifdef ENABLE_BUFFERED_CLOS
91			`wire [MN-1:0][SCN-1:0] imosa4, imowa4, imona4, imoea4, imola4;`
92			`endif
93	12	wsong0210	`else
94			`wire [MN-1:0] imos4, imow4, imon4, imoe4, imol4;`
95			`wire [MN-1:0] imosa, imowa, imona, imoea, imola;`
96	62	wsong0210	`ifdef ENABLE_BUFFERED_CLOS
97			`wire [MN-1:0] imosa4, imowa4, imona4, imoea4, imola4;`
98			`endif
99	12	wsong0210	`endif
100
101			`// input of CMs`
102			`wire [MN-1:0][4:0][SCN-1:0] cmi0, cmi1, cmi2, cmi3;`
103			`ifdef ENABLE_CHANNEL_SLICING
104			`wire [MN-1:0][4:0][SCN-1:0] cmi4, cmia;`
105			`else
106			`wire [MN-1:0][4:0] cmi4, cmia;`
107			`endif
108
109			`// output of CMs`
110			`wire [MN-1:0][4:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3;`
111			`ifdef ENABLE_CHANNEL_SLICING
112			`wire [MN-1:0][4:0][SCN-1:0] cmo4, cmoa;`
113	62	wsong0210	`ifdef ENABLE_BUFFERED_CLOS
114			`wire [MN-1:0][4:0][SCN-1:0] cmoa4;`
115			`endif
116	12	wsong0210	`else
117			`wire [MN-1:0][4:0] cmo4, cmoa;`
118	62	wsong0210	`ifdef ENABLE_BUFFERED_CLOS
119			`wire [MN-1:0][4:0] cmoa4;`
120			`endif
121	12	wsong0210	`endif
122
123			`genvar i,j,k;`
124
125			`dcb #(.NN(NN), .MN(MN), .DW(DW))`
126			`SIM (`
127	64	wsong0210	`.o0 ( imos0 ),`
128			`.o1 ( imos1 ),`
129			`.o2 ( imos2 ),`
130			`.o3 ( imos3 ),`
131			`.o4 ( imos4 ),`
132			`.ia ( sia ),`
133			`.i0 ( si0 ),`
134			`.i1 ( si1 ),`
135			`.i2 ( si2 ),`
136			`.i3 ( si3 ),`
137			`.i4 ( si4 ),`
138			`.oa ( imosa ),`
139			`ifdef ENABLE_BUFFERED_CLOS
140			`.oa4 ( imosa4 ),`
141			`endif
142			`.cfg ( imcfg[0] )`
143			`);`
144	12	wsong0210
145			`dcb #(.NN(NN), .MN(MN), .DW(DW))`
146			`WIM (`
147	64	wsong0210	`.o0 ( imow0 ),`
148			`.o1 ( imow1 ),`
149			`.o2 ( imow2 ),`
150			`.o3 ( imow3 ),`
151			`.o4 ( imow4 ),`
152			`.ia ( wia ),`
153			`.i0 ( wi0 ),`
154			`.i1 ( wi1 ),`
155			`.i2 ( wi2 ),`
156			`.i3 ( wi3 ),`
157			`.i4 ( wi4 ),`
158			`.oa ( imowa ),`
159			`ifdef ENABLE_BUFFERED_CLOS
160			`.oa4 ( imowa4 ),`
161			`endif
162			`.cfg ( imcfg[1] )`
163			`);`
164	12	wsong0210
165			`dcb #(.NN(NN), .MN(MN), .DW(DW))`
166			`NIM (`
167	64	wsong0210	`.o0 ( imon0 ),`
168			`.o1 ( imon1 ),`
169			`.o2 ( imon2 ),`
170			`.o3 ( imon3 ),`
171			`.o4 ( imon4 ),`
172			`.ia ( nia ),`
173			`.i0 ( ni0 ),`
174			`.i1 ( ni1 ),`
175			`.i2 ( ni2 ),`
176			`.i3 ( ni3 ),`
177			`.i4 ( ni4 ),`
178			`.oa ( imona ),`
179			`ifdef ENABLE_BUFFERED_CLOS
180			`.oa4 ( imona4 ),`
181			`endif
182			`.cfg ( imcfg[2] )`
183	12	wsong0210	`);`
184
185			`dcb #(.NN(NN), .MN(MN), .DW(DW))`
186			`EIM (`
187	64	wsong0210	`.o0 ( imoe0 ),`
188			`.o1 ( imoe1 ),`
189			`.o2 ( imoe2 ),`
190			`.o3 ( imoe3 ),`
191			`.o4 ( imoe4 ),`
192			`.ia ( eia ),`
193			`.i0 ( ei0 ),`
194			`.i1 ( ei1 ),`
195			`.i2 ( ei2 ),`
196			`.i3 ( ei3 ),`
197			`.i4 ( ei4 ),`
198			`.oa ( imoea ),`
199			`ifdef ENABLE_BUFFERED_CLOS
200			`.oa4 ( imoea4 ),`
201			`endif
202			`.cfg ( imcfg[3] )`
203			`);`
204	12	wsong0210
205			`dcb #(.NN(NN), .MN(MN), .DW(DW))`
206			`LIM (`
207	64	wsong0210	`.o0 ( imol0 ),`
208			`.o1 ( imol1 ),`
209			`.o2 ( imol2 ),`
210			`.o3 ( imol3 ),`
211			`.o4 ( imol4 ),`
212			`.ia ( lia ),`
213			`.i0 ( li0 ),`
214			`.i1 ( li1 ),`
215			`.i2 ( li2 ),`
216			`.i3 ( li3 ),`
217			`.i4 ( li4 ),`
218			`.oa ( imola ),`
219			`ifdef ENABLE_BUFFERED_CLOS
220			`.oa4 ( imola4 ),`
221			`endif
222			`.cfg ( imcfg[4] )`
223			`);`
224	12	wsong0210
225			`generate for(i=0; i<MN; i++) begin: IMSHF`
226	64	wsong0210	`ifdef ENABLE_BUFFERED_CLOS
227			`// the buffer stage between IM and CM`
228			`ifdef ENABLE_CHANNEL_SLICING
229			`for(j=0; j<SCN; j++) begin:SC`
230			`pipe4 #(.DW(2))`
231			`P (`
232			`.o0 ( cmi0[i][0] ),`
233			`.o1 ( cmi1[i][0] ),`
234			`.o2 ( cmi2[i][0] ),`
235			`.o3 ( cmi3[i][0] ),`
236			`.ia ( imosa[i] ),`
237			`.i0 ( imos0[i] ),`
238			`.i1 ( imos1[i] ),`
239			`.i2 ( imos3[i] ),`
240			`.i3 ( imos4[i] ),`
241	66	wsong0210	`.oa ( cmian[i][0] )`
242			`);`
243	64	wsong0210
244	66	wsong0210	`pipen #(.DW(1))`
245			`PEoF (`
246			`.d_in_a ( imosa4[i] ),`
247			`.d_out ( cmi4[i][0] ),`
248			`.d_in ( imos4[i] ),`
249			`.d_out_a ( cmian[i][0] ),`
250			`);`
251
252
253
254	64	wsong0210	`else
255	12	wsong0210	`// shuffle the interconnects between IMs and CMs`
256			`assign cmi0[i][0] = imos0[i];`
257			`assign cmi1[i][0] = imos1[i];`
258			`assign cmi2[i][0] = imos2[i];`
259			`assign cmi3[i][0] = imos3[i];`
260			`assign cmi4[i][0] = imos4[i];`
261			`assign imosa[i] = cmia[i][0];`
262
263			`assign cmi0[i][1] = imow0[i];`
264			`assign cmi1[i][1] = imow1[i];`
265			`assign cmi2[i][1] = imow2[i];`
266			`assign cmi3[i][1] = imow3[i];`
267			`assign cmi4[i][1] = imow4[i];`
268			`assign imowa[i] = cmia[i][1];`
269
270			`assign cmi0[i][2] = imon0[i];`
271			`assign cmi1[i][2] = imon1[i];`
272			`assign cmi2[i][2] = imon2[i];`
273			`assign cmi3[i][2] = imon3[i];`
274			`assign cmi4[i][2] = imon4[i];`
275			`assign imona[i] = cmia[i][2];`
276
277			`assign cmi0[i][3] = imoe0[i];`
278			`assign cmi1[i][3] = imoe1[i];`
279			`assign cmi2[i][3] = imoe2[i];`
280			`assign cmi3[i][3] = imoe3[i];`
281			`assign cmi4[i][3] = imoe4[i];`
282			`assign imoea[i] = cmia[i][3];`
283
284			`assign cmi0[i][4] = imol0[i];`
285			`assign cmi1[i][4] = imol1[i];`
286			`assign cmi2[i][4] = imol2[i];`
287			`assign cmi3[i][4] = imol3[i];`
288			`assign cmi4[i][4] = imol4[i];`
289			`assign imola[i] = cmia[i][4];`
290	64	wsong0210	`endif // !`ifdef ENABLE_BUFFERED_CLOS
291
292	12	wsong0210	`// CM modules`
293			`dcb_xy #(.VCN(1), .VCW(DW))`
294			`CM (`
295			`.sia ( cmia[i][0] ),`
296			`.wia ( cmia[i][1] ),`
297			`.nia ( cmia[i][2] ),`
298			`.eia ( cmia[i][3] ),`
299			`.lia ( cmia[i][4] ),`
300			`.so0 ( cmo0[i][0] ),`
301			`.so1 ( cmo1[i][0] ),`
302			`.so2 ( cmo2[i][0] ),`
303			`.so3 ( cmo3[i][0] ),`
304			`.so4 ( cmo4[i][0] ),`
305			`.wo0 ( cmo0[i][1] ),`
306			`.wo1 ( cmo1[i][1] ),`
307			`.wo2 ( cmo2[i][1] ),`
308			`.wo3 ( cmo3[i][1] ),`
309			`.wo4 ( cmo4[i][1] ) ,`
310			`.no0 ( cmo0[i][2] ),`
311			`.no1 ( cmo1[i][2] ),`
312			`.no2 ( cmo2[i][2] ),`
313			`.no3 ( cmo3[i][2] ),`
314			`.no4 ( cmo4[i][2] ),`
315			`.eo0 ( cmo0[i][3] ),`
316			`.eo1 ( cmo1[i][3] ),`
317			`.eo2 ( cmo2[i][3] ),`
318			`.eo3 ( cmo3[i][3] ),`
319			`.eo4 ( cmo4[i][3] ),`
320			`.lo0 ( cmo0[i][4] ),`
321			`.lo1 ( cmo1[i][4] ),`
322			`.lo2 ( cmo2[i][4] ),`
323			`.lo3 ( cmo3[i][4] ),`
324			`.lo4 ( cmo4[i][4] ),`
325			`.si0 ( cmi0[i][0] ),`
326			`.si1 ( cmi1[i][0] ),`
327			`.si2 ( cmi2[i][0] ),`
328			`.si3 ( cmi3[i][0] ),`
329			`.si4 ( cmi4[i][0] ),`
330			`.wi0 ( cmi0[i][1] ),`
331			`.wi1 ( cmi1[i][1] ),`
332			`.wi2 ( cmi2[i][1] ),`
333			`.wi3 ( cmi3[i][1] ),`
334			`.wi4 ( cmi4[i][1] ),`
335			`.ni0 ( cmi0[i][2] ),`
336			`.ni1 ( cmi1[i][2] ),`
337			`.ni2 ( cmi2[i][2] ),`
338			`.ni3 ( cmi3[i][2] ),`
339			`.ni4 ( cmi4[i][2] ),`
340			`.ei0 ( cmi0[i][3] ),`
341			`.ei1 ( cmi1[i][3] ),`
342			`.ei2 ( cmi2[i][3] ),`
343			`.ei3 ( cmi3[i][3] ),`
344			`.ei4 ( cmi4[i][3] ),`
345			`.li0 ( cmi0[i][4] ),`
346			`.li1 ( cmi1[i][4] ),`
347			`.li2 ( cmi2[i][4] ),`
348			`.li3 ( cmi3[i][4] ),`
349			`.li4 ( cmi4[i][4] ),`
350			`.soa ( cmoa[i][0] ),`
351	64	wsong0210	`.woa ( cmoa[i][1] ),`
352			`.noa ( cmoa[i][2] ),`
353			`.eoa ( cmoa[i][3] ),`
354			`.loa ( cmoa[i][4] ),`
355			`ifdef ENABLE_BUFFERED_CLOS
356			`.soa4 ( cmoa4[i][0] ),`
357			`.woa4 ( cmoa4[i][1] ),`
358			`.noa4 ( cmoa4[i][2] ),`
359			`.eoa4 ( cmoa4[i][3] ),`
360			`.loa4 ( cmoa4[i][4] ),`
361			`endif
362	12	wsong0210	`.wcfg ( wcfg[i] ),`
363			`.ecfg ( ecfg[i] ),`
364			`.lcfg ( lcfg[i] ),`
365			`.scfg ( scfg[i] ),`
366			`.ncfg ( ncfg[i] )`
367			`);`
368
369			`// shuffle between CMs and OMs(OPs)`
370			`assign so0[i] = cmo0[i][0];`
371			`assign so1[i] = cmo1[i][0];`
372			`assign so2[i] = cmo2[i][0];`
373			`assign so3[i] = cmo3[i][0];`
374			`assign so4[i] = cmo4[i][0];`
375			`assign cmoa[i][0] = soa[i];`
376
377			`assign wo0[i] = cmo0[i][1];`
378			`assign wo1[i] = cmo1[i][1];`
379			`assign wo2[i] = cmo2[i][1];`
380			`assign wo3[i] = cmo3[i][1];`
381			`assign wo4[i] = cmo4[i][1];`
382			`assign cmoa[i][1] = woa[i];`
383
384			`assign no0[i] = cmo0[i][2];`
385			`assign no1[i] = cmo1[i][2];`
386			`assign no2[i] = cmo2[i][2];`
387			`assign no3[i] = cmo3[i][2];`
388			`assign no4[i] = cmo4[i][2];`
389			`assign cmoa[i][2] = noa[i];`
390
391			`assign eo0[i] = cmo0[i][3];`
392			`assign eo1[i] = cmo1[i][3];`
393			`assign eo2[i] = cmo2[i][3];`
394			`assign eo3[i] = cmo3[i][3];`
395			`assign eo4[i] = cmo4[i][3];`
396			`assign cmoa[i][3] = eoa[i];`
397
398			`assign lo0[i] = cmo0[i][4];`
399			`assign lo1[i] = cmo1[i][4];`
400			`assign lo2[i] = cmo2[i][4];`
401			`assign lo3[i] = cmo3[i][4];`
402			`assign lo4[i] = cmo4[i][4];`
403			`assign cmoa[i][4] = loa[i];`
404	64	wsong0210
405			`ifdef ENABLE_BUFFERED_CLOS
406			`assign cmoa4[i][0] = soa4[i];`
407			`assign cmoa4[i][1] = woa4[i];`
408			`assign cmoa4[i][2] = noa4[i];`
409			`assign cmoa4[i][3] = eoa4[i];`
410			`assign cmoa4[i][4] = loa4[i];`
411			`endif
412	12	wsong0210	`end // block: IMSHF`
413
414			`endgenerate`
415
416
417			`endmodule // dclos`
418
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