OpenCores
URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [branches/] [clos_opt/] [common/] [src/] [dclos.v] - Blame information for rev 67

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 wsong0210 
/*
2 
 Asynchronous SDM NoC
3 
 (C)2011 Wei Song
4 
 Advanced Processor Technologies Group
5 
 Computer Science, the Univ. of Manchester, UK
6 
 
7 
 Authors:
8 
 Wei Song     wsong83@gmail.com
9 
 
10 
 License: LGPL 3.0 or later
11 
 
12 
 Data Clos network.
13 
 *** SystemVerilog is used ***
14 
 
15 
 History:
16 
 17/07/2010  Initial version. <wsong83@gmail.com>
17 
 20/09/2010  Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
18 
 23/05/2011  Clean up for opensource. <wsong83@gmail.com>
19 62 wsong0210 
 21/06/2011  Prepare to support buffered Clos. <wsong83@gmail.com>
20 12 wsong0210 
 
21 
*/
22 
 
23 
// the router structure definitions
24 
`include "define.v"
25 
 
26 62 wsong0210 
module dclos (
27 12 wsong0210 
   // Outputs
28 
   so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
29 
   eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
30 
   wia, nia, eia, lia,
31 
   // Inputs
32 
   si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
33 
   ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
34 
   woa, noa, eoa, loa, imcfg, scfg, ncfg, wcfg, ecfg, lcfg
35 62 wsong0210 
`ifdef ENABLE_BUFFERED_CLOS
36 
   , soa4, woa4, noa4, eoa4, loa4
37 
`endif
38 67 wsong0210 
   , rst_n
39 12 wsong0210 
   );
40 
 
41 
   parameter MN = 2;            // number of CMs
42 
   parameter NN = 2;            // number of ports in an IM or OM, equ. to number of virtual circuits
43 
   parameter DW = 8;            // datawidth of a single virtual circuit/port
44 
   parameter SCN = DW/2;        // number of 1-of-4 sub-channels in one port
45 
 
46 
   input [NN-1:0][SCN-1:0]     si0, si1, si2, si3; // south input [0], X+1
47 
   input [NN-1:0][SCN-1:0]     wi0, wi1, wi2, wi3; // west input [1], Y-1
48 
   input [NN-1:0][SCN-1:0]     ni0, ni1, ni2, ni3; // north input [2], X-1
49 
   input [NN-1:0][SCN-1:0]     ei0, ei1, ei2, ei3; // east input [3], Y+1
50 
   input [NN-1:0][SCN-1:0]     li0, li1, li2, li3; // local input
51 
   output [NN-1:0][SCN-1:0]    so0, so1, so2, so3; // south output
52 
   output [NN-1:0][SCN-1:0]    wo0, wo1, wo2, wo3; // west output
53 
   output [NN-1:0][SCN-1:0]    no0, no1, no2, no3; // north output
54 
   output [NN-1:0][SCN-1:0]    eo0, eo1, eo2, eo3; // east output
55 
   output [NN-1:0][SCN-1:0]    lo0, lo1, lo2, lo3; // local output
56 
 
57 
   // eof bits and ack lines
58 
`ifdef ENABLE_CHANNEL_SLICING
59 
   input [NN-1:0][SCN-1:0]     si4, wi4, ni4, ei4, li4;
60 
   output [NN-1:0][SCN-1:0]    so4, wo4, no4, eo4, lo4;
61 
   output [NN-1:0][SCN-1:0]    sia, wia, nia, eia, lia;
62 
   input [NN-1:0][SCN-1:0]     soa, woa, noa, eoa, loa;
63 62 wsong0210 
 `ifdef ENABLE_BUFFERED_CLOS
64 
   input [NN-1:0][SCN-1:0]     soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
65 
 `endif
66 12 wsong0210 
`else
67 
   input [NN-1:0]               si4, wi4, ni4, ei4, li4;
68 
   output [NN-1:0]              so4, wo4, no4, eo4, lo4;
69 
   output [NN-1:0]              sia, wia, nia, eia, lia;
70 
   input [NN-1:0]               soa, woa, noa, eoa, loa;
71 62 wsong0210 
 `ifdef ENABLE_BUFFERED_CLOS
72 
   input [NN-1:0]               soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
73 
 `endif
74 12 wsong0210 
`endif // !`ifdef ENABLE_CHANNEL_SLICING
75 
 
76 
   input [4:0][MN-1:0][NN-1:0] imcfg; // configuration for IMs
77 
   // configuration for CMs
78 
   input [MN-1:0][1:0]           scfg, ncfg;
79 
   input [MN-1:0][3:0]           wcfg, ecfg, lcfg;
80 
   // no OMs
81 
 
82 67 wsong0210 
   input                       rst_n; // globale active low reset
83 
 
84 12 wsong0210 
   // output of IMs
85 
   wire [MN-1:0][SCN-1:0]      imos0, imos1, imos2, imos3;
86 
   wire [MN-1:0][SCN-1:0]      imow0, imow1, imow2, imow3;
87 
   wire [MN-1:0][SCN-1:0]      imon0, imon1, imon2, imon3;
88 
   wire [MN-1:0][SCN-1:0]      imoe0, imoe1, imoe2, imoe3;
89 
   wire [MN-1:0][SCN-1:0]      imol0, imol1, imol2, imol3;
90 
`ifdef ENABLE_CHANNEL_SLICING
91 
   wire [MN-1:0][SCN-1:0]      imos4, imow4, imon4, imoe4, imol4;
92 
   wire [MN-1:0][SCN-1:0]      imosa, imowa, imona, imoea, imola;
93 62 wsong0210 
 `ifdef ENABLE_BUFFERED_CLOS
94 
   wire [MN-1:0][SCN-1:0]      imosa4, imowa4, imona4, imoea4, imola4;
95 67 wsong0210 
   wire [MN-1:0][SCN-1:0]      imosdeca, imowdeca, imondeca, imoedeca, imoldeca;
96 
   wire [MN-1:0][SCN-1:0]      imoseofan, imoweofan, imoneofan, imoeeofan, imoleofan;
97 62 wsong0210 
 `endif
98 12 wsong0210 
`else
99 
   wire [MN-1:0]                imos4, imow4, imon4, imoe4, imol4;
100 
   wire [MN-1:0]                imosa, imowa, imona, imoea, imola;
101 62 wsong0210 
 `ifdef ENABLE_BUFFERED_CLOS
102 67 wsong0210 
   wire [MN-1:0]               imosdeca, imowdeca, imondeca, imoedeca, imoldeca;
103 62 wsong0210 
   wire [MN-1:0]                imosa4, imowa4, imona4, imoea4, imola4;
104 67 wsong0210 
   wire [MN-1:0]                imoseofan, imoweofan, imoneofan, imoeeofan, imoleofan;
105 62 wsong0210 
 `endif
106 12 wsong0210 
`endif
107 
 
108 
   // input of CMs
109 
   wire [MN-1:0][4:0][SCN-1:0] cmi0, cmi1, cmi2, cmi3;
110 
`ifdef ENABLE_CHANNEL_SLICING
111 
   wire [MN-1:0][4:0][SCN-1:0] cmi4, cmia;
112 67 wsong0210 
 `ifdef ENABLE_BUFFERED_CLOS
113 
   wire [MN-1:0][4:0][SCN-1:0] cmian;
114 
 `endif
115 12 wsong0210 
`else
116 
   wire [MN-1:0][4:0]            cmi4, cmia;
117 67 wsong0210 
 `ifdef ENABLE_BUFFERED_CLOS
118 
   wire [MN-1:0][4:0]            cmian;
119 
 `endif
120 12 wsong0210 
`endif
121 
 
122 
   // output of CMs
123 
   wire [MN-1:0][4:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3;
124 
`ifdef ENABLE_CHANNEL_SLICING
125 
   wire [MN-1:0][4:0][SCN-1:0] cmo4, cmoa;
126 62 wsong0210 
 `ifdef ENABLE_BUFFERED_CLOS
127 
   wire [MN-1:0][4:0][SCN-1:0] cmoa4;
128 
 `endif
129 12 wsong0210 
`else
130 
   wire [MN-1:0][4:0]            cmo4, cmoa;
131 62 wsong0210 
 `ifdef ENABLE_BUFFERED_CLOS
132 
   wire [MN-1:0][4:0]            cmoa4;
133 
 `endif
134 12 wsong0210 
`endif
135 
 
136 
   genvar                      i,j,k;
137 
 
138 
   dcb #(.NN(NN), .MN(MN), .DW(DW))
139 
   SIM (
140 64 wsong0210 
        .o0  ( imos0    ),
141 
        .o1  ( imos1    ),
142 
        .o2  ( imos2    ),
143 
        .o3  ( imos3    ),
144 
        .o4  ( imos4    ),
145 
        .ia  ( sia      ),
146 
        .i0  ( si0      ),
147 
        .i1  ( si1      ),
148 
        .i2  ( si2      ),
149 
        .i3  ( si3      ),
150 
        .i4  ( si4      ),
151 
        .oa  ( imosa    ),
152 
`ifdef ENABLE_BUFFERED_CLOS
153 
        .oa4 ( imosa4   ),
154 
`endif
155 
        .cfg ( imcfg[0] )
156 
        );
157 12 wsong0210 
 
158 
   dcb #(.NN(NN), .MN(MN), .DW(DW))
159 
   WIM (
160 64 wsong0210 
        .o0  ( imow0    ),
161 
        .o1  ( imow1    ),
162 
        .o2  ( imow2    ),
163 
        .o3  ( imow3    ),
164 
        .o4  ( imow4    ),
165 
        .ia  ( wia      ),
166 
        .i0  ( wi0      ),
167 
        .i1  ( wi1      ),
168 
        .i2  ( wi2      ),
169 
        .i3  ( wi3      ),
170 
        .i4  ( wi4      ),
171 
        .oa  ( imowa    ),
172 
`ifdef ENABLE_BUFFERED_CLOS
173 
        .oa4 ( imowa4   ),
174 
`endif
175 
        .cfg ( imcfg[1] )
176 
        );
177 12 wsong0210 
 
178 
   dcb #(.NN(NN), .MN(MN), .DW(DW))
179 
   NIM (
180 64 wsong0210 
        .o0  ( imon0    ),
181 
        .o1  ( imon1    ),
182 
        .o2  ( imon2    ),
183 
        .o3  ( imon3    ),
184 
        .o4  ( imon4    ),
185 
        .ia  ( nia      ),
186 
        .i0  ( ni0      ),
187 
        .i1  ( ni1      ),
188 
        .i2  ( ni2      ),
189 
        .i3  ( ni3      ),
190 
        .i4  ( ni4      ),
191 
        .oa  ( imona    ),
192 
`ifdef ENABLE_BUFFERED_CLOS
193 
        .oa4 ( imona4   ),
194 
`endif
195 
        .cfg ( imcfg[2] )
196 12 wsong0210 
       );
197 
 
198 
   dcb #(.NN(NN), .MN(MN), .DW(DW))
199 
   EIM (
200 64 wsong0210 
        .o0  ( imoe0    ),
201 
        .o1  ( imoe1    ),
202 
        .o2  ( imoe2    ),
203 
        .o3  ( imoe3    ),
204 
        .o4  ( imoe4    ),
205 
        .ia  ( eia      ),
206 
        .i0  ( ei0      ),
207 
        .i1  ( ei1      ),
208 
        .i2  ( ei2      ),
209 
        .i3  ( ei3      ),
210 
        .i4  ( ei4      ),
211 
        .oa  ( imoea    ),
212 
`ifdef ENABLE_BUFFERED_CLOS
213 
        .oa4 ( imoea4   ),
214 
`endif
215 
        .cfg ( imcfg[3] )
216 
        );
217 12 wsong0210 
 
218 
   dcb #(.NN(NN), .MN(MN), .DW(DW))
219 
   LIM (
220 64 wsong0210 
        .o0  ( imol0    ),
221 
        .o1  ( imol1    ),
222 
        .o2  ( imol2    ),
223 
        .o3  ( imol3    ),
224 
        .o4  ( imol4    ),
225 
        .ia  ( lia      ),
226 
        .i0  ( li0      ),
227 
        .i1  ( li1      ),
228 
        .i2  ( li2      ),
229 
        .i3  ( li3      ),
230 
        .i4  ( li4      ),
231 
        .oa  ( imola    ),
232 
`ifdef ENABLE_BUFFERED_CLOS
233 
        .oa4 ( imola4   ),
234 
`endif
235 
        .cfg ( imcfg[4] )
236 
        );
237 12 wsong0210 
 
238 
   generate for(i=0; i<MN; i++) begin: IMSHF
239 64 wsong0210 
`ifdef ENABLE_BUFFERED_CLOS
240 
      // the buffer stage between IM and CM
241 
 `ifdef ENABLE_CHANNEL_SLICING
242 67 wsong0210 
      for(j=0; j<SCN; j++) begin:SC_S
243 64 wsong0210 
         pipe4 #(.DW(2))
244 
         P (
245 
            .o0 ( cmi0[i][0]  ),
246 
            .o1 ( cmi1[i][0]  ),
247 
            .o2 ( cmi2[i][0]  ),
248 
            .o3 ( cmi3[i][0]  ),
249 
            .ia ( imosa[i]    ),
250 
            .i0 ( imos0[i]    ),
251 
            .i1 ( imos1[i]    ),
252 
            .i2 ( imos3[i]    ),
253 
            .i3 ( imos4[i]    ),
254 66 wsong0210 
            .oa ( cmian[i][0]  )
255 
            );
256 67 wsong0210 
 
257 66 wsong0210 
         pipen #(.DW(1))
258 
         PEoF (
259 67 wsong0210 
               .d_in_a  (              ),  // imosa4[i]    ),
260 
               .d_out   ( cmi4[i][0]   ),
261 
               .d_in    ( imos4[i]     ),
262 
               .d_out_a ( imoseofan[i] ),
263 66 wsong0210 
               );
264 
 
265 67 wsong0210 
         ppc PCTL (
266 
                   .deca  ( imosdeca[i]   ),
267 
                   .dia   ( imosa4[i]     ),
268 
                   .eof   ( cmi4[i][0]    ),
269 
                   .doa   ( cmia[i][0]    ),
270 
                   .dec   (
271 
                   );
272 66 wsong0210 
 
273 67 wsong0210 
         assign cmian[i][0] = (~cmia[i][0])&rst_n;
274 
         assign imoseofan[i] = (imosdeca[i])&rst_n;
275 
      end // block: SC
276 66 wsong0210 
 
277 67 wsong0210 
      pipen #(.DW(4))
278 
      S_PDIR (
279 
              .d_in_a (
280 
 
281 
 
282 
 
283 
 
284 64 wsong0210 
`else
285 12 wsong0210 
      // shuffle the interconnects between IMs and CMs
286 
      assign cmi0[i][0] = imos0[i];
287 
      assign cmi1[i][0] = imos1[i];
288 
      assign cmi2[i][0] = imos2[i];
289 
      assign cmi3[i][0] = imos3[i];
290 
      assign cmi4[i][0] = imos4[i];
291 
      assign imosa[i] = cmia[i][0];
292 
 
293 
      assign cmi0[i][1] = imow0[i];
294 
      assign cmi1[i][1] = imow1[i];
295 
      assign cmi2[i][1] = imow2[i];
296 
      assign cmi3[i][1] = imow3[i];
297 
      assign cmi4[i][1] = imow4[i];
298 
      assign imowa[i] = cmia[i][1];
299 
 
300 
      assign cmi0[i][2] = imon0[i];
301 
      assign cmi1[i][2] = imon1[i];
302 
      assign cmi2[i][2] = imon2[i];
303 
      assign cmi3[i][2] = imon3[i];
304 
      assign cmi4[i][2] = imon4[i];
305 
      assign imona[i] = cmia[i][2];
306 
 
307 
      assign cmi0[i][3] = imoe0[i];
308 
      assign cmi1[i][3] = imoe1[i];
309 
      assign cmi2[i][3] = imoe2[i];
310 
      assign cmi3[i][3] = imoe3[i];
311 
      assign cmi4[i][3] = imoe4[i];
312 
      assign imoea[i] = cmia[i][3];
313 
 
314 
      assign cmi0[i][4] = imol0[i];
315 
      assign cmi1[i][4] = imol1[i];
316 
      assign cmi2[i][4] = imol2[i];
317 
      assign cmi3[i][4] = imol3[i];
318 
      assign cmi4[i][4] = imol4[i];
319 
      assign imola[i] = cmia[i][4];
320 64 wsong0210 
`endif // !`ifdef ENABLE_BUFFERED_CLOS
321 
 
322 12 wsong0210 
      // CM modules
323 
      dcb_xy #(.VCN(1), .VCW(DW))
324 
      CM (
325 
          .sia   ( cmia[i][0]   ),
326 
          .wia   ( cmia[i][1]   ),
327 
          .nia   ( cmia[i][2]   ),
328 
          .eia   ( cmia[i][3]   ),
329 
          .lia   ( cmia[i][4]   ),
330 
          .so0   ( cmo0[i][0]   ),
331 
          .so1   ( cmo1[i][0]   ),
332 
          .so2   ( cmo2[i][0]   ),
333 
          .so3   ( cmo3[i][0]   ),
334 
          .so4   ( cmo4[i][0]   ),
335 
          .wo0   ( cmo0[i][1]   ),
336 
          .wo1   ( cmo1[i][1]   ),
337 
          .wo2   ( cmo2[i][1]   ),
338 
          .wo3   ( cmo3[i][1]   ),
339 
          .wo4   ( cmo4[i][1]   ) ,
340 
          .no0   ( cmo0[i][2]   ),
341 
          .no1   ( cmo1[i][2]   ),
342 
          .no2   ( cmo2[i][2]   ),
343 
          .no3   ( cmo3[i][2]   ),
344 
          .no4   ( cmo4[i][2]   ),
345 
          .eo0   ( cmo0[i][3]   ),
346 
          .eo1   ( cmo1[i][3]   ),
347 
          .eo2   ( cmo2[i][3]   ),
348 
          .eo3   ( cmo3[i][3]   ),
349 
          .eo4   ( cmo4[i][3]   ),
350 
          .lo0   ( cmo0[i][4]   ),
351 
          .lo1   ( cmo1[i][4]   ),
352 
          .lo2   ( cmo2[i][4]   ),
353 
          .lo3   ( cmo3[i][4]   ),
354 
          .lo4   ( cmo4[i][4]   ),
355 
          .si0   ( cmi0[i][0]   ),
356 
          .si1   ( cmi1[i][0]   ),
357 
          .si2   ( cmi2[i][0]   ),
358 
          .si3   ( cmi3[i][0]   ),
359 
          .si4   ( cmi4[i][0]   ),
360 
          .wi0   ( cmi0[i][1]   ),
361 
          .wi1   ( cmi1[i][1]   ),
362 
          .wi2   ( cmi2[i][1]   ),
363 
          .wi3   ( cmi3[i][1]   ),
364 
          .wi4   ( cmi4[i][1]   ),
365 
          .ni0   ( cmi0[i][2]   ),
366 
          .ni1   ( cmi1[i][2]   ),
367 
          .ni2   ( cmi2[i][2]   ),
368 
          .ni3   ( cmi3[i][2]   ),
369 
          .ni4   ( cmi4[i][2]   ),
370 
          .ei0   ( cmi0[i][3]   ),
371 
          .ei1   ( cmi1[i][3]   ),
372 
          .ei2   ( cmi2[i][3]   ),
373 
          .ei3   ( cmi3[i][3]   ),
374 
          .ei4   ( cmi4[i][3]   ),
375 
          .li0   ( cmi0[i][4]   ),
376 
          .li1   ( cmi1[i][4]   ),
377 
          .li2   ( cmi2[i][4]   ),
378 
          .li3   ( cmi3[i][4]   ),
379 
          .li4   ( cmi4[i][4]   ),
380 
          .soa   ( cmoa[i][0]   ),
381 64 wsong0210 
          .woa   ( cmoa[i][1]   ),
382 
          .noa   ( cmoa[i][2]   ),
383 
          .eoa   ( cmoa[i][3]   ),
384 
          .loa   ( cmoa[i][4]   ),
385 
`ifdef ENABLE_BUFFERED_CLOS
386 
          .soa4  ( cmoa4[i][0]  ),
387 
          .woa4  ( cmoa4[i][1]  ),
388 
          .noa4  ( cmoa4[i][2]  ),
389 
          .eoa4  ( cmoa4[i][3]  ),
390 
          .loa4  ( cmoa4[i][4]  ),
391 
`endif
392 12 wsong0210 
          .wcfg  ( wcfg[i]      ),
393 
          .ecfg  ( ecfg[i]      ),
394 
          .lcfg  ( lcfg[i]      ),
395 
          .scfg  ( scfg[i]      ),
396 
          .ncfg  ( ncfg[i]      )
397 
          );
398 
 
399 
      // shuffle between CMs and OMs(OPs)
400 
      assign so0[i] = cmo0[i][0];
401 
      assign so1[i] = cmo1[i][0];
402 
      assign so2[i] = cmo2[i][0];
403 
      assign so3[i] = cmo3[i][0];
404 
      assign so4[i] = cmo4[i][0];
405 
      assign cmoa[i][0] = soa[i];
406 
 
407 
      assign wo0[i] = cmo0[i][1];
408 
      assign wo1[i] = cmo1[i][1];
409 
      assign wo2[i] = cmo2[i][1];
410 
      assign wo3[i] = cmo3[i][1];
411 
      assign wo4[i] = cmo4[i][1];
412 
      assign cmoa[i][1] = woa[i];
413 
 
414 
      assign no0[i] = cmo0[i][2];
415 
      assign no1[i] = cmo1[i][2];
416 
      assign no2[i] = cmo2[i][2];
417 
      assign no3[i] = cmo3[i][2];
418 
      assign no4[i] = cmo4[i][2];
419 
      assign cmoa[i][2] = noa[i];
420 
 
421 
      assign eo0[i] = cmo0[i][3];
422 
      assign eo1[i] = cmo1[i][3];
423 
      assign eo2[i] = cmo2[i][3];
424 
      assign eo3[i] = cmo3[i][3];
425 
      assign eo4[i] = cmo4[i][3];
426 
      assign cmoa[i][3] = eoa[i];
427 
 
428 
      assign lo0[i] = cmo0[i][4];
429 
      assign lo1[i] = cmo1[i][4];
430 
      assign lo2[i] = cmo2[i][4];
431 
      assign lo3[i] = cmo3[i][4];
432 
      assign lo4[i] = cmo4[i][4];
433 
      assign cmoa[i][4] = loa[i];
434 64 wsong0210 
 
435 
`ifdef ENABLE_BUFFERED_CLOS
436 
      assign cmoa4[i][0] = soa4[i];
437 
      assign cmoa4[i][1] = woa4[i];
438 
      assign cmoa4[i][2] = noa4[i];
439 
      assign cmoa4[i][3] = eoa4[i];
440 
      assign cmoa4[i][4] = loa4[i];
441 
`endif
442 12 wsong0210 
   end // block: IMSHF
443 
 
444 
   endgenerate
445 
 
446 
 
447 
endmodule // dclos
448 
 
449 
 
450 
 
451 
 
452 
 
453 
 
454 
 
455 
 
456 
 
457 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.