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/*
 Asynchronous SDM NoC
 (C)2011 Wei Song
 Advanced Processor Technologies Group
 Computer Science, the Univ. of Manchester, UK
 
 Authors:
 Wei Song     wsong83@gmail.com
 
 License: LGPL 3.0 or later
 
 Output buffer for Wormhole/SDM routers.
 *** SystemVerilog is used ***
 
 History:
 26/05/2009  Initial version. <wsong83@gmail.com>
 20/09/2010  Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
 22/10/2010  Parameterize the number of pipelines in output buffers. <wsong83@gmail.com>
 23/05/2011  Clean up for opensource. <wsong83@gmail.com>
 
*/
 
// the router structure definitions
`include "define.v"
 
// the out buffer
module outp_buf (/*AUTOARG*/
   // Outputs
   o0, o1, o2, o3, o4, ia,
   // Inputs
   rst_n, i0, i1, i2, i3, i4, oa
   );
 
   parameter DW = 16;           // the datawidth of a single virtual circuit
   parameter PD = 2;            // buffer depth
   parameter SCN = DW/2;        // the number of 1-of-4 sub-channel in each virtual circuit
 
   input                  rst_n;          // global reset, active low
   input [SCN-1:0]         i0, i1, i2, i3; // data input
   output [SCN-1:0]        o0, o1, o2, o3; // data output
   wire [PD:0][SCN-1:0]   pd0, pd1, pd2, pd3;  // data wires for the internal pipeline satges
`ifdef ENABLE_CHANNEL_SLICING
   input [SCN-1:0]         i4, oa; // eof and ack
   output [SCN-1:0]        o4, ia;
   wire [SCN-1:0]          ian_dly;
   wire [PD:0][SCN-1:0]   pd4, pda, pdan; // internal eof and ack
`else
   input                  i4, oa; // eof and ack
   output                 o4, ia;
   wire                   ian_dly;
   wire [PD:0]             pd4, pda, pdan; // internal eof and ack
`endif
 
 
//-------------------------- pipeline ---------------------------------------//
    genvar       i,j;
   generate for(i=0; i<PD; i++) begin: DP
`ifdef ENABLE_CHANNEL_SLICING
      for(j=0; j<SCN; j++) begin: SC
         pipe4 #(.DW(2))
         P (
            .o0  ( pd0[i][j]   ),
            .o1  ( pd1[i][j]   ),
            .o2  ( pd2[i][j]   ),
            .o3  ( pd3[i][j]   ),
            .o4  ( pd4[i][j]   ),
            .ia  ( pda[i+1][j] ),
            .i0  ( pd0[i+1][j] ),
            .i1  ( pd1[i+1][j] ),
            .i2  ( pd2[i+1][j] ),
            .i3  ( pd3[i+1][j] ),
            .i4  ( pd4[i+1][j] ),
            .oa  ( pdan[i][j]  )
            );
      end // block: SC
 
`else // !`ifdef ENABLE_CHANNEL_SLICING
      pipe4 #(.DW(DW))
      P (
         .o0  ( pd0[i]   ),
         .o1  ( pd1[i]   ),
         .o2  ( pd2[i]   ),
         .o3  ( pd3[i]   ),
         .o4  ( pd4[i]   ),
         .ia  ( pda[i+1] ),
         .i0  ( pd0[i+1] ),
         .i1  ( pd1[i+1] ),
         .i2  ( pd2[i+1] ),
         .i3  ( pd3[i+1] ),
         .i4  ( pd4[i+1] ),
         .oa  ( pdan[i]  )
         );
`endif // !`ifdef ENABLE_CHANNEL_SLICING
   end // block: DP
   endgenerate
 
   // generate the ack lines for data pipelines
   generate for(i=1; i<PD; i++) begin: DPA
      assign pdan[i] = rst_n ? ~(pda[i]|pd4[i-1]) : 0;
   end
   endgenerate
 
   // generate the input ack, add the AND gate if lookahead pipelines are used
   generate
`ifdef ENABLE_CHANNEL_SLICING
      for(j=0; j<SCN; j++) begin: SCA
 `ifdef ENABLE_LOOKAHEAD
         and ACKG (ia[j], pda[PD][j]|pd4[PD-1][j], ian_dly[j]);
         delay DLY ( .q(ian_dly[j]), .a(pdan[PD-1][j]));
 `else
         assign ia[j] = pda[PD][j]|pd4[PD-1][j];
 `endif
         assign pdan[0][j] = (~oa[j])&rst_n;
      end
`else
 `ifdef ENABLE_LOOKAHEAD
      and ACKG (ia, pda[PD]|pd4[PD-1], ian_dly);
      delay DLY ( .q(ian_dly), .a(pdan[PD-1]));
 `else
      assign ia = pda[PD]|pd4[PD-1];
 `endif
      assign pdan[0] = (~oa)&rst_n;
`endif // !`ifdef ENABLE_LOOKAHEAD
   endgenerate
 
   // name change
   assign pd0[PD] = i0;
   assign pd1[PD] = i1;
   assign pd2[PD] = i2;
   assign pd3[PD] = i3;
   assign pd4[PD] = i4;
   assign o0 = pd0[0];
   assign o1 = pd1[0];
   assign o2 = pd2[0];
   assign o3 = pd3[0];
   assign o4 = pd4[0];
 
endmodule // outp_buf
 

Line No.	Rev	Author	Line
1	14	wsong0210	`/*`
2			`Asynchronous SDM NoC`
3			`(C)2011 Wei Song`
4			`Advanced Processor Technologies Group`
5			`Computer Science, the Univ. of Manchester, UK`
6
7			`Authors:`
8			`Wei Song wsong83@gmail.com`
9
10			`License: LGPL 3.0 or later`
11
12			`Output buffer for Wormhole/SDM routers.`
13			`* SystemVerilog is used *`
14
15			`History:`
16			`26/05/2009 Initial version. <wsong83@gmail.com>`
17			`20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>`
18			`22/10/2010 Parameterize the number of pipelines in output buffers. <wsong83@gmail.com>`
19			`23/05/2011 Clean up for opensource. <wsong83@gmail.com>`
20
21			`*/`
22
23			`// the router structure definitions`
24			`include "define.v"
25
26			`// the out buffer`
27			`module outp_buf (/AUTOARG/`
28			`// Outputs`
29			`o0, o1, o2, o3, o4, ia,`
30			`// Inputs`
31			`rst_n, i0, i1, i2, i3, i4, oa`
32			`);`
33
34			`parameter DW = 16; // the datawidth of a single virtual circuit`
35			`parameter PD = 2; // buffer depth`
36			`parameter SCN = DW/2; // the number of 1-of-4 sub-channel in each virtual circuit`
37
38			`input rst_n; // global reset, active low`
39			`input [SCN-1:0] i0, i1, i2, i3; // data input`
40			`output [SCN-1:0] o0, o1, o2, o3; // data output`
41			`wire [PD:0][SCN-1:0] pd0, pd1, pd2, pd3; // data wires for the internal pipeline satges`
42			`ifdef ENABLE_CHANNEL_SLICING
43			`input [SCN-1:0] i4, oa; // eof and ack`
44			`output [SCN-1:0] o4, ia;`
45			`wire [SCN-1:0] ian_dly;`
46			`wire [PD:0][SCN-1:0] pd4, pda, pdan; // internal eof and ack`
47			`else
48			`input i4, oa; // eof and ack`
49			`output o4, ia;`
50			`wire ian_dly;`
51			`wire [PD:0] pd4, pda, pdan; // internal eof and ack`
52			`endif
53
54
55			`//-------------------------- pipeline ---------------------------------------//`
56			`genvar i,j;`
57			`generate for(i=0; i<PD; i++) begin: DP`
58			`ifdef ENABLE_CHANNEL_SLICING
59			`for(j=0; j<SCN; j++) begin: SC`
60			`pipe4 #(.DW(2))`
61			`P (`
62			`.o0 ( pd0[i][j] ),`
63			`.o1 ( pd1[i][j] ),`
64			`.o2 ( pd2[i][j] ),`
65			`.o3 ( pd3[i][j] ),`
66			`.o4 ( pd4[i][j] ),`
67			`.ia ( pda[i+1][j] ),`
68			`.i0 ( pd0[i+1][j] ),`
69			`.i1 ( pd1[i+1][j] ),`
70			`.i2 ( pd2[i+1][j] ),`
71			`.i3 ( pd3[i+1][j] ),`
72			`.i4 ( pd4[i+1][j] ),`
73			`.oa ( pdan[i][j] )`
74			`);`
75			`end // block: SC`
76
77			`else // !`ifdef ENABLE_CHANNEL_SLICING
78			`pipe4 #(.DW(DW))`
79			`P (`
80			`.o0 ( pd0[i] ),`
81			`.o1 ( pd1[i] ),`
82			`.o2 ( pd2[i] ),`
83			`.o3 ( pd3[i] ),`
84			`.o4 ( pd4[i] ),`
85			`.ia ( pda[i+1] ),`
86			`.i0 ( pd0[i+1] ),`
87			`.i1 ( pd1[i+1] ),`
88			`.i2 ( pd2[i+1] ),`
89			`.i3 ( pd3[i+1] ),`
90			`.i4 ( pd4[i+1] ),`
91			`.oa ( pdan[i] )`
92			`);`
93			`endif // !`ifdef ENABLE_CHANNEL_SLICING
94			`end // block: DP`
95			`endgenerate`
96
97			`// generate the ack lines for data pipelines`
98			`generate for(i=1; i<PD; i++) begin: DPA`
99			`assign pdan[i] = rst_n ? ~(pda[i]\|pd4[i-1]) : 0;`
100			`end`
101			`endgenerate`
102
103			`// generate the input ack, add the AND gate if lookahead pipelines are used`
104			`generate`
105			`ifdef ENABLE_CHANNEL_SLICING
106			`for(j=0; j<SCN; j++) begin: SCA`
107			`ifdef ENABLE_LOOKAHEAD
108			`and ACKG (ia[j], pda[PD][j]\|pd4[PD-1][j], ian_dly[j]);`
109			`delay DLY ( .q(ian_dly[j]), .a(pdan[PD-1][j]));`
110			`else
111			`assign ia[j] = pda[PD][j]\|pd4[PD-1][j];`
112			`endif
113			`assign pdan[0][j] = (~oa[j])&rst_n;`
114			`end`
115			`else
116			`ifdef ENABLE_LOOKAHEAD
117			`and ACKG (ia, pda[PD]\|pd4[PD-1], ian_dly);`
118			`delay DLY ( .q(ian_dly), .a(pdan[PD-1]));`
119			`else
120			`assign ia = pda[PD]\|pd4[PD-1];`
121			`endif
122			`assign pdan[0] = (~oa)&rst_n;`
123			`endif // !`ifdef ENABLE_LOOKAHEAD
124			`endgenerate`
125
126			`// name change`
127			`assign pd0[PD] = i0;`
128			`assign pd1[PD] = i1;`
129			`assign pd2[PD] = i2;`
130			`assign pd3[PD] = i3;`
131			`assign pd4[PD] = i4;`
132			`assign o0 = pd0[0];`
133			`assign o1 = pd1[0];`
134			`assign o2 = pd2[0];`
135			`assign o3 = pd3[0];`
136			`assign o4 = pd4[0];`
137
138			`endmodule // outp_buf`
139

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[/] [async_sdm_noc/] [branches/] [clos_opt/] [sdm/] [src/] [output_buf.v] - Blame information for rev 14