OpenCores
URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [branches/] [clos_opt/] [vc/] [src/] [ddmux.v] - Blame information for rev 82

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 39 wsong0210
/*
2
 Asynchronous SDM NoC
3
 (C)2011 Wei Song
4
 Advanced Processor Technologies Group
5
 Computer Science, the Univ. of Manchester, UK
6
 
7
 Authors:
8
 Wei Song     wsong83@gmail.com
9
 
10
 License: LGPL 3.0 or later
11
 
12
 Demux for a 1-of-n buffer stage.
13
 
14
 History:
15
 31/03/2010  Initial version. <wsong83@gmail.com>
16
 02/06/2011  Clean up for opensource. <wsong83@gmail.com>
17 53 wsong0210
 09/06/2011  Make sure the sel pin is considered in the ack process. <wsong83@gmail.com>
18 39 wsong0210
 
19
*/
20
 
21
module ddmux ( /*AUTOARG*/
22
   // Outputs
23
   d_in_a, d_out,
24
   // Inputs
25
   d_in, d_sel, d_out_a
26
   );
27
   parameter VCN = 2;           // number of output VCs
28
   parameter DW = 32;           // data width of the input
29
 
30
   input [DW-1:0]   d_in;
31
   input [VCN-1:0]  d_sel;
32
   output           d_in_a;
33
 
34
   output [VCN-1:0][DW-1:0]  d_out;
35
   input  [VCN-1:0]           d_out_a;
36
 
37
   genvar                     i,j;
38
 
39
   /*
40
   generate
41
      for (i=0; i<VCN; i++) begin: VCD
42
         for(j=0; j<DW; j++) begin: D
43
            c2 C (.a0(d_in[j]), .a1(d_sel[i]), .q(d_out[i][j]));
44
         end
45
      end
46
   endgenerate
47
    */
48
 
49
   generate
50
      for (i=0; i<VCN; i++) begin: VCD
51
         assign d_out[i] = d_sel[i] ? d_in : 0;
52
      end
53
   endgenerate
54
 
55 53 wsong0210
   //assign d_in_a = |d_out_a;
56
   c2 CACK (.a0(|d_out_a), .a1(|d_sel), .q(d_in_a));
57 39 wsong0210
 
58
endmodule // ddmux
59
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.