OpenCores
URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [branches/] [init/] [common/] [tb/] [procelem.h] - Blame information for rev 54

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 wsong0210
/*
2
 Asynchronous SDM NoC
3
 (C)2011 Wei Song
4
 Advanced Processor Technologies Group
5
 Computer Science, the Univ. of Manchester, UK
6
 
7
 Authors:
8
 Wei Song     wsong83@gmail.com
9
 
10
 License: LGPL 3.0 or later
11
 
12
 The SystemC processing element.
13
 
14
 History:
15
 26/02/2011  Initial version. <wsong83@gmail.com>
16 33 wsong0210
 31/05/2011  Clean up for opensource. <wsong83@gmail.com>
17 30 wsong0210
 
18
*/
19
 
20
#ifndef PROCELEM_H_
21
#define PROCELEM_H_
22
 
23 32 wsong0210
#include "define.h"
24 30 wsong0210
#include <systemc.h>
25
 
26
 
27
// a function to generate random numbers comply with an exponential distribution with expection exp
28 32 wsong0210
double rand_exponential(double exp) {
29
  unsigned int rint = rand() % (unsigned int)(1e6);
30 30 wsong0210
  double rdat = rint * 1.0 / 1e6;
31 33 wsong0210
  return (-1.0 * exp * log(rdat));
32 30 wsong0210
}
33
 
34
class ProcElem : public sc_module {
35
 
36
public:
37
  sc_in<bool>  rst_n;           // active low reset
38
  sc_port<sc_fifo_out_if<FRAME> > Fout; // frame output port
39
  sc_port<sc_fifo_in_if<FRAME> > Fin;   // frame input port
40
 
41
  SC_HAS_PROCESS(ProcElem);
42
 
43
  unsigned int addrx, addry;    // the local address
44
 
45
  ProcElem(sc_module_name nm, unsigned int addrx, unsigned int addry)
46
  : sc_module(nm), addrx(addrx), addry(addry)
47
  {
48
    SC_THREAD(tproc);           // frame transmission thread
49
    SC_THREAD(rproc);           // frame receiving thread
50
  }
51
 
52
  // the transmission thread
53
  void tproc() {
54
    // waiting for reset
55
    wait(rst_n.posedge_event());
56
 
57
    while(1) {
58
      // wait for a random interval
59
      if(FFreq != 0) {
60
        double rnum = rand_exponential(1e6/FFreq);
61
        wait(rnum, SC_PS);
62
      }
63
 
64
      // generate a frame
65
      // specify the target address according to random uniform traffic
66
      unsigned int rint, tarx, tary;
67
      rint = rand()%(DIMX*DIMY-1);
68
      if(rint == addrx*DIMY + addry)
69
        rint = DIMX*DIMY-1;
70
 
71
      tarx = rint/DIMY;
72
      tary = rint%DIMY;
73
 
74
      // initialize the frame object
75
      FRAME tframe(FLEN);
76
 
77
      // fill in the fields
78
      tframe.addrx = tarx;
79
      tframe.addry = tary;
80
      for(unsigned int i=0; i<FLEN; i++)
81
        tframe.push(rand()&0xff);
82
 
83
      // specify the unique key of each frame
84
      // a key is 32 bits log
85
      // in this test bench, it is the first 4 bytes of the frame payload
86
      unsigned long key = 0;
87
      for(unsigned int i=0; (i<FLEN && i<4); i++) {
88
        key <<= 8;
89
        key |= tframe[i];
90
      }
91
 
92
      // record the new frame
93
      ANA->start(key, sc_time_stamp().to_double());
94
 
95
      // sen the frame to the router
96
      Fout->write(tframe);
97
    }
98
  }
99
 
100
  // the receiving thread
101
  void rproc() {
102
    while(1) {
103
      // initialize a space for the frame
104
      FRAME rframe;
105
 
106
      // read in the frame
107
      rframe = Fin->read();
108
      unsigned long key = 0;
109
 
110
      // regenerate the unique key
111
      for(unsigned int i=0; (i<FLEN && i<4); i++) {
112
        key <<= 8;
113
        key |= rframe[i];
114
      }
115
 
116
      // check the key in the simulation analysis database and update info.
117
      if(!ANA->stop(key, sc_time_stamp().to_double(), rframe.psize())) {
118
        // report error when no match is found
119
        cout << sc_time_stamp() << " " << name() ;
120
        cout << "packet did not find!" << endl;
121
        cout << rframe << endl;
122
        sc_stop();
123
      }
124
    }
125
  }
126
 
127
};
128
 
129
#endif
130
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.