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1 38 wsong0210
/*
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 Asynchronous SDM NoC
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 (C)2011 Wei Song
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 Advanced Processor Technologies Group
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 Computer Science, the Univ. of Manchester, UK
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 Authors:
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 Wei Song     wsong83@gmail.com
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 License: LGPL 3.0 or later
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 The full dual-rail pipeline stage for the credit fifo in VC routers.
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 It has a reset pin to feed a token into every cpipe stage.
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 History:
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 31/03/2010  Initial version. <wsong83@gmail.com>
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 01/06/2011  Clean up for opensource. <wsong83@gmail.com>
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*/
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module cpipe (/*AUTOARG*/
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   // Outputs
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   cia, co,
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   // Inputs
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   rst, ci, coa
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   );
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   input rst;                   // active high reset
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   input ci;                    // credit input
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   output cia;                  // credit input ack
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   output co;                   // credit output
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   input  coa;                  // credit output ack
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   wire   c0, c1;               // internal wires
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   dc2 C0 ( .d(ci), .a(~c1), .q(c0));
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   dc2 C1 ( .d(c0|rst), .a((~coa)|rst), .q(c1));
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   assign co = (~rst)&c1;
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   assign cia = c0;
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endmodule // cpipe

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