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Line No. Rev Author Line
1 6 wsong0210 
// A synthesizable cell library for asynchronous logic
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// author Wei Song, songw@cs.man.ac.uk
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// the Advanced Processor Technology Group
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// the School of Computer Science
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// the Uniersity of Manchester
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// 5th May, 2009
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// a latch is added, 11/08/2010 songw@cs.man.ac.uk
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module c2 (
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     a0
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    ,a1
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    ,q
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    );
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input a0;
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input a1;
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output q;
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AO222EHD U1 ( .A1(q), .A2(a0), .B1(q), .B2(a1), .C1(a0), .C2(a1), .O(q) );
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endmodule
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// the dc2 cell for Faraday 130nm Tech
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module dc2 (
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     d
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    ,a
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    ,q
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    );
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input d;
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input a;
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output q;
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AO222HHD U1 ( .A1(q), .A2(d), .B1(q), .B2(a), .C1(d), .C2(a), .O(q) );
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endmodule // dc2
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module c2n (
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     a0
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    ,a1
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    ,q
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    );
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input a0;
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input a1;
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output q;
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   AO12EHD U1 (.B1(a1), .B2(q), .A1(a0), .O(q));
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endmodule
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module c2p (
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     a0
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    ,a1
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    ,q
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    );
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input a0;
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input a1;
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output q;
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OA12EHD U1 ( .B1(a1), .B2(q), .A1(a0), .O(q) );
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endmodule
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// for Faraday
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module mutex ( a, b, qa, qb );
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input a, b;
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output qa, qb;
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wire   qan, qbn;
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ND2HHD U1 ( .I1(a), .I2(qbn), .O(qan) );
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NR3HHD U2 ( .I1(qbn), .I2(qbn), .I3(qbn), .O(qb) );
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NR3HHD U3 ( .I1(qan), .I2(qan), .I3(qan), .O(qa) );
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ND2KHD U4 ( .I1(b), .I2(qan), .O(qbn) );
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endmodule
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module c2p1 (
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             a0,
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             a1,
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             b,
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             q
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             );
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   input a0, a1, b;
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   output q;
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  wire   n1;
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  OA12EHD U2 ( .B1(a1), .B2(a0), .A1(q), .O(n1) );
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  AO13EHD U1 ( .B1(a1), .B2(a0), .B3(b), .A1(n1), .O(q) );
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//assign q = (a0&a1&b)|(a0&q)|(b0&q);
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endmodule // c2p1
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module tarb ( ngnt, ntgnt, req, treq );
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  output [1:0] ngnt;
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  input [1:0] req;
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  input ntgnt;
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  output treq;
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  wire   n1, n2;
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  wire   [1:0] mgnt;
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  mutex ME ( .a(req[0]), .b(req[1]), .qa(mgnt[0]), .qb(mgnt[1]) );
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  c2n C0 ( .a0(ntgnt), .a1(n2), .q(ngnt[0]) );
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  c2n C1 ( .a0(ntgnt), .a1(n1), .q(ngnt[1]) );
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  ND2HHD U1 ( .I1(n1), .I2(n2), .O(treq) );
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  ND2DHD U2 ( .I1(ngnt[0]), .I2(mgnt[1]), .O(n1) );
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  ND2DHD U3 ( .I1(ngnt[1]), .I2(mgnt[0]), .O(n2) );
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endmodule
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module cr_blk ( bo, hs, cbi, rbi, rg, cg );
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  input cbi, rbi, rg, cg;
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  output bo, hs;
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  wire   blk;
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  c2p1 XG ( .a0(rg), .a1(cg), .b(blk), .q(bo) );
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  c2p1 HG ( .a0(cbi), .a1(rbi), .b(bo), .q(hs) );
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  NR2EHD U1 ( .I1(rbi), .I2(cbi), .O(blk) );
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endmodule
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module dlatch ( q, qb, d, g);
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   output q, qb;
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   input  d, g;
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   DLAHEHD U1 (.Q(q), .QB(qb), .D(d), .G(g));
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endmodule // dlatch
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module delay (q, a);
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   input a;
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   output q;
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   BUFKHD U (.O(q), .I(a));
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endmodule // delay
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