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1 12 wsong0210 
/*
2 
 Asynchronous SDM NoC
3 
 (C)2011 Wei Song
4 
 Advanced Processor Technologies Group
5 
 Computer Science, the Univ. of Manchester, UK
6 
 
7 
 Authors:
8 
 Wei Song     wsong83@gmail.com
9 
 
10 
 License: LGPL 3.0 or later
11 
 
12 
 Data crossbar for wormhole and SDM routers.
13 
 Optimized by removing disabled turn models according to the XY routing algorithm.
14 
 *** SystemVerilog is used ***
15 
 
16 
 History:
17 
 21/08/2009  Initial version. <wsong83@gmail.com>
18 
 20/09/2010  Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
19 
 23/05/2011  Clean up for opensource. <wsong83@gmail.com>
20 
 
21 
*/
22 
 
23 
// the router structure definitions
24 
`include "define.v"
25 
 
26 
module dcb_xy (/*AUTOARG*/
27 
   // Outputs
28 
   so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
29 
   eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, sia, wo4, wia, no4, nia,
30 
   eo4, eia, lo4, lia,
31 
   // Inputs
32 
   si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
33 
   ei1, ei2, ei3, li0, li1, li2, li3, si4, soa, wi4, woa, ni4, noa,
34 
   ei4, eoa, li4, loa, scfg, ncfg, wcfg, ecfg, lcfg
35 
   ) ;
36 
 
37 
   parameter VCN = 1;           // number of virtual circuits per port
38 
   parameter VCW = 8;           // the datawidth of a single virtual circuit
39 
   parameter SCN = VCW/2;       // number of 1-of-4 sub-channels in one virtual circuit
40 
 
41 
   input [VCN-1:0][SCN-1:0]    si0, si1, si2, si3; // south input, X+1
42 
   output [VCN-1:0][SCN-1:0]   so0, so1, so2, so3; // south output
43 
   input [VCN-1:0][SCN-1:0]    wi0, wi1, wi2, wi3; // west input, Y-1
44 
   output [VCN-1:0][SCN-1:0]   wo0, wo1, wo2, wo3; // west output
45 
   input [VCN-1:0][SCN-1:0]    ni0, ni1, ni2, ni3; // north input, X-1
46 
   output [VCN-1:0][SCN-1:0]   no0, no1, no2, no3; // north output
47 
   input [VCN-1:0][SCN-1:0]    ei0, ei1, ei2, ei3; // east input, Y+1
48 
   output [VCN-1:0][SCN-1:0]   eo0, eo1, eo2, eo3; // east output
49 
   input [VCN-1:0][SCN-1:0]    li0, li1, li2, li3; // local input
50 
   output [VCN-1:0][SCN-1:0]   lo0, lo1, lo2, lo3; // local output
51 
 
52 
   // ack and eof bits
53 
`ifdef ENABLE_CHANNEL_SLICING
54 
   input [VCN-1:0][SCN-1:0]    si4, soa;
55 
   output [VCN-1:0][SCN-1:0]   so4, sia;
56 
   input [VCN-1:0][SCN-1:0]    wi4, woa;
57 
   output [VCN-1:0][SCN-1:0]   wo4, wia;
58 
   input [VCN-1:0][SCN-1:0]    ni4, noa;
59 
   output [VCN-1:0][SCN-1:0]   no4, nia;
60 
   input [VCN-1:0][SCN-1:0]    ei4, eoa;
61 
   output [VCN-1:0][SCN-1:0]   eo4, eia;
62 
   input [VCN-1:0][SCN-1:0]    li4, loa;
63 
   output [VCN-1:0][SCN-1:0]   lo4, lia;
64 
`else // !`ifdef ENABLE_CHANNEL_SLICING
65 
   input [VCN-1:0]              si4, soa;
66 
   output [VCN-1:0]             so4, sia;
67 
   input [VCN-1:0]              wi4, woa;
68 
   output [VCN-1:0]             wo4, wia;
69 
   input [VCN-1:0]              ni4, noa;
70 
   output [VCN-1:0]             no4, nia;
71 
   input [VCN-1:0]              ei4, eoa;
72 
   output [VCN-1:0]             eo4, eia;
73 
   input [VCN-1:0]              li4, loa;
74 
   output [VCN-1:0]             lo4, lia;
75 
`endif
76 
 
77 
   // configurations
78 
   input [VCN-1:0][1:0][VCN-1:0]        scfg, ncfg;
79 
   input [VCN-1:0][3:0][VCN-1:0]        wcfg, ecfg, lcfg;
80 
 
81 
 
82 
   // ANDed wires
83 
   wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] tos0, tos1, tos2, tos3;     // the wires to the south output port
84 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] tow0, tow1, tow2, tow3;     // the wires to the west output port
85 
   wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] ton0, ton1, ton2, ton3;     // the wires to the north output port
86 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] toe0, toe1, toe2, toe3;     // the wires to the east output port
87 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] tol0, tol1, tol2, tol3;     // the wires to the local output port
88 
 
89 
`ifdef ENABLE_CHANNEL_SLICING
90 
   wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] tos4, tosa;                 // the wires to the south output port
91 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] tow4, towa;                 // the wires to the west output port
92 
   wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] ton4, tona;                 // the wires to the north output port
93 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] toe4, toea;                 // the wires to the east output port
94 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] tol4, tola;                 // the wires to the local output port
95 
 
96 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] isa;                        // ack back to south
97 
   wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] iwa;                        // ack back to west
98 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] ina;                        // ack back to north
99 
   wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] iea;                        // ack back to east
100 
   wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] ila;                        // ack back to local
101 
 
102 
`else // !`ifdef ENABLE_CHANNEL_SLICING
103 
   wire [VCN-1:0][1:0][VCN-1:0] tos4, tosa;                 // the wires to the south output port
104 
   wire [VCN-1:0][3:0][VCN-1:0] tow4, towa;                 // the wires to the west output port
105 
   wire [VCN-1:0][1:0][VCN-1:0] ton4, tona;                 // the wires to the north output port
106 
   wire [VCN-1:0][3:0][VCN-1:0] toe4, toea;                 // the wires to the east output port
107 
   wire [VCN-1:0][3:0][VCN-1:0] tol4, tola;                 // the wires to the local output port
108 
 
109 
   wire [VCN-1:0][3:0][VCN-1:0] isa;                        // ack back to south
110 
   wire [VCN-1:0][1:0][VCN-1:0] iwa;                        // ack back to west
111 
   wire [VCN-1:0][3:0][VCN-1:0] ina;                        // ack back to north
112 
   wire [VCN-1:0][1:0][VCN-1:0] iea;                        // ack back to east
113 
   wire [VCN-1:0][3:0][VCN-1:0] ila;                        // ack back to local
114 
 
115 
`endif // !`ifdef ENABLE_CHANNEL_SLICING
116 
 
117 
   // generate
118 
   genvar                     i, j, k;
119 
 
120 
 
121 
   /*---------------------------- SOUTH OUPUT -------------------------------------*/
122 
   generate for (i=0; i<VCN; i=i+1)
123 
     begin:SOP
124 
        for(j=0; j<VCN; j++) begin: V
125 
           for(k=0; k<SCN; k++) begin: SC
126 
              and AN0 (tos0[i][k][0][j], ni0[j][k], scfg[i][0][j]);
127 
              and AN1 (tos1[i][k][0][j], ni1[j][k], scfg[i][0][j]);
128 
              and AN2 (tos2[i][k][0][j], ni2[j][k], scfg[i][0][j]);
129 
              and AN3 (tos3[i][k][0][j], ni3[j][k], scfg[i][0][j]);
130 
              and AL0 (tos0[i][k][1][j], li0[j][k], scfg[i][1][j]);
131 
              and AL1 (tos1[i][k][1][j], li1[j][k], scfg[i][1][j]);
132 
              and AL2 (tos2[i][k][1][j], li2[j][k], scfg[i][1][j]);
133 
              and AL3 (tos3[i][k][1][j], li3[j][k], scfg[i][1][j]);
134 
`ifdef ENABLE_CHANNEL_SLICING
135 
              and AN4 (tos4[i][k][0][j], ni4[j][k], scfg[i][0][j]);
136 
              and ANA (tosa[i][k][0][j], soa[i][k], scfg[i][0][j]);
137 
              and AL4 (tos4[i][k][1][j], li4[j][k], scfg[i][1][j]);
138 
              and ALA (tosa[i][k][1][j], soa[i][k], scfg[i][1][j]);
139 
`endif
140 
           end // block: SC
141 
`ifndef ENABLE_CHANNEL_SLICING
142 
           and AN4 (tos4[i][0][j], ni4[j], scfg[i][0][j]);
143 
           and ANA (tosa[i][0][j], soa[i], scfg[i][0][j]);
144 
           and AL4 (tos4[i][1][j], li4[j], scfg[i][1][j]);
145 
           and ALA (tosa[i][1][j], soa[i], scfg[i][1][j]);
146 
`endif
147 
        end // block: V
148 
 
149 
        for(k=0; k<SCN; k++) begin: SCOR
150 
           assign so0[i][k] = |(tos0[i][k][0]|tos0[i][k][1]);
151 
           assign so1[i][k] = |(tos1[i][k][0]|tos1[i][k][1]);
152 
           assign so2[i][k] = |(tos2[i][k][0]|tos2[i][k][1]);
153 
           assign so3[i][k] = |(tos3[i][k][0]|tos3[i][k][1]);
154 
`ifdef ENABLE_CHANNEL_SLICING
155 
           assign so4[i][k] = |(tos4[i][k][0]|tos4[i][k][1]);
156 
`endif
157 
        end
158 
`ifndef ENABLE_CHANNEL_SLICING
159 
        assign so4[i] = |(tos4[i][0]|tos4[i][1]);
160 
`endif
161 
     end
162 
   endgenerate
163 
 
164 
   /*---------------------------- WEST OUPUT -------------------------------------*/
165 
   generate for (i=0; i<VCN; i=i+1)
166 
     begin:WOP
167 
        for(j=0; j<VCN; j++) begin: V
168 
           for(k=0; k<SCN; k++) begin: SC
169 
              and AS0 (tow0[i][k][0][j], si0[j][k], wcfg[i][0][j]);
170 
              and AS1 (tow1[i][k][0][j], si1[j][k], wcfg[i][0][j]);
171 
              and AS2 (tow2[i][k][0][j], si2[j][k], wcfg[i][0][j]);
172 
              and AS3 (tow3[i][k][0][j], si3[j][k], wcfg[i][0][j]);
173 
              and AN0 (tow0[i][k][1][j], ni0[j][k], wcfg[i][1][j]);
174 
              and AN1 (tow1[i][k][1][j], ni1[j][k], wcfg[i][1][j]);
175 
              and AN2 (tow2[i][k][1][j], ni2[j][k], wcfg[i][1][j]);
176 
              and AN3 (tow3[i][k][1][j], ni3[j][k], wcfg[i][1][j]);
177 
              and AE0 (tow0[i][k][2][j], ei0[j][k], wcfg[i][2][j]);
178 
              and AE1 (tow1[i][k][2][j], ei1[j][k], wcfg[i][2][j]);
179 
              and AE2 (tow2[i][k][2][j], ei2[j][k], wcfg[i][2][j]);
180 
              and AE3 (tow3[i][k][2][j], ei3[j][k], wcfg[i][2][j]);
181 
              and AL0 (tow0[i][k][3][j], li0[j][k], wcfg[i][3][j]);
182 
              and AL1 (tow1[i][k][3][j], li1[j][k], wcfg[i][3][j]);
183 
              and AL2 (tow2[i][k][3][j], li2[j][k], wcfg[i][3][j]);
184 
              and AL3 (tow3[i][k][3][j], li3[j][k], wcfg[i][3][j]);
185 
`ifdef ENABLE_CHANNEL_SLICING
186 
              and AS4 (tow4[i][k][0][j], si4[j][k], wcfg[i][0][j]);
187 
              and ASA (towa[i][k][0][j], woa[i][k], wcfg[i][0][j]);
188 
              and AN4 (tow4[i][k][1][j], ni4[j][k], wcfg[i][1][j]);
189 
              and ANA (towa[i][k][1][j], woa[i][k], wcfg[i][1][j]);
190 
              and AE4 (tow4[i][k][2][j], ei4[j][k], wcfg[i][2][j]);
191 
              and AEA (towa[i][k][2][j], woa[i][k], wcfg[i][2][j]);
192 
              and AL4 (tow4[i][k][3][j], li4[j][k], wcfg[i][3][j]);
193 
              and ALA (towa[i][k][3][j], woa[i][k], wcfg[i][3][j]);
194 
`endif
195 
           end // block: SC
196 
`ifndef ENABLE_CHANNEL_SLICING
197 
           and AS4 (tow4[i][0][j], si4[j], wcfg[i][0][j]);
198 
           and ASA (towa[i][0][j], woa[i], wcfg[i][0][j]);
199 
           and AN4 (tow4[i][1][j], ni4[j], wcfg[i][1][j]);
200 
           and ANA (towa[i][1][j], woa[i], wcfg[i][1][j]);
201 
           and AE4 (tow4[i][2][j], ei4[j], wcfg[i][2][j]);
202 
           and AEA (towa[i][2][j], woa[i], wcfg[i][2][j]);
203 
           and AL4 (tow4[i][3][j], li4[j], wcfg[i][3][j]);
204 
           and ALA (towa[i][3][j], woa[i], wcfg[i][3][j]);
205 
`endif
206 
        end // block: V
207 
 
208 
        for(k=0; k<SCN; k++) begin: SCOR
209 
           assign wo0[i][k] = |(tow0[i][k][0]|tow0[i][k][1]|tow0[i][k][2]|tow0[i][k][3]);
210 
           assign wo1[i][k] = |(tow1[i][k][0]|tow1[i][k][1]|tow1[i][k][2]|tow1[i][k][3]);
211 
           assign wo2[i][k] = |(tow2[i][k][0]|tow2[i][k][1]|tow2[i][k][2]|tow2[i][k][3]);
212 
           assign wo3[i][k] = |(tow3[i][k][0]|tow3[i][k][1]|tow3[i][k][2]|tow3[i][k][3]);
213 
`ifdef ENABLE_CHANNEL_SLICING
214 
           assign wo4[i][k] = |(tow4[i][k][0]|tow4[i][k][1]|tow4[i][k][2]|tow4[i][k][3]);
215 
`endif
216 
        end
217 
`ifndef ENABLE_CHANNEL_SLICING
218 
        assign wo4[i] = |(tow4[i][0]|tow4[i][1]|tow4[i][2]|tow4[i][3]);
219 
`endif
220 
     end
221 
   endgenerate
222 
 
223 
   /*---------------------------- NORTH OUPUT -------------------------------------*/
224 
   generate for (i=0; i<VCN; i=i+1)
225 
     begin:NOP
226 
        for(j=0; j<VCN; j++) begin: V
227 
           for(k=0; k<SCN; k++) begin: SC
228 
              and AS0 (ton0[i][k][0][j], si0[j][k], ncfg[i][0][j]);
229 
              and AS1 (ton1[i][k][0][j], si1[j][k], ncfg[i][0][j]);
230 
              and AS2 (ton2[i][k][0][j], si2[j][k], ncfg[i][0][j]);
231 
              and AS3 (ton3[i][k][0][j], si3[j][k], ncfg[i][0][j]);
232 
              and AL0 (ton0[i][k][1][j], li0[j][k], ncfg[i][1][j]);
233 
              and AL1 (ton1[i][k][1][j], li1[j][k], ncfg[i][1][j]);
234 
              and AL2 (ton2[i][k][1][j], li2[j][k], ncfg[i][1][j]);
235 
              and AL3 (ton3[i][k][1][j], li3[j][k], ncfg[i][1][j]);
236 
`ifdef ENABLE_CHANNEL_SLICING
237 
              and AS4 (ton4[i][k][0][j], si4[j][k], ncfg[i][0][j]);
238 
              and ASA (tona[i][k][0][j], noa[i][k], ncfg[i][0][j]);
239 
              and AL4 (ton4[i][k][1][j], li4[j][k], ncfg[i][1][j]);
240 
              and ALA (tona[i][k][1][j], noa[i][k], ncfg[i][1][j]);
241 
`endif
242 
           end // block: SC
243 
`ifndef ENABLE_CHANNEL_SLICING
244 
           and AS4 (ton4[i][0][j], si4[j], ncfg[i][0][j]);
245 
           and ASA (tona[i][0][j], noa[i], ncfg[i][0][j]);
246 
           and AL4 (ton4[i][1][j], li4[j], ncfg[i][1][j]);
247 
           and ALA (tona[i][1][j], noa[i], ncfg[i][1][j]);
248 
`endif
249 
        end // block: V
250 
 
251 
        for(k=0; k<SCN; k++) begin: SCOR
252 
           assign no0[i][k] = |(ton0[i][k][0]|ton0[i][k][1]);
253 
           assign no1[i][k] = |(ton1[i][k][0]|ton1[i][k][1]);
254 
           assign no2[i][k] = |(ton2[i][k][0]|ton2[i][k][1]);
255 
           assign no3[i][k] = |(ton3[i][k][0]|ton3[i][k][1]);
256 
`ifdef ENABLE_CHANNEL_SLICING
257 
           assign no4[i][k] = |(ton4[i][k][0]|ton4[i][k][1]);
258 
`endif
259 
        end
260 
`ifndef ENABLE_CHANNEL_SLICING
261 
        assign no4[i] = |(ton4[i][0]|ton4[i][1]);
262 
`endif
263 
     end
264 
   endgenerate
265 
 
266 
   /*---------------------------- EAST OUPUT -------------------------------------*/
267 
   generate for (i=0; i<VCN; i=i+1)
268 
     begin:EOP
269 
        for(j=0; j<VCN; j++) begin: V
270 
           for(k=0; k<SCN; k++) begin: SC
271 
              and AS0 (toe0[i][k][0][j], si0[j][k], ecfg[i][0][j]);
272 
              and AS1 (toe1[i][k][0][j], si1[j][k], ecfg[i][0][j]);
273 
              and AS2 (toe2[i][k][0][j], si2[j][k], ecfg[i][0][j]);
274 
              and AS3 (toe3[i][k][0][j], si3[j][k], ecfg[i][0][j]);
275 
              and AW0 (toe0[i][k][1][j], wi0[j][k], ecfg[i][1][j]);
276 
              and AW1 (toe1[i][k][1][j], wi1[j][k], ecfg[i][1][j]);
277 
              and AW2 (toe2[i][k][1][j], wi2[j][k], ecfg[i][1][j]);
278 
              and AW3 (toe3[i][k][1][j], wi3[j][k], ecfg[i][1][j]);
279 
              and AN0 (toe0[i][k][2][j], ni0[j][k], ecfg[i][2][j]);
280 
              and AN1 (toe1[i][k][2][j], ni1[j][k], ecfg[i][2][j]);
281 
              and AN2 (toe2[i][k][2][j], ni2[j][k], ecfg[i][2][j]);
282 
              and AN3 (toe3[i][k][2][j], ni3[j][k], ecfg[i][2][j]);
283 
              and AL0 (toe0[i][k][3][j], li0[j][k], ecfg[i][3][j]);
284 
              and AL1 (toe1[i][k][3][j], li1[j][k], ecfg[i][3][j]);
285 
              and AL2 (toe2[i][k][3][j], li2[j][k], ecfg[i][3][j]);
286 
              and AL3 (toe3[i][k][3][j], li3[j][k], ecfg[i][3][j]);
287 
`ifdef ENABLE_CHANNEL_SLICING
288 
              and AS4 (toe4[i][k][0][j], si4[j][k], ecfg[i][0][j]);
289 
              and ASA (toea[i][k][0][j], eoa[i][k], ecfg[i][0][j]);
290 
              and AW4 (toe4[i][k][1][j], wi4[j][k], ecfg[i][1][j]);
291 
              and AWA (toea[i][k][1][j], eoa[i][k], ecfg[i][1][j]);
292 
              and AN4 (toe4[i][k][2][j], ni4[j][k], ecfg[i][2][j]);
293 
              and ANA (toea[i][k][2][j], eoa[i][k], ecfg[i][2][j]);
294 
              and AL4 (toe4[i][k][3][j], li4[j][k], ecfg[i][3][j]);
295 
              and ALA (toea[i][k][3][j], eoa[i][k], ecfg[i][3][j]);
296 
`endif
297 
           end // block: SC
298 
`ifndef ENABLE_CHANNEL_SLICING
299 
           and AS4 (toe4[i][0][j], si4[j], ecfg[i][0][j]);
300 
           and ASA (toea[i][0][j], eoa[i], ecfg[i][0][j]);
301 
           and AW4 (toe4[i][1][j], wi4[j], ecfg[i][1][j]);
302 
           and AWA (toea[i][1][j], eoa[i], ecfg[i][1][j]);
303 
           and AN4 (toe4[i][2][j], ni4[j], ecfg[i][2][j]);
304 
           and ANA (toea[i][2][j], eoa[i], ecfg[i][2][j]);
305 
           and AL4 (toe4[i][3][j], li4[j], ecfg[i][3][j]);
306 
           and ALA (toea[i][3][j], eoa[i], ecfg[i][3][j]);
307 
`endif
308 
        end // block: V
309 
 
310 
        for(k=0; k<SCN; k++) begin: SCOR
311 
           assign eo0[i][k] = |(toe0[i][k][0]|toe0[i][k][1]|toe0[i][k][2]|toe0[i][k][3]);
312 
           assign eo1[i][k] = |(toe1[i][k][0]|toe1[i][k][1]|toe1[i][k][2]|toe1[i][k][3]);
313 
           assign eo2[i][k] = |(toe2[i][k][0]|toe2[i][k][1]|toe2[i][k][2]|toe2[i][k][3]);
314 
           assign eo3[i][k] = |(toe3[i][k][0]|toe3[i][k][1]|toe3[i][k][2]|toe3[i][k][3]);
315 
`ifdef ENABLE_CHANNEL_SLICING
316 
           assign eo4[i][k] = |(toe4[i][k][0]|toe4[i][k][1]|toe4[i][k][2]|toe4[i][k][3]);
317 
`endif
318 
        end
319 
`ifndef ENABLE_CHANNEL_SLICING
320 
        assign eo4[i] = |(toe4[i][0]|toe4[i][1]|toe4[i][2]|toe4[i][3]);
321 
`endif
322 
     end
323 
   endgenerate
324 
 
325 
 
326 
   /*---------------------------- LOCAL OUPUT -------------------------------------*/
327 
   generate for (i=0; i<VCN; i=i+1)
328 
     begin:LOP
329 
        for(j=0; j<VCN; j++) begin: V
330 
           for(k=0; k<SCN; k++) begin: SC
331 
              and AS0 (tol0[i][k][0][j], si0[j][k], lcfg[i][0][j]);
332 
              and AS1 (tol1[i][k][0][j], si1[j][k], lcfg[i][0][j]);
333 
              and AS2 (tol2[i][k][0][j], si2[j][k], lcfg[i][0][j]);
334 
              and AS3 (tol3[i][k][0][j], si3[j][k], lcfg[i][0][j]);
335 
              and AW0 (tol0[i][k][1][j], wi0[j][k], lcfg[i][1][j]);
336 
              and AW1 (tol1[i][k][1][j], wi1[j][k], lcfg[i][1][j]);
337 
              and AW2 (tol2[i][k][1][j], wi2[j][k], lcfg[i][1][j]);
338 
              and AW3 (tol3[i][k][1][j], wi3[j][k], lcfg[i][1][j]);
339 
              and AN0 (tol0[i][k][2][j], ni0[j][k], lcfg[i][2][j]);
340 
              and AN1 (tol1[i][k][2][j], ni1[j][k], lcfg[i][2][j]);
341 
              and AN2 (tol2[i][k][2][j], ni2[j][k], lcfg[i][2][j]);
342 
              and AN3 (tol3[i][k][2][j], ni3[j][k], lcfg[i][2][j]);
343 
              and AE0 (tol0[i][k][3][j], ei0[j][k], lcfg[i][3][j]);
344 
              and AE1 (tol1[i][k][3][j], ei1[j][k], lcfg[i][3][j]);
345 
              and AE2 (tol2[i][k][3][j], ei2[j][k], lcfg[i][3][j]);
346 
              and AE3 (tol3[i][k][3][j], ei3[j][k], lcfg[i][3][j]);
347 
`ifdef ENABLE_CHANNEL_SLICING
348 
              and AS4 (tol4[i][k][0][j], si4[j][k], lcfg[i][0][j]);
349 
              and ASA (tola[i][k][0][j], loa[i][k], lcfg[i][0][j]);
350 
              and AW4 (tol4[i][k][1][j], wi4[j][k], lcfg[i][1][j]);
351 
              and AWA (tola[i][k][1][j], loa[i][k], lcfg[i][1][j]);
352 
              and AN4 (tol4[i][k][2][j], ni4[j][k], lcfg[i][2][j]);
353 
              and ANA (tola[i][k][2][j], loa[i][k], lcfg[i][2][j]);
354 
              and AE4 (tol4[i][k][3][j], ei4[j][k], lcfg[i][3][j]);
355 
              and AEA (tola[i][k][3][j], loa[i][k], lcfg[i][3][j]);
356 
`endif
357 
           end // block: SC
358 
`ifndef ENABLE_CHANNEL_SLICING
359 
           and AS4 (tol4[i][0][j], si4[j], lcfg[i][0][j]);
360 
           and ASA (tola[i][0][j], loa[i], lcfg[i][0][j]);
361 
           and AW4 (tol4[i][1][j], wi4[j], lcfg[i][1][j]);
362 
           and AWA (tola[i][1][j], loa[i], lcfg[i][1][j]);
363 
           and AN4 (tol4[i][2][j], ni4[j], lcfg[i][2][j]);
364 
           and ANA (tola[i][2][j], loa[i], lcfg[i][2][j]);
365 
           and AE4 (tol4[i][3][j], ei4[j], lcfg[i][3][j]);
366 
           and AEA (tola[i][3][j], loa[i], lcfg[i][3][j]);
367 
`endif
368 
        end // block: V
369 
 
370 
        for(k=0; k<SCN; k++) begin: SCOR
371 
           assign lo0[i][k] = |(tol0[i][k][0]|tol0[i][k][1]|tol0[i][k][2]|tol0[i][k][3]);
372 
           assign lo1[i][k] = |(tol1[i][k][0]|tol1[i][k][1]|tol1[i][k][2]|tol1[i][k][3]);
373 
           assign lo2[i][k] = |(tol2[i][k][0]|tol2[i][k][1]|tol2[i][k][2]|tol2[i][k][3]);
374 
           assign lo3[i][k] = |(tol3[i][k][0]|tol3[i][k][1]|tol3[i][k][2]|tol3[i][k][3]);
375 
`ifdef ENABLE_CHANNEL_SLICING
376 
           assign lo4[i][k] = |(tol4[i][k][0]|tol4[i][k][1]|tol4[i][k][2]|tol4[i][k][3]);
377 
`endif
378 
        end
379 
`ifndef ENABLE_CHANNEL_SLICING
380 
        assign lo4[i] = |(tol4[i][0]|tol4[i][1]|tol4[i][2]|tol4[i][3]);
381 
`endif
382 
     end
383 
   endgenerate
384 
 
385 
   generate for(i=0; i<VCN; i++) begin: IACK
386 
`ifdef ENABLE_CHANNEL_SLICING
387 
      for(k=0; k<SCN; k++) begin: SC
388 
         for(j=0; j<VCN; j++) begin: SHUFFLE
389 
            assign isa[i][k][0][j] = towa[j][k][0][i];
390 
            assign isa[i][k][1][j] = tona[j][k][0][i];
391 
            assign isa[i][k][2][j] = toea[j][k][0][i];
392 
            assign isa[i][k][3][j] = tola[j][k][0][i];
393 
            assign iwa[i][k][0][j] = toea[j][k][1][i];
394 
            assign iwa[i][k][1][j] = tola[j][k][1][i];
395 
            assign ina[i][k][0][j] = tosa[j][k][0][i];
396 
            assign ina[i][k][1][j] = towa[j][k][1][i];
397 
            assign ina[i][k][2][j] = toea[j][k][2][i];
398 
            assign ina[i][k][3][j] = tola[j][k][2][i];
399 
            assign iea[i][k][0][j] = towa[j][k][2][i];
400 
            assign iea[i][k][1][j] = tola[j][k][3][i];
401 
            assign ila[i][k][0][j] = tosa[j][k][1][i];
402 
            assign ila[i][k][1][j] = towa[j][k][3][i];
403 
            assign ila[i][k][2][j] = tona[j][k][1][i];
404 
            assign ila[i][k][3][j] = toea[j][k][3][i];
405 
         end // block: SHUFFLE
406 
         assign sia[i][k] = |{isa[i][k][0]|isa[i][k][1]|isa[i][k][2]|isa[i][k][3]};
407 
         assign wia[i][k] = |{iwa[i][k][0]|iwa[i][k][1]};
408 
         assign nia[i][k] = |{ina[i][k][0]|ina[i][k][1]|ina[i][k][2]|ina[i][k][3]};
409 
         assign eia[i][k] = |{iea[i][k][0]|iea[i][k][1]};
410 
         assign lia[i][k] = |{ila[i][k][0]|ila[i][k][1]|ila[i][k][2]|ila[i][k][3]};
411 
      end // block: SC
412 
`else // !`ifdef ENABLE_CHANNEL_SLICING
413 
      for(j=0; j<VCN; j++) begin: SHUFFLE
414 
         assign isa[i][0][j] = towa[j][0][i];
415 
         assign isa[i][1][j] = tona[j][0][i];
416 
         assign isa[i][2][j] = toea[j][0][i];
417 
         assign isa[i][3][j] = tola[j][0][i];
418 
         assign iwa[i][0][j] = toea[j][1][i];
419 
         assign iwa[i][1][j] = tola[j][1][i];
420 
         assign ina[i][0][j] = tosa[j][0][i];
421 
         assign ina[i][1][j] = towa[j][1][i];
422 
         assign ina[i][2][j] = toea[j][2][i];
423 
         assign ina[i][3][j] = tola[j][2][i];
424 
         assign iea[i][0][j] = towa[j][2][i];
425 
         assign iea[i][1][j] = tola[j][3][i];
426 
         assign ila[i][0][j] = tosa[j][1][i];
427 
         assign ila[i][1][j] = towa[j][3][i];
428 
         assign ila[i][2][j] = tona[j][1][i];
429 
         assign ila[i][3][j] = toea[j][3][i];
430 
      end // block: SHUFFLE
431 
      assign sia[i] = |{isa[i][0]|isa[i][1]|isa[i][2]|isa[i][3]};
432 
      assign wia[i] = |{iwa[i][0]|iwa[i][1]};
433 
      assign nia[i] = |{ina[i][0]|ina[i][1]|ina[i][2]|ina[i][3]};
434 
      assign eia[i] = |{iea[i][0]|iea[i][1]};
435 
      assign lia[i] = |{ila[i][0]|ila[i][1]|ila[i][2]|ila[i][3]};
436 
`endif
437 
   end // block: IACK
438 
   endgenerate
439 
 
440 
endmodule // dcb_xy
441 
 
442 
 
443 
 

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