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[/] [async_sdm_noc/] [trunk/] [lib/] [NangateOpenCellLibrary_typical_conditional.v] - Blame information for rev 22

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1	7	wsong0210	`//`
2			`// ******************************************************************************`
3			`// * *`
4			`// * Copyright (C) 2004-2009, Nangate Inc. *`
5			`// * All rights reserved. *`
6			`// * *`
7			`// * Nangate and the Nangate logo are trademarks of Nangate Inc. *`
8			`// * *`
9			`// * All trademarks, logos, software marks, and trade names (collectively the *`
10			`// * "Marks") in this program are proprietary to Nangate or other respective *`
11			`// * owners that have granted Nangate the right and license to use such Marks. *`
12			`// * You are not permitted to use the Marks without the prior written consent *`
13			`// * of Nangate or such third party that may own the Marks. *`
14			`// * *`
15			`// * This file has been provided pursuant to a License Agreement containing *`
16			`// * restrictions on its use. This file contains valuable trade secrets and *`
17			`// * proprietary information of Nangate Inc., and is protected by U.S. and *`
18			`// * international laws and/or treaties. *`
19			`// * *`
20			`// * The copyright notice(s) in this file does not indicate actual or intended *`
21			`// * publication of this file. *`
22			`// * *`
23			`// * NGLibraryCharacterizer, v2009.07-HR28-2009-07-08 - build 200907162109 *`
24			`// * *`
25			`// ******************************************************************************`
26
27			`module AND2_X1 (A1, A2, ZN);`
28
29			`input A1;`
30			`input A2;`
31			`output ZN;`
32
33			`and(ZN, A1, A2);`
34
35			`specify`
36			`(A1 => ZN) = (0.1, 0.1);`
37			`(A2 => ZN) = (0.1, 0.1);`
38			`endspecify`
39
40			`endmodule`
41
42			`module AND2_X2 (A1, A2, ZN);`
43
44			`input A1;`
45			`input A2;`
46			`output ZN;`
47
48			`and(ZN, A1, A2);`
49
50			`specify`
51			`(A1 => ZN) = (0.1, 0.1);`
52			`(A2 => ZN) = (0.1, 0.1);`
53			`endspecify`
54
55			`endmodule`
56
57			`module AND2_X4 (A1, A2, ZN);`
58
59			`input A1;`
60			`input A2;`
61			`output ZN;`
62
63			`and(ZN, A1, A2);`
64
65			`specify`
66			`(A1 => ZN) = (0.1, 0.1);`
67			`(A2 => ZN) = (0.1, 0.1);`
68			`endspecify`
69
70			`endmodule`
71
72			`module AND3_X1 (A1, A2, A3, ZN);`
73
74			`input A1;`
75			`input A2;`
76			`input A3;`
77			`output ZN;`
78
79			`and(ZN, i_66, A3);`
80			`and(i_66, A1, A2);`
81
82			`specify`
83			`(A1 => ZN) = (0.1, 0.1);`
84			`(A2 => ZN) = (0.1, 0.1);`
85			`(A3 => ZN) = (0.1, 0.1);`
86			`endspecify`
87
88			`endmodule`
89
90			`module AND3_X2 (A1, A2, A3, ZN);`
91
92			`input A1;`
93			`input A2;`
94			`input A3;`
95			`output ZN;`
96
97			`and(ZN, i_66, A3);`
98			`and(i_66, A1, A2);`
99
100			`specify`
101			`(A1 => ZN) = (0.1, 0.1);`
102			`(A2 => ZN) = (0.1, 0.1);`
103			`(A3 => ZN) = (0.1, 0.1);`
104			`endspecify`
105
106			`endmodule`
107
108			`module AND3_X4 (A1, A2, A3, ZN);`
109
110			`input A1;`
111			`input A2;`
112			`input A3;`
113			`output ZN;`
114
115			`and(ZN, i_46, A3);`
116			`and(i_46, A1, A2);`
117
118			`specify`
119			`(A1 => ZN) = (0.1, 0.1);`
120			`(A2 => ZN) = (0.1, 0.1);`
121			`(A3 => ZN) = (0.1, 0.1);`
122			`endspecify`
123
124			`endmodule`
125
126			`module AND4_X1 (A1, A2, A3, A4, ZN);`
127
128			`input A1;`
129			`input A2;`
130			`input A3;`
131			`input A4;`
132			`output ZN;`
133
134			`and(ZN, i_12, A4);`
135			`and(i_12, i_13, A3);`
136			`and(i_13, A1, A2);`
137
138			`specify`
139			`(A1 => ZN) = (0.1, 0.1);`
140			`(A2 => ZN) = (0.1, 0.1);`
141			`(A3 => ZN) = (0.1, 0.1);`
142			`(A4 => ZN) = (0.1, 0.1);`
143			`endspecify`
144
145			`endmodule`
146
147			`module AND4_X2 (A1, A2, A3, A4, ZN);`
148
149			`input A1;`
150			`input A2;`
151			`input A3;`
152			`input A4;`
153			`output ZN;`
154
155			`and(ZN, i_12, A4);`
156			`and(i_12, i_13, A3);`
157			`and(i_13, A1, A2);`
158
159			`specify`
160			`(A1 => ZN) = (0.1, 0.1);`
161			`(A2 => ZN) = (0.1, 0.1);`
162			`(A3 => ZN) = (0.1, 0.1);`
163			`(A4 => ZN) = (0.1, 0.1);`
164			`endspecify`
165
166			`endmodule`
167
168			`module AND4_X4 (A1, A2, A3, A4, ZN);`
169
170			`input A1;`
171			`input A2;`
172			`input A3;`
173			`input A4;`
174			`output ZN;`
175
176			`and(ZN, i_12, A4);`
177			`and(i_12, i_13, A3);`
178			`and(i_13, A1, A2);`
179
180			`specify`
181			`(A1 => ZN) = (0.1, 0.1);`
182			`(A2 => ZN) = (0.1, 0.1);`
183			`(A3 => ZN) = (0.1, 0.1);`
184			`(A4 => ZN) = (0.1, 0.1);`
185			`endspecify`
186
187			`endmodule`
188
189			`module ANTENNA_X1 (A);`
190
191			`input A;`
192
193			`endmodule`
194
195			`module AOI211_X1 (A, B, C1, C2, ZN);`
196
197			`input A;`
198			`input B;`
199			`input C1;`
200			`input C2;`
201			`output ZN;`
202
203			`not(ZN, i_18);`
204			`or(i_18, i_19, A);`
205			`or(i_19, i_20, B);`
206			`and(i_20, C1, C2);`
207
208			`specify`
209			`if((B == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
210			`if((B == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
211			`if((B == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
212			`if((A == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B => ZN) = (0.1, 0.1);`
213			`if((A == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (B => ZN) = (0.1, 0.1);`
214			`if((A == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B => ZN) = (0.1, 0.1);`
215			`(C1 => ZN) = (0.1, 0.1);`
216			`(C2 => ZN) = (0.1, 0.1);`
217			`endspecify`
218
219			`endmodule`
220
221			`module AOI211_X2 (A, B, C1, C2, ZN);`
222
223			`input A;`
224			`input B;`
225			`input C1;`
226			`input C2;`
227			`output ZN;`
228
229			`not(ZN, i_18);`
230			`or(i_18, i_19, A);`
231			`or(i_19, i_20, B);`
232			`and(i_20, C1, C2);`
233
234			`specify`
235			`if((B == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
236			`if((B == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
237			`if((B == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
238			`if((A == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B => ZN) = (0.1, 0.1);`
239			`if((A == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (B => ZN) = (0.1, 0.1);`
240			`if((A == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B => ZN) = (0.1, 0.1);`
241			`(C1 => ZN) = (0.1, 0.1);`
242			`(C2 => ZN) = (0.1, 0.1);`
243			`endspecify`
244
245			`endmodule`
246
247			`module AOI211_X4 (A, B, C1, C2, ZN);`
248
249			`input A;`
250			`input B;`
251			`input C1;`
252			`input C2;`
253			`output ZN;`
254
255			`not(ZN, i_18);`
256			`or(i_18, i_19, A);`
257			`or(i_19, i_20, B);`
258			`and(i_20, C1, C2);`
259
260			`specify`
261			`if((B == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
262			`if((B == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
263			`if((B == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
264			`if((A == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B => ZN) = (0.1, 0.1);`
265			`if((A == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (B => ZN) = (0.1, 0.1);`
266			`if((A == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B => ZN) = (0.1, 0.1);`
267			`(C1 => ZN) = (0.1, 0.1);`
268			`(C2 => ZN) = (0.1, 0.1);`
269			`endspecify`
270
271			`endmodule`
272
273			`module AOI21_X1 (A, B1, B2, ZN);`
274
275			`input A;`
276			`input B1;`
277			`input B2;`
278			`output ZN;`
279
280			`not(ZN, i_12);`
281			`or(i_12, A, i_13);`
282			`and(i_13, B1, B2);`
283
284			`specify`
285			`if((B1 == 1'b1) && (B2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
286			`if((B1 == 1'b0) && (B2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
287			`if((B1 == 1'b0) && (B2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
288			`(B1 => ZN) = (0.1, 0.1);`
289			`(B2 => ZN) = (0.1, 0.1);`
290			`endspecify`
291
292			`endmodule`
293
294			`module AOI21_X2 (A, B1, B2, ZN);`
295
296			`input A;`
297			`input B1;`
298			`input B2;`
299			`output ZN;`
300
301			`not(ZN, i_52);`
302			`or(i_52, A, i_53);`
303			`and(i_53, B1, B2);`
304
305			`specify`
306			`if((B1 == 1'b1) && (B2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
307			`if((B1 == 1'b0) && (B2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
308			`if((B1 == 1'b0) && (B2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
309			`(B1 => ZN) = (0.1, 0.1);`
310			`(B2 => ZN) = (0.1, 0.1);`
311			`endspecify`
312
313			`endmodule`
314
315			`module AOI21_X4 (A, B1, B2, ZN);`
316
317			`input A;`
318			`input B1;`
319			`input B2;`
320			`output ZN;`
321
322			`not(ZN, i_52);`
323			`or(i_52, A, i_53);`
324			`and(i_53, B1, B2);`
325
326			`specify`
327			`if((B1 == 1'b1) && (B2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
328			`if((B1 == 1'b0) && (B2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
329			`if((B1 == 1'b0) && (B2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
330			`(B1 => ZN) = (0.1, 0.1);`
331			`(B2 => ZN) = (0.1, 0.1);`
332			`endspecify`
333
334			`endmodule`
335
336			`module AOI221_X1 (A, B1, B2, C1, C2, ZN);`
337
338			`input A;`
339			`input B1;`
340			`input B2;`
341			`input C1;`
342			`input C2;`
343			`output ZN;`
344
345			`not(ZN, i_24);`
346			`or(i_24, i_25, i_27);`
347			`or(i_25, i_26, A);`
348			`and(i_26, C1, C2);`
349			`and(i_27, B1, B2);`
350
351			`specify`
352			`(A => ZN) = (0.1, 0.1);`
353			`if((B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b0) \|\| (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0)) (A => ZN) = (0.1, 0.1);`
354			`if((B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
355			`if((B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
356			`if((A == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
357			`if((A == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
358			`if((A == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
359			`if((A == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
360			`if((A == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
361			`if((A == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
362			`if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
363			`if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
364			`if((A == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
365			`if((A == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
366			`if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
367			`if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
368			`endspecify`
369
370			`endmodule`
371
372			`module AOI221_X2 (A, B1, B2, C1, C2, ZN);`
373
374			`input A;`
375			`input B1;`
376			`input B2;`
377			`input C1;`
378			`input C2;`
379			`output ZN;`
380
381			`not(ZN, i_24);`
382			`or(i_24, i_25, i_27);`
383			`or(i_25, i_26, A);`
384			`and(i_26, C1, C2);`
385			`and(i_27, B1, B2);`
386
387			`specify`
388			`(A => ZN) = (0.1, 0.1);`
389			`if((B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b0) \|\| (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0)) (A => ZN) = (0.1, 0.1);`
390			`if((B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) \|\| (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
391			`if((B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
392			`if((A == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
393			`if((A == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
394			`if((A == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
395			`if((A == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
396			`if((A == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
397			`if((A == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
398			`if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
399			`if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
400			`if((A == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
401			`if((A == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
402			`if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
403			`if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
404			`endspecify`
405
406			`endmodule`
407
408			`module AOI221_X4 (A, B1, B2, C1, C2, ZN);`
409
410			`input A;`
411			`input B1;`
412			`input B2;`
413			`input C1;`
414			`input C2;`
415			`output ZN;`
416
417			`not(ZN, i_24);`
418			`or(i_24, i_25, i_27);`
419			`or(i_25, i_26, A);`
420			`and(i_26, C1, C2);`
421			`and(i_27, B1, B2);`
422
423			`specify`
424			`(A => ZN) = (0.1, 0.1);`
425			`if((B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) \|\| (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
426			`if((B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
427			`if((B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0)) (A => ZN) = (0.1, 0.1);`
428			`if((B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
429			`if((A == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
430			`if((A == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
431			`if((A == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
432			`if((A == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
433			`if((A == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
434			`if((A == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
435			`if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
436			`if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
437			`if((A == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
438			`if((A == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
439			`if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
440			`if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
441			`endspecify`
442
443			`endmodule`
444
445			`module AOI222_X1 (A1, A2, B1, B2, C1, C2, ZN);`
446
447			`input A1;`
448			`input A2;`
449			`input B1;`
450			`input B2;`
451			`input C1;`
452			`input C2;`
453			`output ZN;`
454
455			`not(ZN, i_30);`
456			`or(i_30, i_31, i_34);`
457			`or(i_31, i_32, i_33);`
458			`and(i_32, A1, A2);`
459			`and(i_33, B1, B2);`
460			`and(i_34, C1, C2);`
461
462			`specify`
463			`(A1 => ZN) = (0.1, 0.1);`
464			`if((A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
465			`if((A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (A1 => ZN) = (0.1, 0.1);`
466			`if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
467			`if((A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b0) \|\| (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0)) (A1 => ZN) = (0.1, 0.1);`
468			`(A2 => ZN) = (0.1, 0.1);`
469			`if((A1 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0)) (A2 => ZN) = (0.1, 0.1);`
470			`if((A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
471			`if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
472			`if((A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (A2 => ZN) = (0.1, 0.1);`
473			`(B1 => ZN) = (0.1, 0.1);`
474			`if((A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (A1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
475			`if((A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
476			`if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
477			`(B2 => ZN) = (0.1, 0.1);`
478			`if((A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (A1 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
479			`if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
480			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
481			`(C1 => ZN) = (0.1, 0.1);`
482			`if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
483			`if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
484			`if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
485			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
486			`(C2 => ZN) = (0.1, 0.1);`
487			`if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
488			`if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1) \|\| (A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
489			`if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) \|\| (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
490			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
491			`endspecify`
492
493			`endmodule`
494
495			`module AOI222_X2 (A1, A2, B1, B2, C1, C2, ZN);`
496
497			`input A1;`
498			`input A2;`
499			`input B1;`
500			`input B2;`
501			`input C1;`
502			`input C2;`
503			`output ZN;`
504
505			`not(ZN, i_30);`
506			`or(i_30, i_31, i_34);`
507			`or(i_31, i_32, i_33);`
508			`and(i_32, A1, A2);`
509			`and(i_33, B1, B2);`
510			`and(i_34, C1, C2);`
511
512			`specify`
513			`(A1 => ZN) = (0.1, 0.1);`
514			`if((A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
515			`if((A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (A1 => ZN) = (0.1, 0.1);`
516			`if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
517			`if((A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b0) \|\| (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0)) (A1 => ZN) = (0.1, 0.1);`
518			`(A2 => ZN) = (0.1, 0.1);`
519			`if((A1 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0)) (A2 => ZN) = (0.1, 0.1);`
520			`if((A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
521			`if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
522			`if((A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (A2 => ZN) = (0.1, 0.1);`
523			`(B1 => ZN) = (0.1, 0.1);`
524			`if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
525			`if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
526			`if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
527			`if((A1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
528			`(B2 => ZN) = (0.1, 0.1);`
529			`if((A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (A1 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
530			`if((A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
531			`if((A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
532			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
533			`(C1 => ZN) = (0.1, 0.1);`
534			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
535			`if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
536			`if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
537			`if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
538			`(C2 => ZN) = (0.1, 0.1);`
539			`if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
540			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
541			`if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1) \|\| (A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
542			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
543			`endspecify`
544
545			`endmodule`
546
547			`module AOI222_X4 (A1, A2, B1, B2, C1, C2, ZN);`
548
549			`input A1;`
550			`input A2;`
551			`input B1;`
552			`input B2;`
553			`input C1;`
554			`input C2;`
555			`output ZN;`
556
557			`not(ZN, i_30);`
558			`or(i_30, i_31, i_34);`
559			`or(i_31, i_32, i_33);`
560			`and(i_32, A1, A2);`
561			`and(i_33, B1, B2);`
562			`and(i_34, C1, C2);`
563
564			`specify`
565			`(A1 => ZN) = (0.1, 0.1);`
566			`if((A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0)) (A1 => ZN) = (0.1, 0.1);`
567			`if((A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A1 => ZN) = (0.1, 0.1);`
568			`if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
569			`if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A1 => ZN) = (0.1, 0.1);`
570			`(A2 => ZN) = (0.1, 0.1);`
571			`if((A1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0)) (A2 => ZN) = (0.1, 0.1);`
572			`if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A2 => ZN) = (0.1, 0.1);`
573			`if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
574			`(B1 => ZN) = (0.1, 0.1);`
575			`if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
576			`if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
577			`if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
578			`if((A1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
579			`(B2 => ZN) = (0.1, 0.1);`
580			`if((A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
581			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
582			`if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
583			`if((A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
584			`(C1 => ZN) = (0.1, 0.1);`
585			`if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b1) \|\| (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
586			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
587			`if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
588			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1);`
589			`(C2 => ZN) = (0.1, 0.1);`
590			`if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
591			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
592			`if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1) \|\| (A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
593			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1);`
594			`endspecify`
595
596			`endmodule`
597
598			`module AOI22_X1 (A1, A2, B1, B2, ZN);`
599
600			`input A1;`
601			`input A2;`
602			`input B1;`
603			`input B2;`
604			`output ZN;`
605
606			`not(ZN, i_18);`
607			`or(i_18, i_19, i_20);`
608			`and(i_19, A1, A2);`
609			`and(i_20, B1, B2);`
610
611			`specify`
612			`if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
613			`if((A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0)) (A1 => ZN) = (0.1, 0.1);`
614			`if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0)) (A1 => ZN) = (0.1, 0.1);`
615			`if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
616			`if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0)) (A2 => ZN) = (0.1, 0.1);`
617			`if((A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0)) (A2 => ZN) = (0.1, 0.1);`
618			`if((A1 == 1'b0) && (A2 == 1'b0) && (B2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
619			`if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
620			`if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
621			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
622			`if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
623			`if((A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
624			`endspecify`
625
626			`endmodule`
627
628			`module AOI22_X2 (A1, A2, B1, B2, ZN);`
629
630			`input A1;`
631			`input A2;`
632			`input B1;`
633			`input B2;`
634			`output ZN;`
635
636			`not(ZN, i_18);`
637			`or(i_18, i_19, i_20);`
638			`and(i_19, A1, A2);`
639			`and(i_20, B1, B2);`
640
641			`specify`
642			`if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
643			`if((A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0)) (A1 => ZN) = (0.1, 0.1);`
644			`if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0)) (A1 => ZN) = (0.1, 0.1);`
645			`if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
646			`if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0)) (A2 => ZN) = (0.1, 0.1);`
647			`if((A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0)) (A2 => ZN) = (0.1, 0.1);`
648			`if((A1 == 1'b0) && (A2 == 1'b0) && (B2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
649			`if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
650			`if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
651			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
652			`if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
653			`if((A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
654			`endspecify`
655
656			`endmodule`
657
658			`module AOI22_X4 (A1, A2, B1, B2, ZN);`
659
660			`input A1;`
661			`input A2;`
662			`input B1;`
663			`input B2;`
664			`output ZN;`
665
666			`not(ZN, i_18);`
667			`or(i_18, i_19, i_20);`
668			`and(i_19, A1, A2);`
669			`and(i_20, B1, B2);`
670
671			`specify`
672			`if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
673			`if((A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0)) (A1 => ZN) = (0.1, 0.1);`
674			`if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0)) (A1 => ZN) = (0.1, 0.1);`
675			`if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
676			`if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0)) (A2 => ZN) = (0.1, 0.1);`
677			`if((A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0)) (A2 => ZN) = (0.1, 0.1);`
678			`if((A1 == 1'b0) && (A2 == 1'b0) && (B2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
679			`if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
680			`if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
681			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
682			`if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
683			`if((A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
684			`endspecify`
685
686			`endmodule`
687
688			`module BUF_X1 (A, Z);`
689
690			`input A;`
691			`output Z;`
692
693			`buf(Z, A);`
694
695			`specify`
696			`(A => Z) = (0.1, 0.1);`
697			`endspecify`
698
699			`endmodule`
700
701			`module BUF_X16 (A, Z);`
702
703			`input A;`
704			`output Z;`
705
706			`buf(Z, A);`
707
708			`specify`
709			`(A => Z) = (0.1, 0.1);`
710			`endspecify`
711
712			`endmodule`
713
714			`module BUF_X2 (A, Z);`
715
716			`input A;`
717			`output Z;`
718
719			`buf(Z, A);`
720
721			`specify`
722			`(A => Z) = (0.1, 0.1);`
723			`endspecify`
724
725			`endmodule`
726
727			`module BUF_X32 (A, Z);`
728
729			`input A;`
730			`output Z;`
731
732			`buf(Z, A);`
733
734			`specify`
735			`(A => Z) = (0.1, 0.1);`
736			`endspecify`
737
738			`endmodule`
739
740			`module BUF_X4 (A, Z);`
741
742			`input A;`
743			`output Z;`
744
745			`buf(Z, A);`
746
747			`specify`
748			`(A => Z) = (0.1, 0.1);`
749			`endspecify`
750
751			`endmodule`
752
753			`module BUF_X8 (A, Z);`
754
755			`input A;`
756			`output Z;`
757
758			`buf(Z, A);`
759
760			`specify`
761			`(A => Z) = (0.1, 0.1);`
762			`endspecify`
763
764			`endmodule`
765
766			`module CLKBUF_X1 (A, Z);`
767
768			`input A;`
769			`output Z;`
770
771			`buf(Z, A);`
772
773			`specify`
774			`(A => Z) = (0.1, 0.1);`
775			`endspecify`
776
777			`endmodule`
778
779			`module CLKBUF_X2 (A, Z);`
780
781			`input A;`
782			`output Z;`
783
784			`buf(Z, A);`
785
786			`specify`
787			`(A => Z) = (0.1, 0.1);`
788			`endspecify`
789
790			`endmodule`
791
792			`module CLKBUF_X3 (A, Z);`
793
794			`input A;`
795			`output Z;`
796
797			`buf(Z, A);`
798
799			`specify`
800			`(A => Z) = (0.1, 0.1);`
801			`endspecify`
802
803			`endmodule`
804
805			`primitive seq3 (IQ, nextstate, CK, NOTIFIER);`
806			`output IQ;`
807			`input nextstate;`
808			`input CK;`
809			`input NOTIFIER;`
810			`reg IQ;`
811
812			`table`
813			`// nextstate CK NOTIFIER : @IQ : IQ`
814
815			`1 0 ? : ? : 1;`
816			`* ? ? : ? : -; // Ignore all edges on nextstate`
817			`? 1 ? : ? : -; // Ignore non-triggering clock edge`
818			`? ? * : ? : x; // Any NOTIFIER change`
819			`endtable`
820			`endprimitive`
821
822			`module CLKGATETST_X1 (CK, E, SE, GCK);`
823
824			`input CK;`
825			`input E;`
826			`input SE;`
827			`output GCK;`
828			`reg NOTIFIER;`
829
830			`and(GCK, IQ, CK);`
831			`seq3(IQ, nextstate, CK, NOTIFIER);`
832			`not(IQn, IQ);`
833			`or(nextstate, E, SE);`
834
835
836			`specify`
837			`(CK => GCK) = (0.1, 0.1);`
838
839			`$width(negedge CK, 0.1, 0, NOTIFIER);`
840			`$width(posedge CK, 0.1, 0, NOTIFIER);`
841			`$setuphold(posedge CK, negedge E, 0.1, 0.1, NOTIFIER);`
842			`$setuphold(posedge CK, posedge E, 0.1, 0.1, NOTIFIER);`
843			`$width(negedge E, 0.1, 0, NOTIFIER);`
844			`$width(posedge E, 0.1, 0, NOTIFIER);`
845			`$setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER);`
846			`$setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER);`
847			`$width(negedge SE, 0.1, 0, NOTIFIER);`
848			`$width(posedge SE, 0.1, 0, NOTIFIER);`
849			`endspecify`
850
851			`endmodule`
852
853			`primitive seq3 (IQ, nextstate, CK, NOTIFIER);`
854			`output IQ;`
855			`input nextstate;`
856			`input CK;`
857			`input NOTIFIER;`
858			`reg IQ;`
859
860			`table`
861			`// nextstate CK NOTIFIER : @IQ : IQ`
862
863			`1 0 ? : ? : 1;`
864			`* ? ? : ? : -; // Ignore all edges on nextstate`
865			`? 1 ? : ? : -; // Ignore non-triggering clock edge`
866			`? ? * : ? : x; // Any NOTIFIER change`
867			`endtable`
868			`endprimitive`
869
870			`module CLKGATETST_X2 (CK, E, SE, GCK);`
871
872			`input CK;`
873			`input E;`
874			`input SE;`
875			`output GCK;`
876			`reg NOTIFIER;`
877
878			`and(GCK, IQ, CK);`
879			`seq3(IQ, nextstate, CK, NOTIFIER);`
880			`not(IQn, IQ);`
881			`or(nextstate, E, SE);`
882
883
884			`specify`
885			`(CK => GCK) = (0.1, 0.1);`
886
887			`$width(negedge CK, 0.1, 0, NOTIFIER);`
888			`$width(posedge CK, 0.1, 0, NOTIFIER);`
889			`$setuphold(posedge CK, negedge E, 0.1, 0.1, NOTIFIER);`
890			`$setuphold(posedge CK, posedge E, 0.1, 0.1, NOTIFIER);`
891			`$width(negedge E, 0.1, 0, NOTIFIER);`
892			`$width(posedge E, 0.1, 0, NOTIFIER);`
893			`$setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER);`
894			`$setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER);`
895			`$width(negedge SE, 0.1, 0, NOTIFIER);`
896			`$width(posedge SE, 0.1, 0, NOTIFIER);`
897			`endspecify`
898
899			`endmodule`
900
901			`primitive seq3 (IQ, nextstate, CK, NOTIFIER);`
902			`output IQ;`
903			`input nextstate;`
904			`input CK;`
905			`input NOTIFIER;`
906			`reg IQ;`
907
908			`table`
909			`// nextstate CK NOTIFIER : @IQ : IQ`
910
911			`1 0 ? : ? : 1;`
912			`* ? ? : ? : -; // Ignore all edges on nextstate`
913			`? 1 ? : ? : -; // Ignore non-triggering clock edge`
914			`? ? * : ? : x; // Any NOTIFIER change`
915			`endtable`
916			`endprimitive`
917
918			`module CLKGATETST_X4 (CK, E, SE, GCK);`
919
920			`input CK;`
921			`input E;`
922			`input SE;`
923			`output GCK;`
924			`reg NOTIFIER;`
925
926			`and(GCK, IQ, CK);`
927			`seq3(IQ, nextstate, CK, NOTIFIER);`
928			`not(IQn, IQ);`
929			`or(nextstate, E, SE);`
930
931
932			`specify`
933			`(CK => GCK) = (0.1, 0.1);`
934
935			`$width(negedge CK, 0.1, 0, NOTIFIER);`
936			`$width(posedge CK, 0.1, 0, NOTIFIER);`
937			`$setuphold(posedge CK, negedge E, 0.1, 0.1, NOTIFIER);`
938			`$setuphold(posedge CK, posedge E, 0.1, 0.1, NOTIFIER);`
939			`$width(negedge E, 0.1, 0, NOTIFIER);`
940			`$width(posedge E, 0.1, 0, NOTIFIER);`
941			`$setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER);`
942			`$setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER);`
943			`$width(negedge SE, 0.1, 0, NOTIFIER);`
944			`$width(posedge SE, 0.1, 0, NOTIFIER);`
945			`endspecify`
946
947			`endmodule`
948
949			`primitive seq3 (IQ, nextstate, CK, NOTIFIER);`
950			`output IQ;`
951			`input nextstate;`
952			`input CK;`
953			`input NOTIFIER;`
954			`reg IQ;`
955
956			`table`
957			`// nextstate CK NOTIFIER : @IQ : IQ`
958
959			`1 0 ? : ? : 1;`
960			`* ? ? : ? : -; // Ignore all edges on nextstate`
961			`? 1 ? : ? : -; // Ignore non-triggering clock edge`
962			`? ? * : ? : x; // Any NOTIFIER change`
963			`endtable`
964			`endprimitive`
965
966			`module CLKGATETST_X8 (CK, E, SE, GCK);`
967
968			`input CK;`
969			`input E;`
970			`input SE;`
971			`output GCK;`
972			`reg NOTIFIER;`
973
974			`and(GCK, IQ, CK);`
975			`seq3(IQ, nextstate, CK, NOTIFIER);`
976			`not(IQn, IQ);`
977			`or(nextstate, E, SE);`
978
979
980			`specify`
981			`(CK => GCK) = (0.1, 0.1);`
982
983			`$width(negedge CK, 0.1, 0, NOTIFIER);`
984			`$width(posedge CK, 0.1, 0, NOTIFIER);`
985			`$setuphold(posedge CK, negedge E, 0.1, 0.1, NOTIFIER);`
986			`$setuphold(posedge CK, posedge E, 0.1, 0.1, NOTIFIER);`
987			`$width(negedge E, 0.1, 0, NOTIFIER);`
988			`$width(posedge E, 0.1, 0, NOTIFIER);`
989			`$setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER);`
990			`$setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER);`
991			`$width(negedge SE, 0.1, 0, NOTIFIER);`
992			`$width(posedge SE, 0.1, 0, NOTIFIER);`
993			`endspecify`
994
995			`endmodule`
996
997			`primitive seq3 (IQ, nextstate, CK, NOTIFIER);`
998			`output IQ;`
999			`input nextstate;`
1000			`input CK;`
1001			`input NOTIFIER;`
1002			`reg IQ;`
1003
1004			`table`
1005			`// nextstate CK NOTIFIER : @IQ : IQ`
1006
1007			`1 0 ? : ? : 1;`
1008			`* ? ? : ? : -; // Ignore all edges on nextstate`
1009			`? 1 ? : ? : -; // Ignore non-triggering clock edge`
1010			`? ? * : ? : x; // Any NOTIFIER change`
1011			`endtable`
1012			`endprimitive`
1013
1014			`module CLKGATE_X1 (CK, E, GCK);`
1015
1016			`input CK;`
1017			`input E;`
1018			`output GCK;`
1019			`reg NOTIFIER;`
1020
1021			`and(GCK, CK, IQ);`
1022			`seq3(IQ, nextstate, CK, NOTIFIER);`
1023			`not(IQn, IQ);`
1024			`buf(nextstate, E);`
1025
1026
1027			`specify`
1028			`(CK => GCK) = (0.1, 0.1);`
1029
1030			`$width(negedge CK, 0.1, 0, NOTIFIER);`
1031			`$width(posedge CK, 0.1, 0, NOTIFIER);`
1032			`$setuphold(posedge CK, negedge E, 0.1, 0.1, NOTIFIER);`
1033			`$setuphold(posedge CK, posedge E, 0.1, 0.1, NOTIFIER);`
1034			`$width(negedge E, 0.1, 0, NOTIFIER);`
1035			`$width(posedge E, 0.1, 0, NOTIFIER);`
1036			`endspecify`
1037
1038			`endmodule`
1039
1040			`primitive seq3 (IQ, nextstate, CK, NOTIFIER);`
1041			`output IQ;`
1042			`input nextstate;`
1043			`input CK;`
1044			`input NOTIFIER;`
1045			`reg IQ;`
1046
1047			`table`
1048			`// nextstate CK NOTIFIER : @IQ : IQ`
1049
1050			`1 0 ? : ? : 1;`
1051			`* ? ? : ? : -; // Ignore all edges on nextstate`
1052			`? 1 ? : ? : -; // Ignore non-triggering clock edge`
1053			`? ? * : ? : x; // Any NOTIFIER change`
1054			`endtable`
1055			`endprimitive`
1056
1057			`module CLKGATE_X2 (CK, E, GCK);`
1058
1059			`input CK;`
1060			`input E;`
1061			`output GCK;`
1062			`reg NOTIFIER;`
1063
1064			`and(GCK, CK, IQ);`
1065			`seq3(IQ, nextstate, CK, NOTIFIER);`
1066			`not(IQn, IQ);`
1067			`buf(nextstate, E);`
1068
1069
1070			`specify`
1071			`(CK => GCK) = (0.1, 0.1);`
1072
1073			`$width(negedge CK, 0.1, 0, NOTIFIER);`
1074			`$width(posedge CK, 0.1, 0, NOTIFIER);`
1075			`$setuphold(posedge CK, negedge E, 0.1, 0.1, NOTIFIER);`
1076			`$setuphold(posedge CK, posedge E, 0.1, 0.1, NOTIFIER);`
1077			`$width(negedge E, 0.1, 0, NOTIFIER);`
1078			`$width(posedge E, 0.1, 0, NOTIFIER);`
1079			`endspecify`
1080
1081			`endmodule`
1082
1083			`primitive seq3 (IQ, nextstate, CK, NOTIFIER);`
1084			`output IQ;`
1085			`input nextstate;`
1086			`input CK;`
1087			`input NOTIFIER;`
1088			`reg IQ;`
1089
1090			`table`
1091			`// nextstate CK NOTIFIER : @IQ : IQ`
1092
1093			`1 0 ? : ? : 1;`
1094			`* ? ? : ? : -; // Ignore all edges on nextstate`
1095			`? 1 ? : ? : -; // Ignore non-triggering clock edge`
1096			`? ? * : ? : x; // Any NOTIFIER change`
1097			`endtable`
1098			`endprimitive`
1099
1100			`module CLKGATE_X4 (CK, E, GCK);`
1101
1102			`input CK;`
1103			`input E;`
1104			`output GCK;`
1105			`reg NOTIFIER;`
1106
1107			`and(GCK, CK, IQ);`
1108			`seq3(IQ, nextstate, CK, NOTIFIER);`
1109			`not(IQn, IQ);`
1110			`buf(nextstate, E);`
1111
1112
1113			`specify`
1114			`(CK => GCK) = (0.1, 0.1);`
1115
1116			`$width(negedge CK, 0.1, 0, NOTIFIER);`
1117			`$width(posedge CK, 0.1, 0, NOTIFIER);`
1118			`$setuphold(posedge CK, negedge E, 0.1, 0.1, NOTIFIER);`
1119			`$setuphold(posedge CK, posedge E, 0.1, 0.1, NOTIFIER);`
1120			`$width(negedge E, 0.1, 0, NOTIFIER);`
1121			`$width(posedge E, 0.1, 0, NOTIFIER);`
1122			`endspecify`
1123
1124			`endmodule`
1125
1126			`primitive seq3 (IQ, nextstate, CK, NOTIFIER);`
1127			`output IQ;`
1128			`input nextstate;`
1129			`input CK;`
1130			`input NOTIFIER;`
1131			`reg IQ;`
1132
1133			`table`
1134			`// nextstate CK NOTIFIER : @IQ : IQ`
1135
1136			`1 0 ? : ? : 1;`
1137			`* ? ? : ? : -; // Ignore all edges on nextstate`
1138			`? 1 ? : ? : -; // Ignore non-triggering clock edge`
1139			`? ? * : ? : x; // Any NOTIFIER change`
1140			`endtable`
1141			`endprimitive`
1142
1143			`module CLKGATE_X8 (CK, E, GCK);`
1144
1145			`input CK;`
1146			`input E;`
1147			`output GCK;`
1148			`reg NOTIFIER;`
1149
1150			`and(GCK, CK, IQ);`
1151			`seq3(IQ, nextstate, CK, NOTIFIER);`
1152			`not(IQn, IQ);`
1153			`buf(nextstate, E);`
1154
1155
1156			`specify`
1157			`(CK => GCK) = (0.1, 0.1);`
1158
1159			`$width(negedge CK, 0.1, 0, NOTIFIER);`
1160			`$width(posedge CK, 0.1, 0, NOTIFIER);`
1161			`$setuphold(posedge CK, negedge E, 0.1, 0.1, NOTIFIER);`
1162			`$setuphold(posedge CK, posedge E, 0.1, 0.1, NOTIFIER);`
1163			`$width(negedge E, 0.1, 0, NOTIFIER);`
1164			`$width(posedge E, 0.1, 0, NOTIFIER);`
1165			`endspecify`
1166
1167			`endmodule`
1168
1169			`primitive seq3 (IQ, SN, RN, nextstate, CK, NOTIFIER);`
1170			`output IQ;`
1171			`input SN;`
1172			`input RN;`
1173			`input nextstate;`
1174			`input CK;`
1175			`input NOTIFIER;`
1176			`reg IQ;`
1177
1178			`table`
1179			`// SN RN nextstate CK NOTIFIER : @IQ : IQ`
1180			`1 ? 0 r ? : ? : 0;`
1181			`? 1 1 r ? : ? : 1;`
1182			`1 ? 0 * ? : 0 : 0; // reduce pessimism`
1183			`? 1 1 * ? : 1 : 1; // reduce pessimism`
1184			`1 1 * ? ? : ? : -; // Ignore all edges on nextstate`
1185			`1 1 ? f ? : ? : -; // Ignore non-triggering clock edge`
1186
1187			`* 1 ? ? ? : 1 : 1; // Cover all transitions on SN`
1188			`? 0 ? ? ? : ? : 0; // RN activated`
1189			`1 * ? ? ? : 0 : 0; // Cover all transitions on RN`
1190			`? ? ? ? * : ? : x; // Any NOTIFIER change`
1191			`endtable`
1192			`endprimitive`
1193
1194			`module DFFRS_X1 (CK, D, RN, SN, Q, QN);`
1195
1196			`input CK;`
1197			`input D;`
1198			`input RN;`
1199			`input SN;`
1200			`output Q;`
1201			`output QN;`
1202			`reg NOTIFIER;`
1203
1204			`seq3(IQ, SN, RN, nextstate, CK, NOTIFIER);`
1205			`and(IQN, i_15, i_16);`
1206			`not(i_15, IQ);`
1207			`not(i_16, i_17);`
1208			`and(i_17, i_18, i_19);`
1209			`not(i_18, SN);`
1210			`not(i_19, RN);`
1211			`buf(Q, IQ);`
1212			`buf(QN, IQN);`
1213			`buf(nextstate, D);`
1214
1215			`and(id_3, SN, RN);`
1216
1217			`specify`
1218			`(posedge CK => (Q +: D)) = (0.1, 0.1);`
1219			`if((CK == 1'b1) && (SN == 1'b0)) (RN => Q) = (0.1, 0.1);`
1220			`if((CK == 1'b0) && (SN == 1'b0)) (RN => Q) = (0.1, 0.1);`
1221			`if((CK == 1'b1) && (SN == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);`
1222			`if((CK == 1'b0) && (SN == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);`
1223			`if((CK == 1'b1) && (RN == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);`
1224			`if((CK == 1'b0) && (RN == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);`
1225			`(posedge CK => (QN -: D)) = (0.1, 0.1);`
1226			`if((CK == 1'b1) && (SN == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1);`
1227			`if((CK == 1'b0) && (SN == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1);`
1228			`if((CK == 1'b1) && (RN == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);`
1229			`if((CK == 1'b1) && (RN == 1'b0)) (SN => QN) = (0.1, 0.1);`
1230			`if((CK == 1'b0) && (RN == 1'b0)) (SN => QN) = (0.1, 0.1);`
1231			`if((CK == 1'b0) && (RN == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);`
1232
1233			`$width(negedge CK &&& id_3, 0.1, 0, NOTIFIER);`
1234			`$width(posedge CK &&& id_3, 0.1, 0, NOTIFIER);`
1235			`$setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER);`
1236			`$setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER);`
1237			`$width(negedge D, 0.1, 0, NOTIFIER);`
1238			`$width(posedge D, 0.1, 0, NOTIFIER);`
1239			`$recovery(posedge RN, posedge CK, 0.1, NOTIFIER);`
1240			`$hold(posedge CK, posedge RN, 0.1, NOTIFIER);`
1241			`$width(negedge RN, 0.1, 0, NOTIFIER);`
1242			`$width(posedge RN, 0.1, 0, NOTIFIER);`
1243			`$recovery(posedge SN, posedge CK, 0.1, NOTIFIER);`
1244			`$hold(posedge CK, posedge SN, 0.1, NOTIFIER);`
1245			`$width(negedge SN, 0.1, 0, NOTIFIER);`
1246			`$width(posedge SN, 0.1, 0, NOTIFIER);`
1247			`endspecify`
1248
1249			`endmodule`
1250
1251			`primitive seq3 (IQ, SN, RN, nextstate, CK, NOTIFIER);`
1252			`output IQ;`
1253			`input SN;`
1254			`input RN;`
1255			`input nextstate;`
1256			`input CK;`
1257			`input NOTIFIER;`
1258			`reg IQ;`
1259
1260			`table`
1261			`// SN RN nextstate CK NOTIFIER : @IQ : IQ`
1262			`1 ? 0 r ? : ? : 0;`
1263			`? 1 1 r ? : ? : 1;`
1264			`1 ? 0 * ? : 0 : 0; // reduce pessimism`
1265			`? 1 1 * ? : 1 : 1; // reduce pessimism`
1266			`1 1 * ? ? : ? : -; // Ignore all edges on nextstate`
1267			`1 1 ? f ? : ? : -; // Ignore non-triggering clock edge`
1268
1269			`* 1 ? ? ? : 1 : 1; // Cover all transitions on SN`
1270			`? 0 ? ? ? : ? : 0; // RN activated`
1271			`1 * ? ? ? : 0 : 0; // Cover all transitions on RN`
1272			`? ? ? ? * : ? : x; // Any NOTIFIER change`
1273			`endtable`
1274			`endprimitive`
1275
1276			`module DFFRS_X2 (CK, D, RN, SN, Q, QN);`
1277
1278			`input CK;`
1279			`input D;`
1280			`input RN;`
1281			`input SN;`
1282			`output Q;`
1283			`output QN;`
1284			`reg NOTIFIER;`
1285
1286			`seq3(IQ, SN, RN, nextstate, CK, NOTIFIER);`
1287			`and(IQN, i_15, i_16);`
1288			`not(i_15, IQ);`
1289			`not(i_16, i_17);`
1290			`and(i_17, i_18, i_19);`
1291			`not(i_18, SN);`
1292			`not(i_19, RN);`
1293			`buf(Q, IQ);`
1294			`buf(QN, IQN);`
1295			`buf(nextstate, D);`
1296
1297			`and(id_3, SN, RN);`
1298
1299			`specify`
1300			`(posedge CK => (Q +: D)) = (0.1, 0.1);`
1301			`if((CK == 1'b1) && (SN == 1'b0)) (RN => Q) = (0.1, 0.1);`
1302			`if((CK == 1'b0) && (SN == 1'b0)) (RN => Q) = (0.1, 0.1);`
1303			`if((CK == 1'b1) && (SN == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);`
1304			`if((CK == 1'b0) && (SN == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);`
1305			`if((CK == 1'b1) && (RN == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);`
1306			`if((CK == 1'b0) && (RN == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);`
1307			`(posedge CK => (QN -: D)) = (0.1, 0.1);`
1308			`if((CK == 1'b1) && (SN == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1);`
1309			`if((CK == 1'b0) && (SN == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1);`
1310			`if((CK == 1'b1) && (RN == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);`
1311			`if((CK == 1'b1) && (RN == 1'b0)) (SN => QN) = (0.1, 0.1);`
1312			`if((CK == 1'b0) && (RN == 1'b0)) (SN => QN) = (0.1, 0.1);`
1313			`if((CK == 1'b0) && (RN == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);`
1314
1315			`$width(negedge CK &&& id_3, 0.1, 0, NOTIFIER);`
1316			`$width(posedge CK &&& id_3, 0.1, 0, NOTIFIER);`
1317			`$setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER);`
1318			`$setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER);`
1319			`$width(negedge D, 0.1, 0, NOTIFIER);`
1320			`$width(posedge D, 0.1, 0, NOTIFIER);`
1321			`$recovery(posedge RN, posedge CK, 0.1, NOTIFIER);`
1322			`$hold(posedge CK, posedge RN, 0.1, NOTIFIER);`
1323			`$width(negedge RN, 0.1, 0, NOTIFIER);`
1324			`$width(posedge RN, 0.1, 0, NOTIFIER);`
1325			`$recovery(posedge SN, posedge CK, 0.1, NOTIFIER);`
1326			`$hold(posedge CK, posedge SN, 0.1, NOTIFIER);`
1327			`$width(negedge SN, 0.1, 0, NOTIFIER);`
1328			`$width(posedge SN, 0.1, 0, NOTIFIER);`
1329			`endspecify`
1330
1331			`endmodule`
1332
1333			`primitive seq3 (IQ, RN, nextstate, CK, NOTIFIER);`
1334			`output IQ;`
1335			`input RN;`
1336			`input nextstate;`
1337			`input CK;`
1338			`input NOTIFIER;`
1339			`reg IQ;`
1340
1341			`table`
1342			`// RN nextstate CK NOTIFIER : @IQ : IQ`
1343			`? 0 r ? : ? : 0;`
1344			`1 1 r ? : ? : 1;`
1345			`? 0 * ? : 0 : 0; // reduce pessimism`
1346			`1 1 * ? : 1 : 1; // reduce pessimism`
1347			`1 * ? ? : ? : -; // Ignore all edges on nextstate`
1348			`1 ? f ? : ? : -; // Ignore non-triggering clock edge`
1349
1350			`* ? ? ? : 0 : 0; // Cover all transitions on RN`
1351			`? ? ? * : ? : x; // Any NOTIFIER change`
1352			`endtable`
1353			`endprimitive`
1354
1355			`module DFFR_X1 (CK, D, RN, Q, QN);`
1356
1357			`input CK;`
1358			`input D;`
1359			`input RN;`
1360			`output Q;`
1361			`output QN;`
1362			`reg NOTIFIER;`
1363
1364			`seq3(IQ, RN, nextstate, CK, NOTIFIER);`
1365			`not(IQN, IQ);`
1366			`buf(Q, IQ);`
1367			`buf(QN, IQN);`
1368			`buf(nextstate, D);`
1369
1370
1371			`specify`
1372			`(posedge CK => (Q +: D)) = (0.1, 0.1);`
1373			`if((CK == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);`
1374			`if((CK == 1'b0)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);`
1375			`(posedge CK => (QN -: D)) = (0.1, 0.1);`
1376			`if((CK == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1);`
1377			`if((CK == 1'b0)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1);`
1378
1379			`$width(negedge CK &&& ((RN)), 0.1, 0, NOTIFIER);`
1380			`$width(posedge CK &&& ((RN)), 0.1, 0, NOTIFIER);`
1381			`$setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER);`
1382			`$setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER);`
1383			`$width(negedge D, 0.1, 0, NOTIFIER);`
1384			`$width(posedge D, 0.1, 0, NOTIFIER);`
1385			`$recovery(posedge RN, posedge CK, 0.1, NOTIFIER);`
1386			`$hold(posedge CK, posedge RN, 0.1, NOTIFIER);`
1387			`$width(negedge RN, 0.1, 0, NOTIFIER);`
1388			`$width(posedge RN, 0.1, 0, NOTIFIER);`
1389			`endspecify`
1390
1391			`endmodule`
1392
1393			`primitive seq3 (IQ, RN, nextstate, CK, NOTIFIER);`
1394			`output IQ;`
1395			`input RN;`
1396			`input nextstate;`
1397			`input CK;`
1398			`input NOTIFIER;`
1399			`reg IQ;`
1400
1401			`table`
1402			`// RN nextstate CK NOTIFIER : @IQ : IQ`
1403			`? 0 r ? : ? : 0;`
1404			`1 1 r ? : ? : 1;`
1405			`? 0 * ? : 0 : 0; // reduce pessimism`
1406			`1 1 * ? : 1 : 1; // reduce pessimism`
1407			`1 * ? ? : ? : -; // Ignore all edges on nextstate`
1408			`1 ? f ? : ? : -; // Ignore non-triggering clock edge`
1409
1410			`* ? ? ? : 0 : 0; // Cover all transitions on RN`
1411			`? ? ? * : ? : x; // Any NOTIFIER change`
1412			`endtable`
1413			`endprimitive`
1414
1415			`module DFFR_X2 (CK, D, RN, Q, QN);`
1416
1417			`input CK;`
1418			`input D;`
1419			`input RN;`
1420			`output Q;`
1421			`output QN;`
1422			`reg NOTIFIER;`
1423
1424			`seq3(IQ, RN, nextstate, CK, NOTIFIER);`
1425			`not(IQN, IQ);`
1426			`buf(Q, IQ);`
1427			`buf(QN, IQN);`
1428			`buf(nextstate, D);`
1429
1430
1431			`specify`
1432			`(posedge CK => (Q +: D)) = (0.1, 0.1);`
1433			`if((CK == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);`
1434			`if((CK == 1'b0)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);`
1435			`(posedge CK => (QN -: D)) = (0.1, 0.1);`
1436			`if((CK == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1);`
1437			`if((CK == 1'b0)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1);`
1438
1439			`$width(negedge CK &&& ((RN)), 0.1, 0, NOTIFIER);`
1440			`$width(posedge CK &&& ((RN)), 0.1, 0, NOTIFIER);`
1441			`$setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER);`
1442			`$setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER);`
1443			`$width(negedge D, 0.1, 0, NOTIFIER);`
1444			`$width(posedge D, 0.1, 0, NOTIFIER);`
1445			`$recovery(posedge RN, posedge CK, 0.1, NOTIFIER);`
1446			`$hold(posedge CK, posedge RN, 0.1, NOTIFIER);`
1447			`$width(negedge RN, 0.1, 0, NOTIFIER);`
1448			`$width(posedge RN, 0.1, 0, NOTIFIER);`
1449			`endspecify`
1450
1451			`endmodule`
1452
1453			`primitive seq3 (IQ, SN, nextstate, CK, NOTIFIER);`
1454			`output IQ;`
1455			`input SN;`
1456			`input nextstate;`
1457			`input CK;`
1458			`input NOTIFIER;`
1459			`reg IQ;`
1460
1461			`table`
1462			`// SN nextstate CK NOTIFIER : @IQ : IQ`
1463			`1 0 r ? : ? : 0;`
1464			`? 1 r ? : ? : 1;`
1465			`1 0 * ? : 0 : 0; // reduce pessimism`
1466			`? 1 * ? : 1 : 1; // reduce pessimism`
1467			`1 * ? ? : ? : -; // Ignore all edges on nextstate`
1468			`1 ? f ? : ? : -; // Ignore non-triggering clock edge`
1469
1470			`* ? ? ? : 1 : 1; // Cover all transitions on SN`
1471			`? ? ? * : ? : x; // Any NOTIFIER change`
1472			`endtable`
1473			`endprimitive`
1474
1475			`module DFFS_X1 (CK, D, SN, Q, QN);`
1476
1477			`input CK;`
1478			`input D;`
1479			`input SN;`
1480			`output Q;`
1481			`output QN;`
1482			`reg NOTIFIER;`
1483
1484			`seq3(IQ, SN, nextstate, CK, NOTIFIER);`
1485			`not(IQN, IQ);`
1486			`buf(Q, IQ);`
1487			`buf(QN, IQN);`
1488			`buf(nextstate, D);`
1489
1490
1491			`specify`
1492			`(posedge CK => (Q +: D)) = (0.1, 0.1);`
1493			`if((CK == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);`
1494			`if((CK == 1'b0)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);`
1495			`(posedge CK => (QN -: D)) = (0.1, 0.1);`
1496			`if((CK == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);`
1497			`if((CK == 1'b0)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);`
1498
1499			`$width(negedge CK &&& ((SN)), 0.1, 0, NOTIFIER);`
1500			`$width(posedge CK &&& ((SN)), 0.1, 0, NOTIFIER);`
1501			`$setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER);`
1502			`$setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER);`
1503			`$width(negedge D, 0.1, 0, NOTIFIER);`
1504			`$width(posedge D, 0.1, 0, NOTIFIER);`
1505			`$recovery(posedge SN, posedge CK, 0.1, NOTIFIER);`
1506			`$hold(posedge CK, posedge SN, 0.1, NOTIFIER);`
1507			`$width(negedge SN, 0.1, 0, NOTIFIER);`
1508			`$width(posedge SN, 0.1, 0, NOTIFIER);`
1509			`endspecify`
1510
1511			`endmodule`
1512
1513			`primitive seq3 (IQ, SN, nextstate, CK, NOTIFIER);`
1514			`output IQ;`
1515			`input SN;`
1516			`input nextstate;`
1517			`input CK;`
1518			`input NOTIFIER;`
1519			`reg IQ;`
1520
1521			`table`
1522			`// SN nextstate CK NOTIFIER : @IQ : IQ`
1523			`1 0 r ? : ? : 0;`
1524			`? 1 r ? : ? : 1;`
1525			`1 0 * ? : 0 : 0; // reduce pessimism`
1526			`? 1 * ? : 1 : 1; // reduce pessimism`
1527			`1 * ? ? : ? : -; // Ignore all edges on nextstate`
1528			`1 ? f ? : ? : -; // Ignore non-triggering clock edge`
1529
1530			`* ? ? ? : 1 : 1; // Cover all transitions on SN`
1531			`? ? ? * : ? : x; // Any NOTIFIER change`
1532			`endtable`
1533			`endprimitive`
1534
1535			`module DFFS_X2 (CK, D, SN, Q, QN);`
1536
1537			`input CK;`
1538			`input D;`
1539			`input SN;`
1540			`output Q;`
1541			`output QN;`
1542			`reg NOTIFIER;`
1543
1544			`seq3(IQ, SN, nextstate, CK, NOTIFIER);`
1545			`not(IQN, IQ);`
1546			`buf(Q, IQ);`
1547			`buf(QN, IQN);`
1548			`buf(nextstate, D);`
1549
1550
1551			`specify`
1552			`(posedge CK => (Q +: D)) = (0.1, 0.1);`
1553			`if((CK == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);`
1554			`if((CK == 1'b0)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);`
1555			`(posedge CK => (QN -: D)) = (0.1, 0.1);`
1556			`if((CK == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);`
1557			`if((CK == 1'b0)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);`
1558
1559			`$width(negedge CK &&& ((SN)), 0.1, 0, NOTIFIER);`
1560			`$width(posedge CK &&& ((SN)), 0.1, 0, NOTIFIER);`
1561			`$setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER);`
1562			`$setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER);`
1563			`$width(negedge D, 0.1, 0, NOTIFIER);`
1564			`$width(posedge D, 0.1, 0, NOTIFIER);`
1565			`$recovery(posedge SN, posedge CK, 0.1, NOTIFIER);`
1566			`$hold(posedge CK, posedge SN, 0.1, NOTIFIER);`
1567			`$width(negedge SN, 0.1, 0, NOTIFIER);`
1568			`$width(posedge SN, 0.1, 0, NOTIFIER);`
1569			`endspecify`
1570
1571			`endmodule`
1572
1573			`primitive seq3 (IQ, nextstate, CK, NOTIFIER);`
1574			`output IQ;`
1575			`input nextstate;`
1576			`input CK;`
1577			`input NOTIFIER;`
1578			`reg IQ;`
1579
1580			`table`
1581			`// nextstate CK NOTIFIER : @IQ : IQ`
1582
1583			`1 r ? : ? : 1;`
1584
1585			`1 * ? : 1 : 1; // reduce pessimism`
1586			`* ? ? : ? : -; // Ignore all edges on nextstate`
1587			`? f ? : ? : -; // Ignore non-triggering clock edge`
1588			`? ? * : ? : x; // Any NOTIFIER change`
1589			`endtable`
1590			`endprimitive`
1591
1592			`module DFF_X1 (CK, D, Q, QN);`
1593
1594			`input CK;`
1595			`input D;`
1596			`output Q;`
1597			`output QN;`
1598			`reg NOTIFIER;`
1599
1600			`seq3(IQ, nextstate, CK, NOTIFIER);`
1601			`not(IQN, IQ);`
1602			`buf(Q, IQ);`
1603			`buf(QN, IQN);`
1604			`buf(nextstate, D);`
1605
1606
1607			`specify`
1608			`(posedge CK => (Q +: D)) = (0.1, 0.1);`
1609			`(posedge CK => (QN -: D)) = (0.1, 0.1);`
1610
1611			`$width(negedge CK, 0.1, 0, NOTIFIER);`
1612			`$width(posedge CK, 0.1, 0, NOTIFIER);`
1613			`$setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER);`
1614			`$setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER);`
1615			`$width(negedge D, 0.1, 0, NOTIFIER);`
1616			`$width(posedge D, 0.1, 0, NOTIFIER);`
1617			`endspecify`
1618
1619			`endmodule`
1620
1621			`primitive seq3 (IQ, nextstate, CK, NOTIFIER);`
1622			`output IQ;`
1623			`input nextstate;`
1624			`input CK;`
1625			`input NOTIFIER;`
1626			`reg IQ;`
1627
1628			`table`
1629			`// nextstate CK NOTIFIER : @IQ : IQ`
1630
1631			`1 r ? : ? : 1;`
1632
1633			`1 * ? : 1 : 1; // reduce pessimism`
1634			`* ? ? : ? : -; // Ignore all edges on nextstate`
1635			`? f ? : ? : -; // Ignore non-triggering clock edge`
1636			`? ? * : ? : x; // Any NOTIFIER change`
1637			`endtable`
1638			`endprimitive`
1639
1640			`module DFF_X2 (CK, D, Q, QN);`
1641
1642			`input CK;`
1643			`input D;`
1644			`output Q;`
1645			`output QN;`
1646			`reg NOTIFIER;`
1647
1648			`seq3(IQ, nextstate, CK, NOTIFIER);`
1649			`not(IQN, IQ);`
1650			`buf(Q, IQ);`
1651			`buf(QN, IQN);`
1652			`buf(nextstate, D);`
1653
1654
1655			`specify`
1656			`(posedge CK => (Q +: D)) = (0.1, 0.1);`
1657			`(posedge CK => (QN -: D)) = (0.1, 0.1);`
1658
1659			`$width(negedge CK, 0.1, 0, NOTIFIER);`
1660			`$width(posedge CK, 0.1, 0, NOTIFIER);`
1661			`$setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER);`
1662			`$setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER);`
1663			`$width(negedge D, 0.1, 0, NOTIFIER);`
1664			`$width(posedge D, 0.1, 0, NOTIFIER);`
1665			`endspecify`
1666
1667			`endmodule`
1668
1669			`primitive seq3 (IQ, nextstate, G, NOTIFIER);`
1670			`output IQ;`
1671			`input nextstate;`
1672			`input G;`
1673			`input NOTIFIER;`
1674			`reg IQ;`
1675
1676			`table`
1677			`// nextstate G NOTIFIER : @IQ : IQ`
1678
1679			`1 1 ? : ? : 1;`
1680			`* ? ? : ? : -; // Ignore all edges on nextstate`
1681			`? 0 ? : ? : -; // Ignore non-triggering clock edge`
1682			`? ? * : ? : x; // Any NOTIFIER change`
1683			`endtable`
1684			`endprimitive`
1685
1686			`module DLH_X1 (D, G, Q);`
1687
1688			`input D;`
1689			`input G;`
1690			`output Q;`
1691			`reg NOTIFIER;`
1692
1693			`seq3(IQ, nextstate, G, NOTIFIER);`
1694			`not(IQN, IQ);`
1695			`buf(Q, IQ);`
1696			`buf(nextstate, D);`
1697
1698
1699			`specify`
1700			`(D => Q) = (0.1, 0.1);`
1701			`(posedge G => (Q +: D)) = (0.1, 0.1);`
1702
1703			`$setuphold(negedge G, negedge D, 0.1, 0.1, NOTIFIER);`
1704			`$setuphold(negedge G, posedge D, 0.1, 0.1, NOTIFIER);`
1705			`$width(negedge D, 0.1, 0, NOTIFIER);`
1706			`$width(posedge D, 0.1, 0, NOTIFIER);`
1707			`$width(negedge G, 0.1, 0, NOTIFIER);`
1708			`$width(posedge G, 0.1, 0, NOTIFIER);`
1709			`endspecify`
1710
1711			`endmodule`
1712
1713			`primitive seq3 (IQ, nextstate, G, NOTIFIER);`
1714			`output IQ;`
1715			`input nextstate;`
1716			`input G;`
1717			`input NOTIFIER;`
1718			`reg IQ;`
1719
1720			`table`
1721			`// nextstate G NOTIFIER : @IQ : IQ`
1722
1723			`1 1 ? : ? : 1;`
1724			`* ? ? : ? : -; // Ignore all edges on nextstate`
1725			`? 0 ? : ? : -; // Ignore non-triggering clock edge`
1726			`? ? * : ? : x; // Any NOTIFIER change`
1727			`endtable`
1728			`endprimitive`
1729
1730			`module DLH_X2 (D, G, Q);`
1731
1732			`input D;`
1733			`input G;`
1734			`output Q;`
1735			`reg NOTIFIER;`
1736
1737			`seq3(IQ, nextstate, G, NOTIFIER);`
1738			`not(IQN, IQ);`
1739			`buf(Q, IQ);`
1740			`buf(nextstate, D);`
1741
1742
1743			`specify`
1744			`(D => Q) = (0.1, 0.1);`
1745			`(posedge G => (Q +: D)) = (0.1, 0.1);`
1746
1747			`$setuphold(negedge G, negedge D, 0.1, 0.1, NOTIFIER);`
1748			`$setuphold(negedge G, posedge D, 0.1, 0.1, NOTIFIER);`
1749			`$width(negedge D, 0.1, 0, NOTIFIER);`
1750			`$width(posedge D, 0.1, 0, NOTIFIER);`
1751			`$width(negedge G, 0.1, 0, NOTIFIER);`
1752			`$width(posedge G, 0.1, 0, NOTIFIER);`
1753			`endspecify`
1754
1755			`endmodule`
1756
1757			`primitive seq3 (IQ, nextstate, GN, NOTIFIER);`
1758			`output IQ;`
1759			`input nextstate;`
1760			`input GN;`
1761			`input NOTIFIER;`
1762			`reg IQ;`
1763
1764			`table`
1765			`// nextstate GN NOTIFIER : @IQ : IQ`
1766
1767			`1 0 ? : ? : 1;`
1768			`* ? ? : ? : -; // Ignore all edges on nextstate`
1769			`? 1 ? : ? : -; // Ignore non-triggering clock edge`
1770			`? ? * : ? : x; // Any NOTIFIER change`
1771			`endtable`
1772			`endprimitive`
1773
1774			`module DLL_X1 (D, GN, Q);`
1775
1776			`input D;`
1777			`input GN;`
1778			`output Q;`
1779			`reg NOTIFIER;`
1780
1781			`seq3(IQ, nextstate, GN, NOTIFIER);`
1782			`not(IQN, IQ);`
1783			`buf(Q, IQ);`
1784			`buf(nextstate, D);`
1785
1786
1787			`specify`
1788			`(D => Q) = (0.1, 0.1);`
1789			`(negedge GN => (Q +: D)) = (0.1, 0.1);`
1790
1791			`$setuphold(posedge GN, negedge D, 0.1, 0.1, NOTIFIER);`
1792			`$setuphold(posedge GN, posedge D, 0.1, 0.1, NOTIFIER);`
1793			`$width(negedge D, 0.1, 0, NOTIFIER);`
1794			`$width(posedge D, 0.1, 0, NOTIFIER);`
1795			`$width(negedge GN, 0.1, 0, NOTIFIER);`
1796			`$width(posedge GN, 0.1, 0, NOTIFIER);`
1797			`endspecify`
1798
1799			`endmodule`
1800
1801			`primitive seq3 (IQ, nextstate, GN, NOTIFIER);`
1802			`output IQ;`
1803			`input nextstate;`
1804			`input GN;`
1805			`input NOTIFIER;`
1806			`reg IQ;`
1807
1808			`table`
1809			`// nextstate GN NOTIFIER : @IQ : IQ`
1810
1811			`1 0 ? : ? : 1;`
1812			`* ? ? : ? : -; // Ignore all edges on nextstate`
1813			`? 1 ? : ? : -; // Ignore non-triggering clock edge`
1814			`? ? * : ? : x; // Any NOTIFIER change`
1815			`endtable`
1816			`endprimitive`
1817
1818			`module DLL_X2 (D, GN, Q);`
1819
1820			`input D;`
1821			`input GN;`
1822			`output Q;`
1823			`reg NOTIFIER;`
1824
1825			`seq3(IQ, nextstate, GN, NOTIFIER);`
1826			`not(IQN, IQ);`
1827			`buf(Q, IQ);`
1828			`buf(nextstate, D);`
1829
1830
1831			`specify`
1832			`(D => Q) = (0.1, 0.1);`
1833			`(negedge GN => (Q +: D)) = (0.1, 0.1);`
1834
1835			`$setuphold(posedge GN, negedge D, 0.1, 0.1, NOTIFIER);`
1836			`$setuphold(posedge GN, posedge D, 0.1, 0.1, NOTIFIER);`
1837			`$width(negedge D, 0.1, 0, NOTIFIER);`
1838			`$width(posedge D, 0.1, 0, NOTIFIER);`
1839			`$width(negedge GN, 0.1, 0, NOTIFIER);`
1840			`$width(posedge GN, 0.1, 0, NOTIFIER);`
1841			`endspecify`
1842
1843			`endmodule`
1844
1845			`module FA_X1 (A, B, CI, CO, S);`
1846
1847			`input A;`
1848			`input B;`
1849			`input CI;`
1850			`output CO;`
1851			`output S;`
1852
1853			`or(CO, i_24, i_25);`
1854			`and(i_24, A, B);`
1855			`and(i_25, CI, i_26);`
1856			`or(i_26, A, B);`
1857			`xor(S, CI, i_30);`
1858			`xor(i_30, A, B);`
1859
1860			`specify`
1861			`if((B == 1'b0) && (CI == 1'b1)) (A => CO) = (0.1, 0.1);`
1862			`if((B == 1'b1) && (CI == 1'b0)) (A => CO) = (0.1, 0.1);`
1863			`if((A == 1'b1) && (CI == 1'b0)) (B => CO) = (0.1, 0.1);`
1864			`if((A == 1'b0) && (CI == 1'b1)) (B => CO) = (0.1, 0.1);`
1865			`if((A == 1'b1) && (B == 1'b0)) (CI => CO) = (0.1, 0.1);`
1866			`if((A == 1'b0) && (B == 1'b1)) (CI => CO) = (0.1, 0.1);`
1867			`if((B == 1'b0) && (CI == 1'b1)) (A => S) = (0.1, 0.1);`
1868			`if((B == 1'b0) && (CI == 1'b0)) (A => S) = (0.1, 0.1);`
1869			`if((B == 1'b1) && (CI == 1'b1)) (A => S) = (0.1, 0.1);`
1870			`if((B == 1'b1) && (CI == 1'b0)) (A => S) = (0.1, 0.1);`
1871			`if((A == 1'b0) && (CI == 1'b0)) (B => S) = (0.1, 0.1);`
1872			`if((A == 1'b1) && (CI == 1'b0)) (B => S) = (0.1, 0.1);`
1873			`if((A == 1'b1) && (CI == 1'b1)) (B => S) = (0.1, 0.1);`
1874			`if((A == 1'b0) && (CI == 1'b1)) (B => S) = (0.1, 0.1);`
1875			`if((A == 1'b1) && (B == 1'b1)) (CI => S) = (0.1, 0.1);`
1876			`if((A == 1'b1) && (B == 1'b0)) (CI => S) = (0.1, 0.1);`
1877			`if((A == 1'b0) && (B == 1'b1)) (CI => S) = (0.1, 0.1);`
1878			`if((A == 1'b0) && (B == 1'b0)) (CI => S) = (0.1, 0.1);`
1879			`endspecify`
1880
1881			`endmodule`
1882
1883			`module FILLCELL_X1 ();`
1884
1885
1886			`endmodule`
1887
1888			`module FILLCELL_X16 ();`
1889
1890
1891			`endmodule`
1892
1893			`module FILLCELL_X2 ();`
1894
1895
1896			`endmodule`
1897
1898			`module FILLCELL_X32 ();`
1899
1900
1901			`endmodule`
1902
1903			`module FILLCELL_X4 ();`
1904
1905
1906			`endmodule`
1907
1908			`module FILLCELL_X8 ();`
1909
1910
1911			`endmodule`
1912
1913			`module HA_X1 (A, B, CO, S);`
1914
1915			`input A;`
1916			`input B;`
1917			`output CO;`
1918			`output S;`
1919
1920			`and(CO, A, B);`
1921			`xor(S, A, B);`
1922
1923			`specify`
1924			`(A => CO) = (0.1, 0.1);`
1925			`(B => CO) = (0.1, 0.1);`
1926			`if((B == 1'b0)) (A => S) = (0.1, 0.1);`
1927			`if((B == 1'b1)) (A => S) = (0.1, 0.1);`
1928			`if((A == 1'b1)) (B => S) = (0.1, 0.1);`
1929			`if((A == 1'b0)) (B => S) = (0.1, 0.1);`
1930			`endspecify`
1931
1932			`endmodule`
1933
1934			`module INV_X1 (A, ZN);`
1935
1936			`input A;`
1937			`output ZN;`
1938
1939			`not(ZN, A);`
1940
1941			`specify`
1942			`(A => ZN) = (0.1, 0.1);`
1943			`endspecify`
1944
1945			`endmodule`
1946
1947			`module INV_X16 (A, ZN);`
1948
1949			`input A;`
1950			`output ZN;`
1951
1952			`not(ZN, A);`
1953
1954			`specify`
1955			`(A => ZN) = (0.1, 0.1);`
1956			`endspecify`
1957
1958			`endmodule`
1959
1960			`module INV_X2 (A, ZN);`
1961
1962			`input A;`
1963			`output ZN;`
1964
1965			`not(ZN, A);`
1966
1967			`specify`
1968			`(A => ZN) = (0.1, 0.1);`
1969			`endspecify`
1970
1971			`endmodule`
1972
1973			`module INV_X32 (A, ZN);`
1974
1975			`input A;`
1976			`output ZN;`
1977
1978			`not(ZN, A);`
1979
1980			`specify`
1981			`(A => ZN) = (0.1, 0.1);`
1982			`endspecify`
1983
1984			`endmodule`
1985
1986			`module INV_X4 (A, ZN);`
1987
1988			`input A;`
1989			`output ZN;`
1990
1991			`not(ZN, A);`
1992
1993			`specify`
1994			`(A => ZN) = (0.1, 0.1);`
1995			`endspecify`
1996
1997			`endmodule`
1998
1999			`module INV_X8 (A, ZN);`
2000
2001			`input A;`
2002			`output ZN;`
2003
2004			`not(ZN, A);`
2005
2006			`specify`
2007			`(A => ZN) = (0.1, 0.1);`
2008			`endspecify`
2009
2010			`endmodule`
2011
2012			`module LOGIC0_X1 (Z);`
2013
2014			`output Z;`
2015
2016			`buf(Z, 0);`
2017			`endmodule`
2018
2019			`module LOGIC1_X1 (Z);`
2020
2021			`output Z;`
2022
2023			`buf(Z, 1);`
2024			`endmodule`
2025
2026			`module MUX2_X1 (A, B, S, Z);`
2027
2028			`input A;`
2029			`input B;`
2030			`input S;`
2031			`output Z;`
2032
2033			`or(Z, i_38, i_39);`
2034			`and(i_38, S, B);`
2035			`and(i_39, A, i_40);`
2036			`not(i_40, S);`
2037
2038			`specify`
2039			`if((B == 1'b1) && (S == 1'b0)) (A => Z) = (0.1, 0.1);`
2040			`if((B == 1'b0) && (S == 1'b0)) (A => Z) = (0.1, 0.1);`
2041			`if((A == 1'b1) && (S == 1'b1)) (B => Z) = (0.1, 0.1);`
2042			`if((A == 1'b0) && (S == 1'b1)) (B => Z) = (0.1, 0.1);`
2043			`if((A == 1'b1) && (B == 1'b0)) (S => Z) = (0.1, 0.1);`
2044			`if((A == 1'b0) && (B == 1'b1)) (S => Z) = (0.1, 0.1);`
2045			`endspecify`
2046
2047			`endmodule`
2048
2049			`module MUX2_X2 (A, B, S, Z);`
2050
2051			`input A;`
2052			`input B;`
2053			`input S;`
2054			`output Z;`
2055
2056			`or(Z, i_58, i_59);`
2057			`and(i_58, S, B);`
2058			`and(i_59, A, i_60);`
2059			`not(i_60, S);`
2060
2061			`specify`
2062			`if((B == 1'b1) && (S == 1'b0)) (A => Z) = (0.1, 0.1);`
2063			`if((B == 1'b0) && (S == 1'b0)) (A => Z) = (0.1, 0.1);`
2064			`if((A == 1'b1) && (S == 1'b1)) (B => Z) = (0.1, 0.1);`
2065			`if((A == 1'b0) && (S == 1'b1)) (B => Z) = (0.1, 0.1);`
2066			`if((A == 1'b1) && (B == 1'b0)) (S => Z) = (0.1, 0.1);`
2067			`if((A == 1'b0) && (B == 1'b1)) (S => Z) = (0.1, 0.1);`
2068			`endspecify`
2069
2070			`endmodule`
2071
2072			`module NAND2_X1 (A1, A2, ZN);`
2073
2074			`input A1;`
2075			`input A2;`
2076			`output ZN;`
2077
2078			`not(ZN, i_6);`
2079			`and(i_6, A1, A2);`
2080
2081			`specify`
2082			`(A1 => ZN) = (0.1, 0.1);`
2083			`(A2 => ZN) = (0.1, 0.1);`
2084			`endspecify`
2085
2086			`endmodule`
2087
2088			`module NAND2_X2 (A1, A2, ZN);`
2089
2090			`input A1;`
2091			`input A2;`
2092			`output ZN;`
2093
2094			`not(ZN, i_6);`
2095			`and(i_6, A1, A2);`
2096
2097			`specify`
2098			`(A1 => ZN) = (0.1, 0.1);`
2099			`(A2 => ZN) = (0.1, 0.1);`
2100			`endspecify`
2101
2102			`endmodule`
2103
2104			`module NAND2_X4 (A1, A2, ZN);`
2105
2106			`input A1;`
2107			`input A2;`
2108			`output ZN;`
2109
2110			`not(ZN, i_6);`
2111			`and(i_6, A1, A2);`
2112
2113			`specify`
2114			`(A1 => ZN) = (0.1, 0.1);`
2115			`(A2 => ZN) = (0.1, 0.1);`
2116			`endspecify`
2117
2118			`endmodule`
2119
2120			`module NAND3_X1 (A1, A2, A3, ZN);`
2121
2122			`input A1;`
2123			`input A2;`
2124			`input A3;`
2125			`output ZN;`
2126
2127			`not(ZN, i_32);`
2128			`and(i_32, i_33, A3);`
2129			`and(i_33, A1, A2);`
2130
2131			`specify`
2132			`(A1 => ZN) = (0.1, 0.1);`
2133			`(A2 => ZN) = (0.1, 0.1);`
2134			`(A3 => ZN) = (0.1, 0.1);`
2135			`endspecify`
2136
2137			`endmodule`
2138
2139			`module NAND3_X2 (A1, A2, A3, ZN);`
2140
2141			`input A1;`
2142			`input A2;`
2143			`input A3;`
2144			`output ZN;`
2145
2146			`not(ZN, i_32);`
2147			`and(i_32, i_33, A3);`
2148			`and(i_33, A1, A2);`
2149
2150			`specify`
2151			`(A1 => ZN) = (0.1, 0.1);`
2152			`(A2 => ZN) = (0.1, 0.1);`
2153			`(A3 => ZN) = (0.1, 0.1);`
2154			`endspecify`
2155
2156			`endmodule`
2157
2158			`module NAND3_X4 (A1, A2, A3, ZN);`
2159
2160			`input A1;`
2161			`input A2;`
2162			`input A3;`
2163			`output ZN;`
2164
2165			`not(ZN, i_12);`
2166			`and(i_12, i_13, A3);`
2167			`and(i_13, A1, A2);`
2168
2169			`specify`
2170			`(A1 => ZN) = (0.1, 0.1);`
2171			`(A2 => ZN) = (0.1, 0.1);`
2172			`(A3 => ZN) = (0.1, 0.1);`
2173			`endspecify`
2174
2175			`endmodule`
2176
2177			`module NAND4_X1 (A1, A2, A3, A4, ZN);`
2178
2179			`input A1;`
2180			`input A2;`
2181			`input A3;`
2182			`input A4;`
2183			`output ZN;`
2184
2185			`not(ZN, i_18);`
2186			`and(i_18, i_19, A4);`
2187			`and(i_19, i_20, A3);`
2188			`and(i_20, A1, A2);`
2189
2190			`specify`
2191			`(A1 => ZN) = (0.1, 0.1);`
2192			`(A2 => ZN) = (0.1, 0.1);`
2193			`(A3 => ZN) = (0.1, 0.1);`
2194			`(A4 => ZN) = (0.1, 0.1);`
2195			`endspecify`
2196
2197			`endmodule`
2198
2199			`module NAND4_X2 (A1, A2, A3, A4, ZN);`
2200
2201			`input A1;`
2202			`input A2;`
2203			`input A3;`
2204			`input A4;`
2205			`output ZN;`
2206
2207			`not(ZN, i_18);`
2208			`and(i_18, i_19, A4);`
2209			`and(i_19, i_20, A3);`
2210			`and(i_20, A1, A2);`
2211
2212			`specify`
2213			`(A1 => ZN) = (0.1, 0.1);`
2214			`(A2 => ZN) = (0.1, 0.1);`
2215			`(A3 => ZN) = (0.1, 0.1);`
2216			`(A4 => ZN) = (0.1, 0.1);`
2217			`endspecify`
2218
2219			`endmodule`
2220
2221			`module NAND4_X4 (A1, A2, A3, A4, ZN);`
2222
2223			`input A1;`
2224			`input A2;`
2225			`input A3;`
2226			`input A4;`
2227			`output ZN;`
2228
2229			`not(ZN, i_18);`
2230			`and(i_18, i_19, A4);`
2231			`and(i_19, i_20, A3);`
2232			`and(i_20, A1, A2);`
2233
2234			`specify`
2235			`(A1 => ZN) = (0.1, 0.1);`
2236			`(A2 => ZN) = (0.1, 0.1);`
2237			`(A3 => ZN) = (0.1, 0.1);`
2238			`(A4 => ZN) = (0.1, 0.1);`
2239			`endspecify`
2240
2241			`endmodule`
2242
2243			`module NOR2_X1 (A1, A2, ZN);`
2244
2245			`input A1;`
2246			`input A2;`
2247			`output ZN;`
2248
2249			`not(ZN, i_66);`
2250			`or(i_66, A1, A2);`
2251
2252			`specify`
2253			`(A1 => ZN) = (0.1, 0.1);`
2254			`(A2 => ZN) = (0.1, 0.1);`
2255			`endspecify`
2256
2257			`endmodule`
2258
2259			`module NOR2_X2 (A1, A2, ZN);`
2260
2261			`input A1;`
2262			`input A2;`
2263			`output ZN;`
2264
2265			`not(ZN, i_46);`
2266			`or(i_46, A1, A2);`
2267
2268			`specify`
2269			`(A1 => ZN) = (0.1, 0.1);`
2270			`(A2 => ZN) = (0.1, 0.1);`
2271			`endspecify`
2272
2273			`endmodule`
2274
2275			`module NOR2_X4 (A1, A2, ZN);`
2276
2277			`input A1;`
2278			`input A2;`
2279			`output ZN;`
2280
2281			`not(ZN, i_66);`
2282			`or(i_66, A1, A2);`
2283
2284			`specify`
2285			`(A1 => ZN) = (0.1, 0.1);`
2286			`(A2 => ZN) = (0.1, 0.1);`
2287			`endspecify`
2288
2289			`endmodule`
2290
2291			`module NOR3_X1 (A1, A2, A3, ZN);`
2292
2293			`input A1;`
2294			`input A2;`
2295			`input A3;`
2296			`output ZN;`
2297
2298			`not(ZN, i_12);`
2299			`or(i_12, i_13, A3);`
2300			`or(i_13, A1, A2);`
2301
2302			`specify`
2303			`(A1 => ZN) = (0.1, 0.1);`
2304			`(A2 => ZN) = (0.1, 0.1);`
2305			`(A3 => ZN) = (0.1, 0.1);`
2306			`endspecify`
2307
2308			`endmodule`
2309
2310			`module NOR3_X2 (A1, A2, A3, ZN);`
2311
2312			`input A1;`
2313			`input A2;`
2314			`input A3;`
2315			`output ZN;`
2316
2317			`not(ZN, i_12);`
2318			`or(i_12, i_13, A3);`
2319			`or(i_13, A1, A2);`
2320
2321			`specify`
2322			`(A1 => ZN) = (0.1, 0.1);`
2323			`(A2 => ZN) = (0.1, 0.1);`
2324			`(A3 => ZN) = (0.1, 0.1);`
2325			`endspecify`
2326
2327			`endmodule`
2328
2329			`module NOR3_X4 (A1, A2, A3, ZN);`
2330
2331			`input A1;`
2332			`input A2;`
2333			`input A3;`
2334			`output ZN;`
2335
2336			`not(ZN, i_12);`
2337			`or(i_12, i_13, A3);`
2338			`or(i_13, A1, A2);`
2339
2340			`specify`
2341			`(A1 => ZN) = (0.1, 0.1);`
2342			`(A2 => ZN) = (0.1, 0.1);`
2343			`(A3 => ZN) = (0.1, 0.1);`
2344			`endspecify`
2345
2346			`endmodule`
2347
2348			`module NOR4_X1 (A1, A2, A3, A4, ZN);`
2349
2350			`input A1;`
2351			`input A2;`
2352			`input A3;`
2353			`input A4;`
2354			`output ZN;`
2355
2356			`not(ZN, i_18);`
2357			`or(i_18, i_19, A4);`
2358			`or(i_19, i_20, A3);`
2359			`or(i_20, A1, A2);`
2360
2361			`specify`
2362			`(A1 => ZN) = (0.1, 0.1);`
2363			`(A2 => ZN) = (0.1, 0.1);`
2364			`(A3 => ZN) = (0.1, 0.1);`
2365			`(A4 => ZN) = (0.1, 0.1);`
2366			`endspecify`
2367
2368			`endmodule`
2369
2370			`module NOR4_X2 (A1, A2, A3, A4, ZN);`
2371
2372			`input A1;`
2373			`input A2;`
2374			`input A3;`
2375			`input A4;`
2376			`output ZN;`
2377
2378			`not(ZN, i_18);`
2379			`or(i_18, i_19, A4);`
2380			`or(i_19, i_20, A3);`
2381			`or(i_20, A1, A2);`
2382
2383			`specify`
2384			`(A1 => ZN) = (0.1, 0.1);`
2385			`(A2 => ZN) = (0.1, 0.1);`
2386			`(A3 => ZN) = (0.1, 0.1);`
2387			`(A4 => ZN) = (0.1, 0.1);`
2388			`endspecify`
2389
2390			`endmodule`
2391
2392			`module NOR4_X4 (A1, A2, A3, A4, ZN);`
2393
2394			`input A1;`
2395			`input A2;`
2396			`input A3;`
2397			`input A4;`
2398			`output ZN;`
2399
2400			`not(ZN, i_18);`
2401			`or(i_18, i_19, A4);`
2402			`or(i_19, i_20, A3);`
2403			`or(i_20, A1, A2);`
2404
2405			`specify`
2406			`(A1 => ZN) = (0.1, 0.1);`
2407			`(A2 => ZN) = (0.1, 0.1);`
2408			`(A3 => ZN) = (0.1, 0.1);`
2409			`(A4 => ZN) = (0.1, 0.1);`
2410			`endspecify`
2411
2412			`endmodule`
2413
2414			`module OAI211_X1 (A, B, C1, C2, ZN);`
2415
2416			`input A;`
2417			`input B;`
2418			`input C1;`
2419			`input C2;`
2420			`output ZN;`
2421
2422			`not(ZN, i_18);`
2423			`and(i_18, i_19, B);`
2424			`and(i_19, i_20, A);`
2425			`or(i_20, C1, C2);`
2426
2427			`specify`
2428			`if((B == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
2429			`if((B == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
2430			`if((B == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
2431			`if((A == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B => ZN) = (0.1, 0.1);`
2432			`if((A == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B => ZN) = (0.1, 0.1);`
2433			`if((A == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (B => ZN) = (0.1, 0.1);`
2434			`(C1 => ZN) = (0.1, 0.1);`
2435			`(C2 => ZN) = (0.1, 0.1);`
2436			`endspecify`
2437
2438			`endmodule`
2439
2440			`module OAI211_X2 (A, B, C1, C2, ZN);`
2441
2442			`input A;`
2443			`input B;`
2444			`input C1;`
2445			`input C2;`
2446			`output ZN;`
2447
2448			`not(ZN, i_18);`
2449			`and(i_18, i_19, B);`
2450			`and(i_19, i_20, A);`
2451			`or(i_20, C1, C2);`
2452
2453			`specify`
2454			`if((B == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
2455			`if((B == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
2456			`if((B == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
2457			`if((A == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B => ZN) = (0.1, 0.1);`
2458			`if((A == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B => ZN) = (0.1, 0.1);`
2459			`if((A == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (B => ZN) = (0.1, 0.1);`
2460			`(C1 => ZN) = (0.1, 0.1);`
2461			`(C2 => ZN) = (0.1, 0.1);`
2462			`endspecify`
2463
2464			`endmodule`
2465
2466			`module OAI211_X4 (A, B, C1, C2, ZN);`
2467
2468			`input A;`
2469			`input B;`
2470			`input C1;`
2471			`input C2;`
2472			`output ZN;`
2473
2474			`not(ZN, i_18);`
2475			`and(i_18, i_19, B);`
2476			`and(i_19, i_20, A);`
2477			`or(i_20, C1, C2);`
2478
2479			`specify`
2480			`if((B == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
2481			`if((B == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
2482			`if((B == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
2483			`if((A == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B => ZN) = (0.1, 0.1);`
2484			`if((A == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B => ZN) = (0.1, 0.1);`
2485			`if((A == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (B => ZN) = (0.1, 0.1);`
2486			`(C1 => ZN) = (0.1, 0.1);`
2487			`(C2 => ZN) = (0.1, 0.1);`
2488			`endspecify`
2489
2490			`endmodule`
2491
2492			`module OAI21_X1 (A, B1, B2, ZN);`
2493
2494			`input A;`
2495			`input B1;`
2496			`input B2;`
2497			`output ZN;`
2498
2499			`not(ZN, i_12);`
2500			`and(i_12, A, i_13);`
2501			`or(i_13, B1, B2);`
2502
2503			`specify`
2504			`if((B1 == 1'b1) && (B2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
2505			`if((B1 == 1'b0) && (B2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
2506			`if((B1 == 1'b1) && (B2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
2507			`(B1 => ZN) = (0.1, 0.1);`
2508			`(B2 => ZN) = (0.1, 0.1);`
2509			`endspecify`
2510
2511			`endmodule`
2512
2513			`module OAI21_X2 (A, B1, B2, ZN);`
2514
2515			`input A;`
2516			`input B1;`
2517			`input B2;`
2518			`output ZN;`
2519
2520			`not(ZN, i_12);`
2521			`and(i_12, A, i_13);`
2522			`or(i_13, B1, B2);`
2523
2524			`specify`
2525			`if((B1 == 1'b1) && (B2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
2526			`if((B1 == 1'b0) && (B2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
2527			`if((B1 == 1'b1) && (B2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
2528			`(B1 => ZN) = (0.1, 0.1);`
2529			`(B2 => ZN) = (0.1, 0.1);`
2530			`endspecify`
2531
2532			`endmodule`
2533
2534			`module OAI21_X4 (A, B1, B2, ZN);`
2535
2536			`input A;`
2537			`input B1;`
2538			`input B2;`
2539			`output ZN;`
2540
2541			`not(ZN, i_12);`
2542			`and(i_12, A, i_13);`
2543			`or(i_13, B1, B2);`
2544
2545			`specify`
2546			`if((B1 == 1'b1) && (B2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
2547			`if((B1 == 1'b0) && (B2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
2548			`if((B1 == 1'b1) && (B2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
2549			`(B1 => ZN) = (0.1, 0.1);`
2550			`(B2 => ZN) = (0.1, 0.1);`
2551			`endspecify`
2552
2553			`endmodule`
2554
2555			`module OAI221_X1 (A, B1, B2, C1, C2, ZN);`
2556
2557			`input A;`
2558			`input B1;`
2559			`input B2;`
2560			`input C1;`
2561			`input C2;`
2562			`output ZN;`
2563
2564			`not(ZN, i_24);`
2565			`and(i_24, i_25, i_27);`
2566			`and(i_25, i_26, A);`
2567			`or(i_26, C1, C2);`
2568			`or(i_27, B1, B2);`
2569
2570			`specify`
2571			`(A => ZN) = (0.1, 0.1);`
2572			`if((B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
2573			`if((B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
2574			`if((B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) \|\| (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b1) \|\| (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
2575			`if((A == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
2576			`if((A == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
2577			`if((A == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
2578			`if((A == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
2579			`if((A == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
2580			`if((A == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
2581			`if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2582			`if((A == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2583			`if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2584			`if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2585			`if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2586			`if((A == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2587			`endspecify`
2588
2589			`endmodule`
2590
2591			`module OAI221_X2 (A, B1, B2, C1, C2, ZN);`
2592
2593			`input A;`
2594			`input B1;`
2595			`input B2;`
2596			`input C1;`
2597			`input C2;`
2598			`output ZN;`
2599
2600			`not(ZN, i_24);`
2601			`and(i_24, i_25, i_27);`
2602			`and(i_25, i_26, A);`
2603			`or(i_26, C1, C2);`
2604			`or(i_27, B1, B2);`
2605
2606			`specify`
2607			`(A => ZN) = (0.1, 0.1);`
2608			`if((B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
2609			`if((B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
2610			`if((B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) \|\| (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b1) \|\| (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
2611			`if((A == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
2612			`if((A == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
2613			`if((A == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
2614			`if((A == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
2615			`if((A == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
2616			`if((A == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
2617			`if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2618			`if((A == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2619			`if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2620			`if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2621			`if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2622			`if((A == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2623			`endspecify`
2624
2625			`endmodule`
2626
2627			`module OAI221_X4 (A, B1, B2, C1, C2, ZN);`
2628
2629			`input A;`
2630			`input B1;`
2631			`input B2;`
2632			`input C1;`
2633			`input C2;`
2634			`output ZN;`
2635
2636			`not(ZN, i_24);`
2637			`and(i_24, i_25, i_27);`
2638			`and(i_25, i_26, A);`
2639			`or(i_26, C1, C2);`
2640			`or(i_27, B1, B2);`
2641
2642			`specify`
2643			`(A => ZN) = (0.1, 0.1);`
2644			`if((B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
2645			`if((B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1);`
2646			`if((B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) \|\| (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b1) \|\| (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1);`
2647			`if((A == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
2648			`if((A == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
2649			`if((A == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
2650			`if((A == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
2651			`if((A == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
2652			`if((A == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
2653			`if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2654			`if((A == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2655			`if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2656			`if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2657			`if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2658			`if((A == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2659			`endspecify`
2660
2661			`endmodule`
2662
2663			`module OAI222_X1 (A1, A2, B1, B2, C1, C2, ZN);`
2664
2665			`input A1;`
2666			`input A2;`
2667			`input B1;`
2668			`input B2;`
2669			`input C1;`
2670			`input C2;`
2671			`output ZN;`
2672
2673			`not(ZN, i_30);`
2674			`and(i_30, i_31, i_34);`
2675			`and(i_31, i_32, i_33);`
2676			`or(i_32, A1, A2);`
2677			`or(i_33, B1, B2);`
2678			`or(i_34, C1, C2);`
2679
2680			`specify`
2681			`(A1 => ZN) = (0.1, 0.1);`
2682			`if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
2683			`if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
2684			`if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) \|\| (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b1) \|\| (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
2685			`(A2 => ZN) = (0.1, 0.1);`
2686			`if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) \|\| (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
2687			`if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
2688			`if((A1 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
2689			`(B1 => ZN) = (0.1, 0.1);`
2690			`if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
2691			`if((A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
2692			`if((A1 == 1'b1) && (A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) \|\| (A1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1) \|\| (A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
2693			`(B2 => ZN) = (0.1, 0.1);`
2694			`if((A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
2695			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
2696			`if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) \|\| (A1 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1) \|\| (A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
2697			`(C1 => ZN) = (0.1, 0.1);`
2698			`if((A1 == 1'b1) && (B1 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2699			`if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2700			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2701			`if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2702			`(C2 => ZN) = (0.1, 0.1);`
2703			`if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b1) && (C1 == 1'b0) \|\| (A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2704			`if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2705			`if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2706			`if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2707			`endspecify`
2708
2709			`endmodule`
2710
2711			`module OAI222_X2 (A1, A2, B1, B2, C1, C2, ZN);`
2712
2713			`input A1;`
2714			`input A2;`
2715			`input B1;`
2716			`input B2;`
2717			`input C1;`
2718			`input C2;`
2719			`output ZN;`
2720
2721			`not(ZN, i_30);`
2722			`and(i_30, i_31, i_34);`
2723			`and(i_31, i_32, i_33);`
2724			`or(i_32, A1, A2);`
2725			`or(i_33, B1, B2);`
2726			`or(i_34, C1, C2);`
2727
2728			`specify`
2729			`(A1 => ZN) = (0.1, 0.1);`
2730			`if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
2731			`if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
2732			`if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) \|\| (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b1) \|\| (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
2733			`(A2 => ZN) = (0.1, 0.1);`
2734			`if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) \|\| (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
2735			`if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
2736			`if((A1 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
2737			`(B1 => ZN) = (0.1, 0.1);`
2738			`if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
2739			`if((A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
2740			`if((A1 == 1'b1) && (A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) \|\| (A1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1) \|\| (A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
2741			`(B2 => ZN) = (0.1, 0.1);`
2742			`if((A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
2743			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
2744			`if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) \|\| (A1 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1) \|\| (A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
2745			`(C1 => ZN) = (0.1, 0.1);`
2746			`if((A1 == 1'b1) && (B1 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2747			`if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2748			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2749			`if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2750			`(C2 => ZN) = (0.1, 0.1);`
2751			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2752			`if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b1) && (C1 == 1'b0) \|\| (A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2753			`if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2754			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2755			`endspecify`
2756
2757			`endmodule`
2758
2759			`module OAI222_X4 (A1, A2, B1, B2, C1, C2, ZN);`
2760
2761			`input A1;`
2762			`input A2;`
2763			`input B1;`
2764			`input B2;`
2765			`input C1;`
2766			`input C2;`
2767			`output ZN;`
2768
2769			`not(ZN, i_30);`
2770			`and(i_30, i_31, i_34);`
2771			`and(i_31, i_32, i_33);`
2772			`or(i_32, A1, A2);`
2773			`or(i_33, B1, B2);`
2774			`or(i_34, C1, C2);`
2775
2776			`specify`
2777			`(A1 => ZN) = (0.1, 0.1);`
2778			`if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
2779			`if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) \|\| (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b1) \|\| (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1) \|\| (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
2780			`if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A1 => ZN) = (0.1, 0.1);`
2781			`(A2 => ZN) = (0.1, 0.1);`
2782			`if((A1 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A2 => ZN) = (0.1, 0.1);`
2783			`if((A1 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
2784			`if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) \|\| (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1) \|\| (A1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
2785			`(B1 => ZN) = (0.1, 0.1);`
2786			`if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
2787			`if((A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
2788			`if((A1 == 1'b1) && (A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) \|\| (A1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1) \|\| (A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1);`
2789			`(B2 => ZN) = (0.1, 0.1);`
2790			`if((A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
2791			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
2792			`if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) \|\| (A1 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1) \|\| (A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1);`
2793			`(C1 => ZN) = (0.1, 0.1);`
2794			`if((A1 == 1'b1) && (B1 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2795			`if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2796			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b0) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2797			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1);`
2798			`(C2 => ZN) = (0.1, 0.1);`
2799			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2800			`if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b1) && (C1 == 1'b0) \|\| (A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2801			`if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2802			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) \|\| (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1);`
2803			`endspecify`
2804
2805			`endmodule`
2806
2807			`module OAI22_X1 (A1, A2, B1, B2, ZN);`
2808
2809			`input A1;`
2810			`input A2;`
2811			`input B1;`
2812			`input B2;`
2813			`output ZN;`
2814
2815			`not(ZN, i_18);`
2816			`and(i_18, i_19, i_20);`
2817			`or(i_19, A1, A2);`
2818			`or(i_20, B1, B2);`
2819
2820			`specify`
2821			`if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
2822			`if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0)) (A1 => ZN) = (0.1, 0.1);`
2823			`if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
2824			`if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
2825			`if((A1 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
2826			`if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0)) (A2 => ZN) = (0.1, 0.1);`
2827			`if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
2828			`if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
2829			`if((A1 == 1'b1) && (A2 == 1'b1) && (B2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
2830			`if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
2831			`if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
2832			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
2833			`endspecify`
2834
2835			`endmodule`
2836
2837			`module OAI22_X2 (A1, A2, B1, B2, ZN);`
2838
2839			`input A1;`
2840			`input A2;`
2841			`input B1;`
2842			`input B2;`
2843			`output ZN;`
2844
2845			`not(ZN, i_18);`
2846			`and(i_18, i_19, i_20);`
2847			`or(i_19, A1, A2);`
2848			`or(i_20, B1, B2);`
2849
2850			`specify`
2851			`if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
2852			`if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0)) (A1 => ZN) = (0.1, 0.1);`
2853			`if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
2854			`if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
2855			`if((A1 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
2856			`if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0)) (A2 => ZN) = (0.1, 0.1);`
2857			`if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
2858			`if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
2859			`if((A1 == 1'b1) && (A2 == 1'b1) && (B2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
2860			`if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
2861			`if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
2862			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
2863			`endspecify`
2864
2865			`endmodule`
2866
2867			`module OAI22_X4 (A1, A2, B1, B2, ZN);`
2868
2869			`input A1;`
2870			`input A2;`
2871			`input B1;`
2872			`input B2;`
2873			`output ZN;`
2874
2875			`not(ZN, i_18);`
2876			`and(i_18, i_19, i_20);`
2877			`or(i_19, A1, A2);`
2878			`or(i_20, B1, B2);`
2879
2880			`specify`
2881			`if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
2882			`if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0)) (A1 => ZN) = (0.1, 0.1);`
2883			`if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
2884			`if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
2885			`if((A1 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
2886			`if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0)) (A2 => ZN) = (0.1, 0.1);`
2887			`if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
2888			`if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
2889			`if((A1 == 1'b1) && (A2 == 1'b1) && (B2 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
2890			`if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
2891			`if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
2892			`if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
2893			`endspecify`
2894
2895			`endmodule`
2896
2897			`module OAI33_X1 (A1, A2, A3, B1, B2, B3, ZN);`
2898
2899			`input A1;`
2900			`input A2;`
2901			`input A3;`
2902			`input B1;`
2903			`input B2;`
2904			`input B3;`
2905			`output ZN;`
2906
2907			`not(ZN, i_30);`
2908			`and(i_30, i_31, i_33);`
2909			`or(i_31, i_32, A3);`
2910			`or(i_32, A1, A2);`
2911			`or(i_33, i_34, B3);`
2912			`or(i_34, B1, B2);`
2913
2914			`specify`
2915			`(A1 => ZN) = (0.1, 0.1);`
2916			`if((A2 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (B3 == 1'b0) \|\| (A2 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (B3 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
2917			`if((A2 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (B3 == 1'b0)) (A1 => ZN) = (0.1, 0.1);`
2918			`if((A2 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (B3 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
2919			`if((A2 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) \|\| (A2 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b1) && (B3 == 1'b1)) (A1 => ZN) = (0.1, 0.1);`
2920			`(A2 => ZN) = (0.1, 0.1);`
2921			`if((A1 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (B3 == 1'b0) \|\| (A1 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (B3 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
2922			`if((A1 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (B3 == 1'b0)) (A2 => ZN) = (0.1, 0.1);`
2923			`if((A1 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) \|\| (A1 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b1) && (B3 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
2924			`if((A1 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (B3 == 1'b1)) (A2 => ZN) = (0.1, 0.1);`
2925			`(A3 => ZN) = (0.1, 0.1);`
2926			`if((A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (B3 == 1'b1)) (A3 => ZN) = (0.1, 0.1);`
2927			`if((A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) \|\| (A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b1) && (B3 == 1'b1)) (A3 => ZN) = (0.1, 0.1);`
2928			`if((A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (B3 == 1'b0)) (A3 => ZN) = (0.1, 0.1);`
2929			`if((A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (B3 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (B3 == 1'b1)) (A3 => ZN) = (0.1, 0.1);`
2930			`(B1 => ZN) = (0.1, 0.1);`
2931			`if((A1 == 1'b0) && (A2 == 1'b1) && (A3 == 1'b0) && (B2 == 1'b0) && (B3 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b0) && (A3 == 1'b1) && (B2 == 1'b0) && (B3 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
2932			`if((A1 == 1'b0) && (A2 == 1'b1) && (A3 == 1'b1) && (B2 == 1'b0) && (B3 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
2933			`if((A1 == 1'b1) && (B2 == 1'b0) && (B3 == 1'b0)) (B1 => ZN) = (0.1, 0.1);`
2934			`(B2 => ZN) = (0.1, 0.1);`
2935			`if((A1 == 1'b0) && (A2 == 1'b1) && (A3 == 1'b1) && (B1 == 1'b0) && (B3 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
2936			`if((A1 == 1'b1) && (B1 == 1'b0) && (B3 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
2937			`if((A1 == 1'b0) && (A2 == 1'b1) && (A3 == 1'b0) && (B1 == 1'b0) && (B3 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b0) && (A3 == 1'b1) && (B1 == 1'b0) && (B3 == 1'b0)) (B2 => ZN) = (0.1, 0.1);`
2938			`(B3 => ZN) = (0.1, 0.1);`
2939			`if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0)) (B3 => ZN) = (0.1, 0.1);`
2940			`if((A1 == 1'b0) && (A2 == 1'b1) && (A3 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) \|\| (A1 == 1'b0) && (A2 == 1'b0) && (A3 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0)) (B3 => ZN) = (0.1, 0.1);`
2941			`if((A1 == 1'b0) && (A2 == 1'b1) && (A3 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0)) (B3 => ZN) = (0.1, 0.1);`
2942			`endspecify`
2943
2944			`endmodule`
2945
2946			`module OR2_X1 (A1, A2, ZN);`
2947
2948			`input A1;`
2949			`input A2;`
2950			`output ZN;`
2951
2952			`or(ZN, A1, A2);`
2953
2954			`specify`
2955			`(A1 => ZN) = (0.1, 0.1);`
2956			`(A2 => ZN) = (0.1, 0.1);`
2957			`endspecify`
2958
2959			`endmodule`
2960
2961			`module OR2_X2 (A1, A2, ZN);`
2962
2963			`input A1;`
2964			`input A2;`
2965			`output ZN;`
2966
2967			`or(ZN, A1, A2);`
2968
2969			`specify`
2970			`(A1 => ZN) = (0.1, 0.1);`
2971			`(A2 => ZN) = (0.1, 0.1);`
2972			`endspecify`
2973
2974			`endmodule`
2975
2976			`module OR2_X4 (A1, A2, ZN);`
2977
2978			`input A1;`
2979			`input A2;`
2980			`output ZN;`
2981
2982			`or(ZN, A1, A2);`
2983
2984			`specify`
2985			`(A1 => ZN) = (0.1, 0.1);`
2986			`(A2 => ZN) = (0.1, 0.1);`
2987			`endspecify`
2988
2989			`endmodule`
2990
2991			`module OR3_X1 (A1, A2, A3, ZN);`
2992
2993			`input A1;`
2994			`input A2;`
2995			`input A3;`
2996			`output ZN;`
2997
2998			`or(ZN, i_6, A3);`
2999			`or(i_6, A1, A2);`
3000
3001			`specify`
3002			`(A1 => ZN) = (0.1, 0.1);`
3003			`(A2 => ZN) = (0.1, 0.1);`
3004			`(A3 => ZN) = (0.1, 0.1);`
3005			`endspecify`
3006
3007			`endmodule`
3008
3009			`module OR3_X2 (A1, A2, A3, ZN);`
3010
3011			`input A1;`
3012			`input A2;`
3013			`input A3;`
3014			`output ZN;`
3015
3016			`or(ZN, i_6, A3);`
3017			`or(i_6, A1, A2);`
3018
3019			`specify`
3020			`(A1 => ZN) = (0.1, 0.1);`
3021			`(A2 => ZN) = (0.1, 0.1);`
3022			`(A3 => ZN) = (0.1, 0.1);`
3023			`endspecify`
3024
3025			`endmodule`
3026
3027			`module OR3_X4 (A1, A2, A3, ZN);`
3028
3029			`input A1;`
3030			`input A2;`
3031			`input A3;`
3032			`output ZN;`
3033
3034			`or(ZN, i_6, A3);`
3035			`or(i_6, A1, A2);`
3036
3037			`specify`
3038			`(A1 => ZN) = (0.1, 0.1);`
3039			`(A2 => ZN) = (0.1, 0.1);`
3040			`(A3 => ZN) = (0.1, 0.1);`
3041			`endspecify`
3042
3043			`endmodule`
3044
3045			`module OR4_X1 (A1, A2, A3, A4, ZN);`
3046
3047			`input A1;`
3048			`input A2;`
3049			`input A3;`
3050			`input A4;`
3051			`output ZN;`
3052
3053			`or(ZN, i_12, A4);`
3054			`or(i_12, i_13, A3);`
3055			`or(i_13, A1, A2);`
3056
3057			`specify`
3058			`(A1 => ZN) = (0.1, 0.1);`
3059			`(A2 => ZN) = (0.1, 0.1);`
3060			`(A3 => ZN) = (0.1, 0.1);`
3061			`(A4 => ZN) = (0.1, 0.1);`
3062			`endspecify`
3063
3064			`endmodule`
3065
3066			`module OR4_X2 (A1, A2, A3, A4, ZN);`
3067
3068			`input A1;`
3069			`input A2;`
3070			`input A3;`
3071			`input A4;`
3072			`output ZN;`
3073
3074			`or(ZN, i_12, A4);`
3075			`or(i_12, i_13, A3);`
3076			`or(i_13, A1, A2);`
3077
3078			`specify`
3079			`(A1 => ZN) = (0.1, 0.1);`
3080			`(A2 => ZN) = (0.1, 0.1);`
3081			`(A3 => ZN) = (0.1, 0.1);`
3082			`(A4 => ZN) = (0.1, 0.1);`
3083			`endspecify`
3084
3085			`endmodule`
3086
3087			`module OR4_X4 (A1, A2, A3, A4, ZN);`
3088
3089			`input A1;`
3090			`input A2;`
3091			`input A3;`
3092			`input A4;`
3093			`output ZN;`
3094
3095			`or(ZN, i_12, A4);`
3096			`or(i_12, i_13, A3);`
3097			`or(i_13, A1, A2);`
3098
3099			`specify`
3100			`(A1 => ZN) = (0.1, 0.1);`
3101			`(A2 => ZN) = (0.1, 0.1);`
3102			`(A3 => ZN) = (0.1, 0.1);`
3103			`(A4 => ZN) = (0.1, 0.1);`
3104			`endspecify`
3105
3106			`endmodule`
3107
3108			`primitive seq3 (IQ, SN, RN, nextstate, CK, NOTIFIER);`
3109			`output IQ;`
3110			`input SN;`
3111			`input RN;`
3112			`input nextstate;`
3113			`input CK;`
3114			`input NOTIFIER;`
3115			`reg IQ;`
3116
3117			`table`
3118			`// SN RN nextstate CK NOTIFIER : @IQ : IQ`
3119			`1 ? 0 r ? : ? : 0;`
3120			`? 1 1 r ? : ? : 1;`
3121			`1 ? 0 * ? : 0 : 0; // reduce pessimism`
3122			`? 1 1 * ? : 1 : 1; // reduce pessimism`
3123			`1 1 * ? ? : ? : -; // Ignore all edges on nextstate`
3124			`1 1 ? f ? : ? : -; // Ignore non-triggering clock edge`
3125
3126			`* 1 ? ? ? : 1 : 1; // Cover all transitions on SN`
3127			`? 0 ? ? ? : ? : 0; // RN activated`
3128			`1 * ? ? ? : 0 : 0; // Cover all transitions on RN`
3129			`? ? ? ? * : ? : x; // Any NOTIFIER change`
3130			`endtable`
3131			`endprimitive`
3132
3133			`module SDFFRS_X1 (CK, D, RN, SE, SI, SN, Q, QN);`
3134
3135			`input CK;`
3136			`input D;`
3137			`input RN;`
3138			`input SE;`
3139			`input SI;`
3140			`input SN;`
3141			`output Q;`
3142			`output QN;`
3143			`reg NOTIFIER;`
3144
3145			`seq3(IQ, SN, RN, nextstate, CK, NOTIFIER);`
3146			`and(IQN, i_33, i_34);`
3147			`not(i_33, IQ);`
3148			`not(i_34, i_35);`
3149			`and(i_35, i_36, i_37);`
3150			`not(i_36, SN);`
3151			`not(i_37, RN);`
3152			`buf(Q, IQ);`
3153			`buf(QN, IQN);`
3154			`or(nextstate, i_38, i_39);`
3155			`and(i_38, SE, SI);`
3156			`and(i_39, D, i_40);`
3157			`not(i_40, SE);`
3158
3159			`and(id_3, SN, RN);`
3160
3161			`specify`
3162			`(posedge CK => (Q +: D)) = (0.1, 0.1);`
3163			`if((CK == 1'b1) && (SN == 1'b0)) (RN => Q) = (0.1, 0.1);`
3164			`if((CK == 1'b0) && (SN == 1'b0)) (RN => Q) = (0.1, 0.1);`
3165			`if((CK == 1'b1) && (SN == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);`
3166			`if((CK == 1'b0) && (SN == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);`
3167			`if((CK == 1'b1) && (RN == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);`
3168			`if((CK == 1'b0) && (RN == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);`
3169			`(posedge CK => (QN -: D)) = (0.1, 0.1);`
3170			`if((CK == 1'b1) && (SN == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1);`
3171			`if((CK == 1'b0) && (SN == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1);`
3172			`if((CK == 1'b1) && (RN == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);`
3173			`if((CK == 1'b1) && (RN == 1'b0)) (SN => QN) = (0.1, 0.1);`
3174			`if((CK == 1'b0) && (RN == 1'b0)) (SN => QN) = (0.1, 0.1);`
3175			`if((CK == 1'b0) && (RN == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);`
3176
3177			`$width(negedge CK &&& id_3, 0.1, 0, NOTIFIER);`
3178			`$width(posedge CK &&& id_3, 0.1, 0, NOTIFIER);`
3179			`$setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER);`
3180			`$setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER);`
3181			`$width(negedge D, 0.1, 0, NOTIFIER);`
3182			`$width(posedge D, 0.1, 0, NOTIFIER);`
3183			`$recovery(posedge RN, posedge CK, 0.1, NOTIFIER);`
3184			`$hold(posedge CK, posedge RN, 0.1, NOTIFIER);`
3185			`$width(negedge RN, 0.1, 0, NOTIFIER);`
3186			`$width(posedge RN, 0.1, 0, NOTIFIER);`
3187			`$setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER);`
3188			`$setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER);`
3189			`$width(negedge SE, 0.1, 0, NOTIFIER);`
3190			`$width(posedge SE, 0.1, 0, NOTIFIER);`
3191			`$setuphold(posedge CK, negedge SI, 0.1, 0.1, NOTIFIER);`
3192			`$setuphold(posedge CK, posedge SI, 0.1, 0.1, NOTIFIER);`
3193			`$width(negedge SI, 0.1, 0, NOTIFIER);`
3194			`$width(posedge SI, 0.1, 0, NOTIFIER);`
3195			`$recovery(posedge SN, posedge CK, 0.1, NOTIFIER);`
3196			`$hold(posedge CK, posedge SN, 0.1, NOTIFIER);`
3197			`$width(negedge SN, 0.1, 0, NOTIFIER);`
3198			`$width(posedge SN, 0.1, 0, NOTIFIER);`
3199			`endspecify`
3200
3201			`endmodule`
3202
3203			`primitive seq3 (IQ, SN, RN, nextstate, CK, NOTIFIER);`
3204			`output IQ;`
3205			`input SN;`
3206			`input RN;`
3207			`input nextstate;`
3208			`input CK;`
3209			`input NOTIFIER;`
3210			`reg IQ;`
3211
3212			`table`
3213			`// SN RN nextstate CK NOTIFIER : @IQ : IQ`
3214			`1 ? 0 r ? : ? : 0;`
3215			`? 1 1 r ? : ? : 1;`
3216			`1 ? 0 * ? : 0 : 0; // reduce pessimism`
3217			`? 1 1 * ? : 1 : 1; // reduce pessimism`
3218			`1 1 * ? ? : ? : -; // Ignore all edges on nextstate`
3219			`1 1 ? f ? : ? : -; // Ignore non-triggering clock edge`
3220
3221			`* 1 ? ? ? : 1 : 1; // Cover all transitions on SN`
3222			`? 0 ? ? ? : ? : 0; // RN activated`
3223			`1 * ? ? ? : 0 : 0; // Cover all transitions on RN`
3224			`? ? ? ? * : ? : x; // Any NOTIFIER change`
3225			`endtable`
3226			`endprimitive`
3227
3228			`module SDFFRS_X2 (CK, D, RN, SE, SI, SN, Q, QN);`
3229
3230			`input CK;`
3231			`input D;`
3232			`input RN;`
3233			`input SE;`
3234			`input SI;`
3235			`input SN;`
3236			`output Q;`
3237			`output QN;`
3238			`reg NOTIFIER;`
3239
3240			`seq3(IQ, SN, RN, nextstate, CK, NOTIFIER);`
3241			`and(IQN, i_33, i_34);`
3242			`not(i_33, IQ);`
3243			`not(i_34, i_35);`
3244			`and(i_35, i_36, i_37);`
3245			`not(i_36, SN);`
3246			`not(i_37, RN);`
3247			`buf(Q, IQ);`
3248			`buf(QN, IQN);`
3249			`or(nextstate, i_38, i_39);`
3250			`and(i_38, SE, SI);`
3251			`and(i_39, D, i_40);`
3252			`not(i_40, SE);`
3253
3254			`and(id_3, SN, RN);`
3255
3256			`specify`
3257			`(posedge CK => (Q +: D)) = (0.1, 0.1);`
3258			`if((CK == 1'b1) && (SN == 1'b0)) (RN => Q) = (0.1, 0.1);`
3259			`if((CK == 1'b0) && (SN == 1'b0)) (RN => Q) = (0.1, 0.1);`
3260			`if((CK == 1'b1) && (SN == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);`
3261			`if((CK == 1'b0) && (SN == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);`
3262			`if((CK == 1'b1) && (RN == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);`
3263			`if((CK == 1'b0) && (RN == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);`
3264			`(posedge CK => (QN -: D)) = (0.1, 0.1);`
3265			`if((CK == 1'b1) && (SN == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1);`
3266			`if((CK == 1'b0) && (SN == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1);`
3267			`if((CK == 1'b1) && (RN == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);`
3268			`if((CK == 1'b1) && (RN == 1'b0)) (SN => QN) = (0.1, 0.1);`
3269			`if((CK == 1'b0) && (RN == 1'b0)) (SN => QN) = (0.1, 0.1);`
3270			`if((CK == 1'b0) && (RN == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);`
3271
3272			`$width(negedge CK &&& id_3, 0.1, 0, NOTIFIER);`
3273			`$width(posedge CK &&& id_3, 0.1, 0, NOTIFIER);`
3274			`$setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER);`
3275			`$setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER);`
3276			`$width(negedge D, 0.1, 0, NOTIFIER);`
3277			`$width(posedge D, 0.1, 0, NOTIFIER);`
3278			`$recovery(posedge RN, posedge CK, 0.1, NOTIFIER);`
3279			`$hold(posedge CK, posedge RN, 0.1, NOTIFIER);`
3280			`$width(negedge RN, 0.1, 0, NOTIFIER);`
3281			`$width(posedge RN, 0.1, 0, NOTIFIER);`
3282			`$setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER);`
3283			`$setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER);`
3284			`$width(negedge SE, 0.1, 0, NOTIFIER);`
3285			`$width(posedge SE, 0.1, 0, NOTIFIER);`
3286			`$setuphold(posedge CK, negedge SI, 0.1, 0.1, NOTIFIER);`
3287			`$setuphold(posedge CK, posedge SI, 0.1, 0.1, NOTIFIER);`
3288			`$width(negedge SI, 0.1, 0, NOTIFIER);`
3289			`$width(posedge SI, 0.1, 0, NOTIFIER);`
3290			`$recovery(posedge SN, posedge CK, 0.1, NOTIFIER);`
3291			`$hold(posedge CK, posedge SN, 0.1, NOTIFIER);`
3292			`$width(negedge SN, 0.1, 0, NOTIFIER);`
3293			`$width(posedge SN, 0.1, 0, NOTIFIER);`
3294			`endspecify`
3295
3296			`endmodule`
3297
3298			`primitive seq3 (IQ, RN, nextstate, CK, NOTIFIER);`
3299			`output IQ;`
3300			`input RN;`
3301			`input nextstate;`
3302			`input CK;`
3303			`input NOTIFIER;`
3304			`reg IQ;`
3305
3306			`table`
3307			`// RN nextstate CK NOTIFIER : @IQ : IQ`
3308			`? 0 r ? : ? : 0;`
3309			`1 1 r ? : ? : 1;`
3310			`? 0 * ? : 0 : 0; // reduce pessimism`
3311			`1 1 * ? : 1 : 1; // reduce pessimism`
3312			`1 * ? ? : ? : -; // Ignore all edges on nextstate`
3313			`1 ? f ? : ? : -; // Ignore non-triggering clock edge`
3314
3315			`* ? ? ? : 0 : 0; // Cover all transitions on RN`
3316			`? ? ? * : ? : x; // Any NOTIFIER change`
3317			`endtable`
3318			`endprimitive`
3319
3320			`module SDFFR_X1 (CK, D, RN, SE, SI, Q, QN);`
3321
3322			`input CK;`
3323			`input D;`
3324			`input RN;`
3325			`input SE;`
3326			`input SI;`
3327			`output Q;`
3328			`output QN;`
3329			`reg NOTIFIER;`
3330
3331			`seq3(IQ, RN, nextstate, CK, NOTIFIER);`
3332			`not(IQN, IQ);`
3333			`buf(Q, IQ);`
3334			`buf(QN, IQN);`
3335			`or(nextstate, i_18, i_19);`
3336			`and(i_18, SE, SI);`
3337			`and(i_19, D, i_20);`
3338			`not(i_20, SE);`
3339
3340
3341			`specify`
3342			`(posedge CK => (Q +: D)) = (0.1, 0.1);`
3343			`if((CK == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);`
3344			`if((CK == 1'b0)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);`
3345			`(posedge CK => (QN -: D)) = (0.1, 0.1);`
3346			`if((CK == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1);`
3347			`if((CK == 1'b0)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1);`
3348
3349			`$width(negedge CK &&& ((RN)), 0.1, 0, NOTIFIER);`
3350			`$width(posedge CK &&& ((RN)), 0.1, 0, NOTIFIER);`
3351			`$setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER);`
3352			`$setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER);`
3353			`$width(negedge D, 0.1, 0, NOTIFIER);`
3354			`$width(posedge D, 0.1, 0, NOTIFIER);`
3355			`$recovery(posedge RN, posedge CK, 0.1, NOTIFIER);`
3356			`$hold(posedge CK, posedge RN, 0.1, NOTIFIER);`
3357			`$width(negedge RN, 0.1, 0, NOTIFIER);`
3358			`$width(posedge RN, 0.1, 0, NOTIFIER);`
3359			`$setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER);`
3360			`$setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER);`
3361			`$width(negedge SE, 0.1, 0, NOTIFIER);`
3362			`$width(posedge SE, 0.1, 0, NOTIFIER);`
3363			`$setuphold(posedge CK, negedge SI, 0.1, 0.1, NOTIFIER);`
3364			`$setuphold(posedge CK, posedge SI, 0.1, 0.1, NOTIFIER);`
3365			`$width(negedge SI, 0.1, 0, NOTIFIER);`
3366			`$width(posedge SI, 0.1, 0, NOTIFIER);`
3367			`endspecify`
3368
3369			`endmodule`
3370
3371			`primitive seq3 (IQ, RN, nextstate, CK, NOTIFIER);`
3372			`output IQ;`
3373			`input RN;`
3374			`input nextstate;`
3375			`input CK;`
3376			`input NOTIFIER;`
3377			`reg IQ;`
3378
3379			`table`
3380			`// RN nextstate CK NOTIFIER : @IQ : IQ`
3381			`? 0 r ? : ? : 0;`
3382			`1 1 r ? : ? : 1;`
3383			`? 0 * ? : 0 : 0; // reduce pessimism`
3384			`1 1 * ? : 1 : 1; // reduce pessimism`
3385			`1 * ? ? : ? : -; // Ignore all edges on nextstate`
3386			`1 ? f ? : ? : -; // Ignore non-triggering clock edge`
3387
3388			`* ? ? ? : 0 : 0; // Cover all transitions on RN`
3389			`? ? ? * : ? : x; // Any NOTIFIER change`
3390			`endtable`
3391			`endprimitive`
3392
3393			`module SDFFR_X2 (CK, D, RN, SE, SI, Q, QN);`
3394
3395			`input CK;`
3396			`input D;`
3397			`input RN;`
3398			`input SE;`
3399			`input SI;`
3400			`output Q;`
3401			`output QN;`
3402			`reg NOTIFIER;`
3403
3404			`seq3(IQ, RN, nextstate, CK, NOTIFIER);`
3405			`not(IQN, IQ);`
3406			`buf(Q, IQ);`
3407			`buf(QN, IQN);`
3408			`or(nextstate, i_18, i_19);`
3409			`and(i_18, SE, SI);`
3410			`and(i_19, D, i_20);`
3411			`not(i_20, SE);`
3412
3413
3414			`specify`
3415			`(posedge CK => (Q +: D)) = (0.1, 0.1);`
3416			`if((CK == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);`
3417			`if((CK == 1'b0)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1);`
3418			`(posedge CK => (QN -: D)) = (0.1, 0.1);`
3419			`if((CK == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1);`
3420			`if((CK == 1'b0)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1);`
3421
3422			`$width(negedge CK &&& ((RN)), 0.1, 0, NOTIFIER);`
3423			`$width(posedge CK &&& ((RN)), 0.1, 0, NOTIFIER);`
3424			`$setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER);`
3425			`$setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER);`
3426			`$width(negedge D, 0.1, 0, NOTIFIER);`
3427			`$width(posedge D, 0.1, 0, NOTIFIER);`
3428			`$recovery(posedge RN, posedge CK, 0.1, NOTIFIER);`
3429			`$hold(posedge CK, posedge RN, 0.1, NOTIFIER);`
3430			`$width(negedge RN, 0.1, 0, NOTIFIER);`
3431			`$width(posedge RN, 0.1, 0, NOTIFIER);`
3432			`$setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER);`
3433			`$setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER);`
3434			`$width(negedge SE, 0.1, 0, NOTIFIER);`
3435			`$width(posedge SE, 0.1, 0, NOTIFIER);`
3436			`$setuphold(posedge CK, negedge SI, 0.1, 0.1, NOTIFIER);`
3437			`$setuphold(posedge CK, posedge SI, 0.1, 0.1, NOTIFIER);`
3438			`$width(negedge SI, 0.1, 0, NOTIFIER);`
3439			`$width(posedge SI, 0.1, 0, NOTIFIER);`
3440			`endspecify`
3441
3442			`endmodule`
3443
3444			`primitive seq3 (IQ, SN, nextstate, CK, NOTIFIER);`
3445			`output IQ;`
3446			`input SN;`
3447			`input nextstate;`
3448			`input CK;`
3449			`input NOTIFIER;`
3450			`reg IQ;`
3451
3452			`table`
3453			`// SN nextstate CK NOTIFIER : @IQ : IQ`
3454			`1 0 r ? : ? : 0;`
3455			`? 1 r ? : ? : 1;`
3456			`1 0 * ? : 0 : 0; // reduce pessimism`
3457			`? 1 * ? : 1 : 1; // reduce pessimism`
3458			`1 * ? ? : ? : -; // Ignore all edges on nextstate`
3459			`1 ? f ? : ? : -; // Ignore non-triggering clock edge`
3460
3461			`* ? ? ? : 1 : 1; // Cover all transitions on SN`
3462			`? ? ? * : ? : x; // Any NOTIFIER change`
3463			`endtable`
3464			`endprimitive`
3465
3466			`module SDFFS_X1 (CK, D, SE, SI, SN, Q, QN);`
3467
3468			`input CK;`
3469			`input D;`
3470			`input SE;`
3471			`input SI;`
3472			`input SN;`
3473			`output Q;`
3474			`output QN;`
3475			`reg NOTIFIER;`
3476
3477			`seq3(IQ, SN, nextstate, CK, NOTIFIER);`
3478			`not(IQN, IQ);`
3479			`buf(Q, IQ);`
3480			`buf(QN, IQN);`
3481			`or(nextstate, i_18, i_19);`
3482			`and(i_18, SE, SI);`
3483			`and(i_19, D, i_20);`
3484			`not(i_20, SE);`
3485
3486
3487			`specify`
3488			`(posedge CK => (Q +: D)) = (0.1, 0.1);`
3489			`if((CK == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);`
3490			`if((CK == 1'b0)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);`
3491			`(posedge CK => (QN -: D)) = (0.1, 0.1);`
3492			`if((CK == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);`
3493			`if((CK == 1'b0)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);`
3494
3495			`$width(negedge CK &&& ((SN)), 0.1, 0, NOTIFIER);`
3496			`$width(posedge CK &&& ((SN)), 0.1, 0, NOTIFIER);`
3497			`$setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER);`
3498			`$setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER);`
3499			`$width(negedge D, 0.1, 0, NOTIFIER);`
3500			`$width(posedge D, 0.1, 0, NOTIFIER);`
3501			`$setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER);`
3502			`$setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER);`
3503			`$width(negedge SE, 0.1, 0, NOTIFIER);`
3504			`$width(posedge SE, 0.1, 0, NOTIFIER);`
3505			`$setuphold(posedge CK, negedge SI, 0.1, 0.1, NOTIFIER);`
3506			`$setuphold(posedge CK, posedge SI, 0.1, 0.1, NOTIFIER);`
3507			`$width(negedge SI, 0.1, 0, NOTIFIER);`
3508			`$width(posedge SI, 0.1, 0, NOTIFIER);`
3509			`$recovery(posedge SN, posedge CK, 0.1, NOTIFIER);`
3510			`$hold(posedge CK, posedge SN, 0.1, NOTIFIER);`
3511			`$width(negedge SN, 0.1, 0, NOTIFIER);`
3512			`$width(posedge SN, 0.1, 0, NOTIFIER);`
3513			`endspecify`
3514
3515			`endmodule`
3516
3517			`primitive seq3 (IQ, SN, nextstate, CK, NOTIFIER);`
3518			`output IQ;`
3519			`input SN;`
3520			`input nextstate;`
3521			`input CK;`
3522			`input NOTIFIER;`
3523			`reg IQ;`
3524
3525			`table`
3526			`// SN nextstate CK NOTIFIER : @IQ : IQ`
3527			`1 0 r ? : ? : 0;`
3528			`? 1 r ? : ? : 1;`
3529			`1 0 * ? : 0 : 0; // reduce pessimism`
3530			`? 1 * ? : 1 : 1; // reduce pessimism`
3531			`1 * ? ? : ? : -; // Ignore all edges on nextstate`
3532			`1 ? f ? : ? : -; // Ignore non-triggering clock edge`
3533
3534			`* ? ? ? : 1 : 1; // Cover all transitions on SN`
3535			`? ? ? * : ? : x; // Any NOTIFIER change`
3536			`endtable`
3537			`endprimitive`
3538
3539			`module SDFFS_X2 (CK, D, SE, SI, SN, Q, QN);`
3540
3541			`input CK;`
3542			`input D;`
3543			`input SE;`
3544			`input SI;`
3545			`input SN;`
3546			`output Q;`
3547			`output QN;`
3548			`reg NOTIFIER;`
3549
3550			`seq3(IQ, SN, nextstate, CK, NOTIFIER);`
3551			`not(IQN, IQ);`
3552			`buf(Q, IQ);`
3553			`buf(QN, IQN);`
3554			`or(nextstate, i_18, i_19);`
3555			`and(i_18, SE, SI);`
3556			`and(i_19, D, i_20);`
3557			`not(i_20, SE);`
3558
3559
3560			`specify`
3561			`(posedge CK => (Q +: D)) = (0.1, 0.1);`
3562			`if((CK == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);`
3563			`if((CK == 1'b0)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1);`
3564			`(posedge CK => (QN -: D)) = (0.1, 0.1);`
3565			`if((CK == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);`
3566			`if((CK == 1'b0)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1);`
3567
3568			`$width(negedge CK &&& ((SN)), 0.1, 0, NOTIFIER);`
3569			`$width(posedge CK &&& ((SN)), 0.1, 0, NOTIFIER);`
3570			`$setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER);`
3571			`$setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER);`
3572			`$width(negedge D, 0.1, 0, NOTIFIER);`
3573			`$width(posedge D, 0.1, 0, NOTIFIER);`
3574			`$setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER);`
3575			`$setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER);`
3576			`$width(negedge SE, 0.1, 0, NOTIFIER);`
3577			`$width(posedge SE, 0.1, 0, NOTIFIER);`
3578			`$setuphold(posedge CK, negedge SI, 0.1, 0.1, NOTIFIER);`
3579			`$setuphold(posedge CK, posedge SI, 0.1, 0.1, NOTIFIER);`
3580			`$width(negedge SI, 0.1, 0, NOTIFIER);`
3581			`$width(posedge SI, 0.1, 0, NOTIFIER);`
3582			`$recovery(posedge SN, posedge CK, 0.1, NOTIFIER);`
3583			`$hold(posedge CK, posedge SN, 0.1, NOTIFIER);`
3584			`$width(negedge SN, 0.1, 0, NOTIFIER);`
3585			`$width(posedge SN, 0.1, 0, NOTIFIER);`
3586			`endspecify`
3587
3588			`endmodule`
3589
3590			`primitive seq3 (IQ, nextstate, CK, NOTIFIER);`
3591			`output IQ;`
3592			`input nextstate;`
3593			`input CK;`
3594			`input NOTIFIER;`
3595			`reg IQ;`
3596
3597			`table`
3598			`// nextstate CK NOTIFIER : @IQ : IQ`
3599
3600			`1 r ? : ? : 1;`
3601
3602			`1 * ? : 1 : 1; // reduce pessimism`
3603			`* ? ? : ? : -; // Ignore all edges on nextstate`
3604			`? f ? : ? : -; // Ignore non-triggering clock edge`
3605			`? ? * : ? : x; // Any NOTIFIER change`
3606			`endtable`
3607			`endprimitive`
3608
3609			`module SDFF_X1 (CK, D, SE, SI, Q, QN);`
3610
3611			`input CK;`
3612			`input D;`
3613			`input SE;`
3614			`input SI;`
3615			`output Q;`
3616			`output QN;`
3617			`reg NOTIFIER;`
3618
3619			`seq3(IQ, nextstate, CK, NOTIFIER);`
3620			`not(IQN, IQ);`
3621			`buf(Q, IQ);`
3622			`buf(QN, IQN);`
3623			`or(nextstate, i_18, i_19);`
3624			`and(i_18, SE, SI);`
3625			`and(i_19, D, i_20);`
3626			`not(i_20, SE);`
3627
3628
3629			`specify`
3630			`(posedge CK => (Q +: D)) = (0.1, 0.1);`
3631			`(posedge CK => (QN -: D)) = (0.1, 0.1);`
3632
3633			`$width(negedge CK, 0.1, 0, NOTIFIER);`
3634			`$width(posedge CK, 0.1, 0, NOTIFIER);`
3635			`$setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER);`
3636			`$setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER);`
3637			`$width(negedge D, 0.1, 0, NOTIFIER);`
3638			`$width(posedge D, 0.1, 0, NOTIFIER);`
3639			`$setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER);`
3640			`$setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER);`
3641			`$width(negedge SE, 0.1, 0, NOTIFIER);`
3642			`$width(posedge SE, 0.1, 0, NOTIFIER);`
3643			`$setuphold(posedge CK, negedge SI, 0.1, 0.1, NOTIFIER);`
3644			`$setuphold(posedge CK, posedge SI, 0.1, 0.1, NOTIFIER);`
3645			`$width(negedge SI, 0.1, 0, NOTIFIER);`
3646			`$width(posedge SI, 0.1, 0, NOTIFIER);`
3647			`endspecify`
3648
3649			`endmodule`
3650
3651			`primitive seq3 (IQ, nextstate, CK, NOTIFIER);`
3652			`output IQ;`
3653			`input nextstate;`
3654			`input CK;`
3655			`input NOTIFIER;`
3656			`reg IQ;`
3657
3658			`table`
3659			`// nextstate CK NOTIFIER : @IQ : IQ`
3660
3661			`1 r ? : ? : 1;`
3662
3663			`1 * ? : 1 : 1; // reduce pessimism`
3664			`* ? ? : ? : -; // Ignore all edges on nextstate`
3665			`? f ? : ? : -; // Ignore non-triggering clock edge`
3666			`? ? * : ? : x; // Any NOTIFIER change`
3667			`endtable`
3668			`endprimitive`
3669
3670			`module SDFF_X2 (CK, D, SE, SI, Q, QN);`
3671
3672			`input CK;`
3673			`input D;`
3674			`input SE;`
3675			`input SI;`
3676			`output Q;`
3677			`output QN;`
3678			`reg NOTIFIER;`
3679
3680			`seq3(IQ, nextstate, CK, NOTIFIER);`
3681			`not(IQN, IQ);`
3682			`buf(Q, IQ);`
3683			`buf(QN, IQN);`
3684			`or(nextstate, i_18, i_19);`
3685			`and(i_18, SE, SI);`
3686			`and(i_19, D, i_20);`
3687			`not(i_20, SE);`
3688
3689
3690			`specify`
3691			`(posedge CK => (Q +: D)) = (0.1, 0.1);`
3692			`(posedge CK => (QN -: D)) = (0.1, 0.1);`
3693
3694			`$width(negedge CK, 0.1, 0, NOTIFIER);`
3695			`$width(posedge CK, 0.1, 0, NOTIFIER);`
3696			`$setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER);`
3697			`$setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER);`
3698			`$width(negedge D, 0.1, 0, NOTIFIER);`
3699			`$width(posedge D, 0.1, 0, NOTIFIER);`
3700			`$setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER);`
3701			`$setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER);`
3702			`$width(negedge SE, 0.1, 0, NOTIFIER);`
3703			`$width(posedge SE, 0.1, 0, NOTIFIER);`
3704			`$setuphold(posedge CK, negedge SI, 0.1, 0.1, NOTIFIER);`
3705			`$setuphold(posedge CK, posedge SI, 0.1, 0.1, NOTIFIER);`
3706			`$width(negedge SI, 0.1, 0, NOTIFIER);`
3707			`$width(posedge SI, 0.1, 0, NOTIFIER);`
3708			`endspecify`
3709
3710			`endmodule`
3711
3712			`module TBUF_X1 (A, EN, Z);`
3713
3714			`input A;`
3715			`input EN;`
3716			`output Z;`
3717
3718			`bufif0(Z, Z_in, Z_enable);`
3719			`buf(Z_enable, EN);`
3720			`buf(Z_in, A);`
3721
3722			`specify`
3723			`(A => Z) = (0.1, 0.1);`
3724			`(EN => Z) = (0.1, 0.1);`
3725			`endspecify`
3726
3727			`endmodule`
3728
3729			`module TBUF_X16 (A, EN, Z);`
3730
3731			`input A;`
3732			`input EN;`
3733			`output Z;`
3734
3735			`bufif0(Z, Z_in, Z_enable);`
3736			`buf(Z_enable, EN);`
3737			`buf(Z_in, A);`
3738
3739			`specify`
3740			`(A => Z) = (0.1, 0.1);`
3741			`(EN => Z) = (0.1, 0.1);`
3742			`endspecify`
3743
3744			`endmodule`
3745
3746			`module TBUF_X2 (A, EN, Z);`
3747
3748			`input A;`
3749			`input EN;`
3750			`output Z;`
3751
3752			`bufif0(Z, Z_in, Z_enable);`
3753			`buf(Z_enable, EN);`
3754			`buf(Z_in, A);`
3755
3756			`specify`
3757			`(A => Z) = (0.1, 0.1);`
3758			`(EN => Z) = (0.1, 0.1);`
3759			`endspecify`
3760
3761			`endmodule`
3762
3763			`module TBUF_X4 (A, EN, Z);`
3764
3765			`input A;`
3766			`input EN;`
3767			`output Z;`
3768
3769			`bufif0(Z, Z_in, Z_enable);`
3770			`buf(Z_enable, EN);`
3771			`buf(Z_in, A);`
3772
3773			`specify`
3774			`(A => Z) = (0.1, 0.1);`
3775			`(EN => Z) = (0.1, 0.1);`
3776			`endspecify`
3777
3778			`endmodule`
3779
3780			`module TBUF_X8 (A, EN, Z);`
3781
3782			`input A;`
3783			`input EN;`
3784			`output Z;`
3785
3786			`bufif0(Z, Z_in, Z_enable);`
3787			`buf(Z_enable, EN);`
3788			`buf(Z_in, A);`
3789
3790			`specify`
3791			`(A => Z) = (0.1, 0.1);`
3792			`(EN => Z) = (0.1, 0.1);`
3793			`endspecify`
3794
3795			`endmodule`
3796
3797			`module TINV_X1 (EN, I, ZN);`
3798
3799			`input EN;`
3800			`input I;`
3801			`output ZN;`
3802
3803			`bufif0(ZN, ZN_in, ZN_enable);`
3804			`buf(ZN_enable, EN);`
3805			`not(ZN_in, I);`
3806
3807			`specify`
3808			`(EN => ZN) = (0.1, 0.1);`
3809			`(I => ZN) = (0.1, 0.1);`
3810			`endspecify`
3811
3812			`endmodule`
3813
3814			`primitive seq3 (IQ, nextstate, G, NOTIFIER);`
3815			`output IQ;`
3816			`input nextstate;`
3817			`input G;`
3818			`input NOTIFIER;`
3819			`reg IQ;`
3820
3821			`table`
3822			`// nextstate G NOTIFIER : @IQ : IQ`
3823
3824			`1 1 ? : ? : 1;`
3825			`* ? ? : ? : -; // Ignore all edges on nextstate`
3826			`? 0 ? : ? : -; // Ignore non-triggering clock edge`
3827			`? ? * : ? : x; // Any NOTIFIER change`
3828			`endtable`
3829			`endprimitive`
3830
3831			`module TLAT_X1 (D, G, OE, Q);`
3832
3833			`input D;`
3834			`input G;`
3835			`input OE;`
3836			`output Q;`
3837			`reg NOTIFIER;`
3838
3839			`bufif0(Q, Q_in, Q_enable);`
3840			`not(Q_enable, OE);`
3841			`seq3(IQ, nextstate, G, NOTIFIER);`
3842			`not(IQN, IQ);`
3843			`buf(Q_in, IQ);`
3844			`buf(nextstate, D);`
3845
3846
3847			`specify`
3848			`(D => Q) = (0.1, 0.1);`
3849			`(posedge G => (Q +: D)) = (0.1, 0.1);`
3850			`(OE => Q) = (0.1, 0.1);`
3851
3852			`$setuphold(negedge G, negedge D, 0.1, 0.1, NOTIFIER);`
3853			`$setuphold(negedge G, posedge D, 0.1, 0.1, NOTIFIER);`
3854			`$width(negedge D, 0.1, 0, NOTIFIER);`
3855			`$width(posedge D, 0.1, 0, NOTIFIER);`
3856			`$width(negedge G, 0.1, 0, NOTIFIER);`
3857			`$width(posedge G, 0.1, 0, NOTIFIER);`
3858			`$width(negedge OE, 0.1, 0, NOTIFIER);`
3859			`$width(posedge OE, 0.1, 0, NOTIFIER);`
3860			`endspecify`
3861
3862			`endmodule`
3863
3864			`module XNOR2_X1 (A, B, ZN);`
3865
3866			`input A;`
3867			`input B;`
3868			`output ZN;`
3869
3870			`not(ZN, i_46);`
3871			`xor(i_46, A, B);`
3872
3873			`specify`
3874			`if((B == 1'b0)) (A => ZN) = (0.1, 0.1);`
3875			`if((B == 1'b1)) (A => ZN) = (0.1, 0.1);`
3876			`if((A == 1'b1)) (B => ZN) = (0.1, 0.1);`
3877			`if((A == 1'b0)) (B => ZN) = (0.1, 0.1);`
3878			`endspecify`
3879
3880			`endmodule`
3881
3882			`module XNOR2_X2 (A, B, ZN);`
3883
3884			`input A;`
3885			`input B;`
3886			`output ZN;`
3887
3888			`not(ZN, i_46);`
3889			`xor(i_46, A, B);`
3890
3891			`specify`
3892			`if((B == 1'b0)) (A => ZN) = (0.1, 0.1);`
3893			`if((B == 1'b1)) (A => ZN) = (0.1, 0.1);`
3894			`if((A == 1'b1)) (B => ZN) = (0.1, 0.1);`
3895			`if((A == 1'b0)) (B => ZN) = (0.1, 0.1);`
3896			`endspecify`
3897
3898			`endmodule`
3899
3900			`module XOR2_X1 (A, B, Z);`
3901
3902			`input A;`
3903			`input B;`
3904			`output Z;`
3905
3906			`xor(Z, A, B);`
3907
3908			`specify`
3909			`if((B == 1'b0)) (A => Z) = (0.1, 0.1);`
3910			`if((B == 1'b1)) (A => Z) = (0.1, 0.1);`
3911			`if((A == 1'b1)) (B => Z) = (0.1, 0.1);`
3912			`if((A == 1'b0)) (B => Z) = (0.1, 0.1);`
3913			`endspecify`
3914
3915			`endmodule`
3916
3917			`module XOR2_X2 (A, B, Z);`
3918
3919			`input A;`
3920			`input B;`
3921			`output Z;`
3922
3923			`xor(Z, A, B);`
3924
3925			`specify`
3926			`if((B == 1'b0)) (A => Z) = (0.1, 0.1);`
3927			`if((B == 1'b1)) (A => Z) = (0.1, 0.1);`
3928			`if((A == 1'b1)) (B => Z) = (0.1, 0.1);`
3929			`if((A == 1'b0)) (B => Z) = (0.1, 0.1);`
3930			`endspecify`
3931
3932			`endmodule`
3933
3934			`//`
3935			`// End of file`
3936			`//`

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