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[/] [async_sdm_noc/] [trunk/] [sdm/] [src/] [clos_sch.v] - Blame information for rev 28

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1 19 wsong0210 
/*
2 
 Asynchronous SDM NoC
3 
 (C)2011 Wei Song
4 
 Advanced Processor Technologies Group
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 Computer Science, the Univ. of Manchester, UK
6 
 
7 
 Authors:
8 
 Wei Song     wsong83@gmail.com
9 
 
10 
 License: LGPL 3.0 or later
11 
 
12 
 Clos scheduler
13 
 *** SystemVerilog is used ***
14 
 
15 
 References
16 
 For the detail structure, please refer to Section 6.3.1 of the thesis:
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   Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011.
18 
 
19 
 History:
20 
 11/12/2009  Initial version. <wsong83@gmail.com>
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 10/06/2010  Change to use PIM structure <wsong83@gmail.com>
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 23/08/2010  Fix the non-QDI request withdraw process <wsong83@gmail.com>
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 23/09/2010  Modified for Clos SDM router <wsong83@gmail.com>
24 28 wsong0210 
 27/05/2011  Clean up for opensource. <wsong83@gmail.com>
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26 
*/
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// the router structure definitions
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`include "define.v"
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module clos_sch (/*AUTOARG*/
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   // Outputs
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   sack, wack, nack, eack, lack, imc, scfg, ncfg, wcfg, ecfg, lcfg,
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   // Inputs
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   sreq, nreq, lreq, wreq, ereq, rst_n
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   );
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   parameter M = 2;             // the number of CMs
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   parameter N = 2;             // the number of ports in IMs/OMs
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   // reuests from all input buffers
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   input [N-1:0][3:0]             sreq, nreq, lreq;
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   input [N-1:0][1:0]               wreq, ereq;
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   // ack to input buffers
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   output [N-1:0]                  sack, wack, nack, eack, lack;
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   // IM acks
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   wire [4:0][N-1:0]                imra;
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   wire [4:0][N-1:0]                cmra;
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   // IM cfgs and CM cfgs
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   output [4:0][M-1:0][N-1:0]        imc;
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   output [M-1:0][1:0]              scfg, ncfg;
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   output [M-1:0][3:0]              wcfg, ecfg, lcfg;
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   input                          rst_n;        // reset, active low
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   // the requests from IMs to CMs
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   wire [M-1:0][1:0]                wr, er;
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   wire [M-1:0][3:0]                sr, nr, lr;
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   wire [M-1:0]            sra, wra, nra, era, lra;
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64 
`ifndef ENABLE_CRRD
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   wire [M-1:0][4:0]                cms;          // the states from CMs
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   wire [M-1:0][3:0]                scms, ncms, lcms;
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   wire [M-1:0][1:0]                wcms, ecms;
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`endif
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   genvar                         i;
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   // IM schedulers
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   im_alloc #(.VCN(N), .CMN(M), .SN(4))
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   SIM (
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        .IMr   ( sreq      ),
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        .IMa   ( imra[0]   ),
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`ifndef ENABLE_CRRD
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        .CMs   ( scms      ),
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`endif
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        .cfg   ( imc[0]    ),
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        .rst_n ( rst_n     )
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        );
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   rcb #(.NN(N), .MN(M), .DW(4))
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   SRIM (
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         .ireq ( sreq      ),
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         .ira  ( cmra[0]   ),
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         .oreq ( sr        ),
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         .ora  ( sra       ),
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         .cfg  ( imc[0]    )
92 19 wsong0210 
         );
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   // the C-element to force the request withdrawal sequence
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   generate for(i=0; i<N; i++) begin: SA
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      c2 UA (.q(sack[i]), .a0(imra[0][i]), .a1(cmra[0][i]));
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   end endgenerate
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   im_alloc #(.VCN(N), .CMN(M), .SN(2))
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   WIM (
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        .IMr   ( wreq      ),
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        .IMa   ( imra[1]   ),
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`ifndef ENABLE_CRRD
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        .CMs   ( wcms      ),
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`endif
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        .cfg   ( imc[1]    ),
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        .rst_n ( rst_n     )
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        );
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   rcb #(.NN(N), .MN(M), .DW(2))
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   WRIM (
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         .ireq ( wreq      ),
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         .ira  ( cmra[1]   ),
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         .oreq ( wr        ),
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         .ora  ( wra       ),
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         .cfg  ( imc[1]    )
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         );
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   generate for(i=0; i<N; i++) begin: WA
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      c2 UA (.q(wack[i]), .a0(imra[1][i]), .a1(cmra[1][i]));
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   end endgenerate
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   im_alloc #(.VCN(N), .CMN(M), .SN(4))
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   NIM (
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        .IMr   ( nreq      ),
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        .IMa   ( imra[2]   ),
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`ifndef ENABLE_CRRD
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        .CMs   ( ncms      ),
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`endif
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        .cfg   ( imc[2]    ),
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        .rst_n ( rst_n     )
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        );
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   rcb #(.NN(N), .MN(M), .DW(4))
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   NRIM (
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         .ireq ( nreq      ),
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         .ira  ( cmra[2]   ),
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         .oreq ( nr        ),
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         .ora  ( nra       ),
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         .cfg  ( imc[2]    )
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         );
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   generate for(i=0; i<N; i++) begin: NA
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      c2 UA (.q(nack[i]), .a0(imra[2][i]), .a1(cmra[2][i]));
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   end endgenerate
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   im_alloc #(.VCN(N), .CMN(M), .SN(2))
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   EIM (
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        .IMr   ( ereq      ),
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        .IMa   ( imra[3]   ),
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`ifndef ENABLE_CRRD
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        .CMs   ( ecms      ),
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`endif
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        .cfg   ( imc[3]    ),
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        .rst_n ( rst_n     )
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        );
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   rcb #(.NN(N), .MN(M), .DW(2))
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   ERIM (
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         .ireq ( ereq      ),
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         .ira  ( cmra[3]   ),
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         .oreq ( er        ),
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         .ora  ( era       ),
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         .cfg  ( imc[3]    )
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         );
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   generate for(i=0; i<N; i++) begin: EA
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      c2 UA (.q(eack[i]), .a0(imra[3][i]), .a1(cmra[3][i]));
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   end endgenerate
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   im_alloc #(.VCN(N), .CMN(M), .SN(4))
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   LIM (
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        .IMr   ( lreq      ),
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        .IMa   ( imra[4]   ),
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`ifndef ENABLE_CRRD
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        .CMs   ( lcms      ),
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`endif
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        .cfg   ( imc[4]    ),
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        .rst_n ( rst_n     )
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        );
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   rcb #(.NN(N), .MN(M), .DW(4))
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   LRIM (
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         .ireq ( lreq      ),
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         .ira  ( cmra[4]   ),
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         .oreq ( lr        ),
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         .ora  ( lra       ),
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         .cfg  ( imc[4]    )
189 19 wsong0210 
         );
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191 
   generate for(i=0; i<N; i++) begin: LA
192 
      c2 UA (.q(lack[i]), .a0(imra[4][i]), .a1(cmra[4][i]));
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   end endgenerate
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195 
   // CM schedulers
196 
   generate
197 
      for(i=0; i<M; i=i+1) begin: CMSch
198 
         cm_alloc S (
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                   .sra   ( sra[i]  ),
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                   .wra   ( wra[i]  ),
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                   .nra   ( nra[i]  ),
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                   .era   ( era[i]  ),
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                   .lra   ( lra[i]  ),
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                   .scfg  ( scfg[i] ),
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                   .ncfg  ( ncfg[i] ),
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                   .wcfg  ( wcfg[i] ),
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                   .ecfg  ( ecfg[i] ),
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                   .lcfg  ( lcfg[i] ),
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`ifndef ENABLE_CRRD
210 
                   .s     ( cms[i]  ),
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`endif
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                   .wr    ( wr[i]   ),
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                   .er    ( er[i]   ),
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                   .sr    ( sr[i]   ),
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                   .nr    ( nr[i]   ),
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                   .lr    ( lr[i]   )
217 
                   );
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219 
`ifndef ENABLE_CRRD
220 
         assign scms[i] = {cms[i][4], cms[i][3], cms[i][2], cms[i][1]};
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         assign wcms[i] = {cms[i][4], cms[i][3]};
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         assign ncms[i] = {cms[i][4], cms[i][3], cms[i][1], cms[i][0]};
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         assign ecms[i] = {cms[i][4], cms[i][1]};
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         assign lcms[i] = {cms[i][3], cms[i][2], cms[i][1], cms[i][0]};
225 
`endif
226 
 
227 
      end
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   endgenerate
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endmodule // clos_sch
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