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/*
 Asynchronous SDM NoC
 (C)2011 Wei Song
 Advanced Processor Technologies Group
 Computer Science, the Univ. of Manchester, UK
 
 Authors:
 Wei Song     wsong83@gmail.com
 
 License: LGPL 3.0 or later
 
 IM allocator (the IM dispatcher in the thesis)
 *** SystemVerilog is used ***
 
 References
 For the detail structure, please refer to Section 6.3.1 of the thesis:
   Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011.
 
 History:
 05/09/2009  Initial version. <wsong83@gmail.com>
 10/10/2009  Add the reset port. <wsong83@gmail.com>
 05/11/2009  Speed up the arbiter. <wsong83@gmail.com>
 10/06/2010  [Major] change to use PIM structure. <wsong83@gmail.com>
 23/08/2010  Fix the non-QDI request withdraw process. <wsong83@gmail.com>
 27/05/2011  Clean up for opensource. <wsong83@gmail.com>
 
*/
 
// the router structure definitions
`include "define.v"
 
module im_alloc (/*AUTOARG*/
`ifndef ENABLE_CRRD
   CMs,
`endif
   // Outputs
   IMa, cfg,
   // Inputs
   IMr, rst_n
   ) ;
   // parameters
   parameter VCN = 2;    // the number of virtual circuits on one port
   parameter CMN = 2;    // the number of central modules
   parameter SN = 2;     // the possible output port choice of a port
 
   input  [VCN-1:0][SN-1:0]     IMr; // the requests from virtual circuits
   output [VCN-1:0]              IMa; // switch ready, ack for the request
 
`ifndef ENABLE_CRRD
   input [CMN-1:0][SN-1:0]        CMs; // the states from CMs
`endif
 
   input                        rst_n; // the negtive active reset
 
   output [CMN-1:0][VCN-1:0]      cfg; // the matrix configuration signals
 
   // internal wires
`ifdef ENABLE_CRRD
 `ifdef ENABLE_MRMA
   wire [VCN-1:0]                IPr; // request to the MRMA
   wire [CMN-1:0]               OPrdy, OPblk; // OP ready and blocked status
   wire [CMN:0]          OPrst_n; // the buffered resets to avoid metastability
 `else
   wire [VCN-1:0][CMN-1:0]        IPr; // request to the MNMA
 `endif
`else
   // using the feedback from CMs
   wire [VCN-1:0][CMN-1:0][SN-1:0] IPrm; // to generate the practical IPr
   wire [VCN-1:0][CMN-1:0]           IPr;
`endif
 
   // generate variables
   genvar                  i, j, k;
 
   //----------------------------------------
   // the PIM crossbar allocator
`ifndef ENABLE_MRMA
   mnma #(.N(VCN), .M(CMN))
   PIMA (
         .cfg ( cfg   ),
         .r   ( IPr   ),
         .ra  ( IMa   )
         );
 
   generate
      for(i=0; i<VCN; i++) begin: IPC
         for(j=0; j<CMN; j++) begin: OPC
 `ifdef ENABLE_CRRD
            assign IPr[i][j] = |IMr[i];
 `else
            assign IPr[i][j] = |IPrm[i][j];
            for(k=0; k<SN; k++) begin: DIRC
               c2p IPRen (.q(IPrm[i][j][k]), .a0(IMr[i][k]), .a1(~CMs[j][k]));
            end
 `endif
         end
      end // block: IPC
   endgenerate
 
`else
   mrma #(.N(VCN), .M(CMN))
   PIMA (
         .ca    ( IMa   ),
         .ra    ( OPblk ),
         .cfg   ( cfg   ),
         .c     ( IPr   ),
         .r     ( OPrdy ),
         .rst_n ( rst_n )
         );
 
   generate
      for(i=0; i<CMN; i++) begin: OPC
         delay DLY ( .q(OPrst_n[i+1]), .a(OPrst_n[i])); // dont touch
         assign OPrdy[i] = (~OPblk[i])&OPrst_n[i+1];
      end
 
      for(i=0; i<VCN; i++) begin: IPC
         assign IPr[i] = |IMr[i];
      end
   endgenerate
 
   assign OPrst_n[0] = rst_n;
 
`endif // !`ifndef ENABLE_MRMA
 
endmodule // im_alloc

Line No.	Rev	Author	Line
1	19	wsong0210	`/*`
2			`Asynchronous SDM NoC`
3			`(C)2011 Wei Song`
4			`Advanced Processor Technologies Group`
5			`Computer Science, the Univ. of Manchester, UK`
6
7			`Authors:`
8			`Wei Song wsong83@gmail.com`
9
10			`License: LGPL 3.0 or later`
11
12			`IM allocator (the IM dispatcher in the thesis)`
13			`* SystemVerilog is used *`
14
15			`References`
16			`For the detail structure, please refer to Section 6.3.1 of the thesis:`
17			`Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011.`
18
19			`History:`
20			`05/09/2009 Initial version. <wsong83@gmail.com>`
21			`10/10/2009 Add the reset port. <wsong83@gmail.com>`
22			`05/11/2009 Speed up the arbiter. <wsong83@gmail.com>`
23			`10/06/2010 [Major] change to use PIM structure. <wsong83@gmail.com>`
24			`23/08/2010 Fix the non-QDI request withdraw process. <wsong83@gmail.com>`
25	28	wsong0210	`27/05/2011 Clean up for opensource. <wsong83@gmail.com>`
26	19	wsong0210
27			`*/`
28
29			`// the router structure definitions`
30			`include "define.v"
31
32			`module im_alloc (/AUTOARG/`
33			`ifndef ENABLE_CRRD
34			`CMs,`
35			`endif
36			`// Outputs`
37			`IMa, cfg,`
38			`// Inputs`
39			`IMr, rst_n`
40			`) ;`
41			`// parameters`
42			`parameter VCN = 2; // the number of virtual circuits on one port`
43			`parameter CMN = 2; // the number of central modules`
44			`parameter SN = 2; // the possible output port choice of a port`
45
46			`input [VCN-1:0][SN-1:0] IMr; // the requests from virtual circuits`
47			`output [VCN-1:0] IMa; // switch ready, ack for the request`
48
49			`ifndef ENABLE_CRRD
50			`input [CMN-1:0][SN-1:0] CMs; // the states from CMs`
51			`endif
52
53			`input rst_n; // the negtive active reset`
54
55			`output [CMN-1:0][VCN-1:0] cfg; // the matrix configuration signals`
56
57			`// internal wires`
58			`ifdef ENABLE_CRRD
59			`ifdef ENABLE_MRMA
60			`wire [VCN-1:0] IPr; // request to the MRMA`
61			`wire [CMN-1:0] OPrdy, OPblk; // OP ready and blocked status`
62			`wire [CMN:0] OPrst_n; // the buffered resets to avoid metastability`
63			`else
64			`wire [VCN-1:0][CMN-1:0] IPr; // request to the MNMA`
65			`endif
66			`else
67			`// using the feedback from CMs`
68			`wire [VCN-1:0][CMN-1:0][SN-1:0] IPrm; // to generate the practical IPr`
69			`wire [VCN-1:0][CMN-1:0] IPr;`
70			`endif
71
72			`// generate variables`
73			`genvar i, j, k;`
74
75			`//----------------------------------------`
76			`// the PIM crossbar allocator`
77			`ifndef ENABLE_MRMA
78			`mnma #(.N(VCN), .M(CMN))`
79			`PIMA (`
80			`.cfg ( cfg ),`
81			`.r ( IPr ),`
82			`.ra ( IMa )`
83			`);`
84
85			`generate`
86			`for(i=0; i<VCN; i++) begin: IPC`
87			`for(j=0; j<CMN; j++) begin: OPC`
88			`ifdef ENABLE_CRRD
89	28	wsong0210	`assign IPr[i][j] = \|IMr[i];`
90	19	wsong0210	`else
91	28	wsong0210	`assign IPr[i][j] = \|IPrm[i][j];`
92	19	wsong0210	`for(k=0; k<SN; k++) begin: DIRC`
93			`c2p IPRen (.q(IPrm[i][j][k]), .a0(IMr[i][k]), .a1(~CMs[j][k]));`
94			`end`
95			`endif
96			`end`
97			`end // block: IPC`
98			`endgenerate`
99
100			`else
101			`mrma #(.N(VCN), .M(CMN))`
102			`PIMA (`
103			`.ca ( IMa ),`
104			`.ra ( OPblk ),`
105			`.cfg ( cfg ),`
106			`.c ( IPr ),`
107			`.r ( OPrdy ),`
108			`.rst_n ( rst_n )`
109			`);`
110
111			`generate`
112			`for(i=0; i<CMN; i++) begin: OPC`
113			`delay DLY ( .q(OPrst_n[i+1]), .a(OPrst_n[i])); // dont touch`
114			`assign OPrdy[i] = (~OPblk[i])&OPrst_n[i+1];`
115			`end`
116
117			`for(i=0; i<VCN; i++) begin: IPC`
118			`assign IPr[i] = \|IMr[i];`
119			`end`
120			`endgenerate`
121	28	wsong0210
122			`assign OPrst_n[0] = rst_n;`
123
124	19	wsong0210	`endif // !`ifndef ENABLE_MRMA
125
126			`endmodule // im_alloc`

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[/] [async_sdm_noc/] [trunk/] [sdm/] [src/] [im_alloc.v] - Blame information for rev 28