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/*
 Asynchronous SDM NoC
 (C)2011 Wei Song
 Advanced Processor Technologies Group
 Computer Science, the Univ. of Manchester, UK
 
 Authors:
 Wei Song     wsong83@gmail.com
 
 License: LGPL 3.0 or later
 
 Wormhole/SDM router top level module
 *** SystemVerilog is used ***
 
 History:
 28/05/2009  Initial version. <wsong83@gmail.com>
 23/09/2010  Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
 22/10/2010  Parameterize the number of pipelines in output buffers. <wsong83@gmail.com>
 25/05/2011  Clean up for opensource. <wsong83@gmail.com>
 
*/
 
// the router structure definitions
`include "define.v"
 
module router(/*AUTOARG*/
   // Outputs
   so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
   eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
   wia, nia, eia, lia,
   // Inputs
   si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
   ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
   woa, noa, eoa, loa, addrx, addry, rst_n
   );
 
   parameter VCN = 1;           // number of virtual circuits in each direction. When VCN == 1, it is a wormhole router
   parameter DW = 32;           // the datawidth of a single virtual circuit, the total data width of the router is DW*VCN
   parameter IPD = 1;           // the number of half-buffer stages in input buffers
   parameter OPD = 2;           // the number of half-buffer stages in output buffers
   parameter SCN = DW/2;        // the number of 1-of-4 sub-channel in each virtual circuit
 
   input [VCN-1:0][SCN-1:0]      si0, si1, si2, si3; // south input [0], X+1
   input [VCN-1:0][SCN-1:0]        wi0, wi1, wi2, wi3; // west input [1], Y-1
   input [VCN-1:0][SCN-1:0]        ni0, ni1, ni2, ni3; // north input [2], X-1
   input [VCN-1:0][SCN-1:0]        ei0, ei1, ei2, ei3; // east input [3], Y+1
   input [VCN-1:0][SCN-1:0]        li0, li1, li2, li3; // local input
   output [VCN-1:0][SCN-1:0]       so0, so1, so2, so3; // south output
   output [VCN-1:0][SCN-1:0]       wo0, wo1, wo2, wo3; // west output
   output [VCN-1:0][SCN-1:0]       no0, no1, no2, no3; // north output
   output [VCN-1:0][SCN-1:0]       eo0, eo1, eo2, eo3; // east output
   output [VCN-1:0][SCN-1:0]       lo0, lo1, lo2, lo3; // local output
 
   // eof bits and ack lines
`ifdef ENABLE_CHANNEL_SLICING
   input [VCN-1:0][SCN-1:0]        si4, wi4, ni4, ei4, li4;
   output [VCN-1:0][SCN-1:0]       so4, wo4, no4, eo4, lo4;
   output [VCN-1:0][SCN-1:0]       sia, wia, nia, eia, lia;
   input [VCN-1:0][SCN-1:0]        soa, woa, noa, eoa, loa;
`else
   input [VCN-1:0]                si4, wi4, ni4, ei4, li4;
   output [VCN-1:0]               so4, wo4, no4, eo4, lo4;
   output [VCN-1:0]               sia, wia, nia, eia, lia;
   input [VCN-1:0]                soa, woa, noa, eoa, loa;
`endif // !`ifdef ENABLE_CHANNEL_SLICING
 
   input [7:0]                    addrx, addry; // the local address of the router, coded in 1-of-4 coding
   input                         rst_n;        // active low reset signal
 
   // internal wires, input buffers to switches (crossbar): [dir]2[cb][1-of-4 index]
   wire [VCN-1:0][SCN-1:0]         s2c0, s2c1, s2c2, s2c3; // south input to switch data
   wire [VCN-1:0][SCN-1:0]         w2c0, w2c1, w2c2, w2c3;
   wire [VCN-1:0][SCN-1:0]         n2c0, n2c1, n2c2, n2c3;
   wire [VCN-1:0][SCN-1:0]         e2c0, e2c1, e2c2, e2c3;
   wire [VCN-1:0][SCN-1:0]         l2c0, l2c1, l2c2, l2c3;
   // internal wires, switches (crossbar) to output buffers: [cb]2[dir][1-of-4 index]
   wire [VCN-1:0][SCN-1:0]         c2s0, c2s1, c2s2, c2s3;
   wire [VCN-1:0][SCN-1:0]         c2w0, c2w1, c2w2, c2w3;
   wire [VCN-1:0][SCN-1:0]         c2n0, c2n1, c2n2, c2n3; // switch to north output
   wire [VCN-1:0][SCN-1:0]         c2e0, c2e1, c2e2, c2e3;
   wire [VCN-1:0][SCN-1:0]         c2l0, c2l1, c2l2, c2l3;
 
   // internal wires for ack and eof bits
`ifdef ENABLE_CHANNEL_SLICING
   wire [VCN-1:0][SCN-1:0]         s2c4, w2c4, n2c4, e2c4, l2c4;
   wire [VCN-1:0][SCN-1:0]         c2s4, c2w4, c2n4, c2e4, c2l4;
   wire [VCN-1:0][SCN-1:0]         s2ca, w2ca, n2ca, e2ca, l2ca;
   wire [VCN-1:0][SCN-1:0]         c2sa, c2wa, c2na, c2ea, c2la;
`else
   wire [VCN-1:0]                 s2c4, w2c4, n2c4, e2c4, l2c4;
   wire [VCN-1:0]                 c2s4, c2w4, c2n4, c2e4, c2l4;
   wire [VCN-1:0]                 s2ca, w2ca, n2ca, e2ca, l2ca;
   wire [VCN-1:0]                 c2sa, c2wa, c2na, c2ea, c2la;
`endif // !`ifdef ENABLE_CHANNEL_SLICING
 
   // the requests/acks from/to input buffers to switch allocators
   wire [VCN-1:0][3:0]             sreq, nreq, lreq;
   wire [VCN-1:0][1:0]             wreq, ereq;
   wire [VCN-1:0]                 sack, wack, nack, eack, lack;
 
   // configuration bits for the switches
`ifdef ENABLE_CLOS
   wire [4:0][VCN-1:0][VCN-1:0]  imcfg;
   wire [VCN-1:0][1:0]             scfg, ncfg;
   wire [VCN-1:0][3:0]             wcfg, ecfg, lcfg;
`else // normal crossbar based SDM
   wire [VCN-1:0][2*VCN-1:0]       scfg, ncfg;
   wire [VCN-1:0][4*VCN-1:0]       wcfg, ecfg, lcfg;
`endif
 
 
   genvar                 i;
 
   generate
      for (i=0; i<VCN; i++) begin: SC
 
         // --------------- input buffers ------------------- //
 
         inp_buf #(.DIR(0), .RN(4), .DW(DW), .PD(IPD))
         SIB (
              .o0     ( s2c0[i]  ),
              .o1     ( s2c1[i]  ),
              .o2     ( s2c2[i]  ),
              .o3     ( s2c3[i]  ),
              .o4     ( s2c4[i]  ),
              .ia     ( sia[i]   ),
              .arb_r  ( sreq[i]  ),
              .rst_n  ( rst_n    ),
              .i0     ( si0[i]   ),
              .i1     ( si1[i]   ),
              .i2     ( si2[i]   ),
              .i3     ( si3[i]   ),
              .i4     ( si4[i]   ),
              .oa     ( s2ca[i]  ),
              .addrx  ( addrx    ),
              .addry  ( addry    ),
              .arb_ra ( sack[i]  )
              );
 
         inp_buf #(.DIR(1), .RN(2), .DW(DW), .PD(IPD))
         WIB (
              .o0     ( w2c0[i]  ),
              .o1     ( w2c1[i]  ),
              .o2     ( w2c2[i]  ),
              .o3     ( w2c3[i]  ),
              .o4     ( w2c4[i]  ),
              .ia     ( wia[i]   ),
              .arb_r  ( wreq[i]  ),
              .rst_n  ( rst_n    ),
              .i0     ( wi0[i]   ),
              .i1     ( wi1[i]   ),
              .i2     ( wi2[i]   ),
              .i3     ( wi3[i]   ),
              .i4     ( wi4[i]   ),
              .oa     ( w2ca[i]  ),
              .addrx  ( addrx    ),
              .addry  ( addry    ),
              .arb_ra ( wack[i]  )
              );
 
         inp_buf #(.DIR(2), .RN(4), .DW(DW), .PD(IPD))
         NIB (
              .o0     ( n2c0[i]  ),
              .o1     ( n2c1[i]  ),
              .o2     ( n2c2[i]  ),
              .o3     ( n2c3[i]  ),
              .o4     ( n2c4[i]  ),
              .ia     ( nia[i]   ),
              .arb_r  ( nreq[i]  ),
              .rst_n  ( rst_n    ),
              .i0     ( ni0[i]   ),
              .i1     ( ni1[i]   ),
              .i2     ( ni2[i]   ),
              .i3     ( ni3[i]   ),
              .i4     ( ni4[i]   ),
              .oa     ( n2ca[i]  ),
              .addrx  ( addrx    ),
              .addry  ( addry    ),
              .arb_ra ( nack[i]  )
              );
 
         inp_buf #(.DIR(3), .RN(2), .DW(DW), .PD(IPD))
         EIB (
              .o0     ( e2c0[i]  ),
              .o1     ( e2c1[i]  ),
              .o2     ( e2c2[i]  ),
              .o3     ( e2c3[i]  ),
              .o4     ( e2c4[i]  ),
              .ia     ( eia[i]   ),
              .arb_r  ( ereq[i]  ),
              .rst_n  ( rst_n    ),
              .i0     ( ei0[i]   ),
              .i1     ( ei1[i]   ),
              .i2     ( ei2[i]   ),
              .i3     ( ei3[i]   ),
              .i4     ( ei4[i]   ),
              .oa     ( e2ca[i]  ),
              .addrx  ( addrx    ),
              .addry  ( addry    ),
              .arb_ra ( eack[i]  )
              );
 
         inp_buf #(.DIR(4), .RN(4), .DW(DW), .PD(IPD))
         LIB (
              .o0     ( l2c0[i]  ),
              .o1     ( l2c1[i]  ),
              .o2     ( l2c2[i]  ),
              .o3     ( l2c3[i]  ),
              .o4     ( l2c4[i]  ),
              .ia     ( lia[i]   ),
              .arb_r  ( lreq[i]  ),
              .rst_n  ( rst_n    ),
              .i0     ( li0[i]   ),
              .i1     ( li1[i]   ),
              .i2     ( li2[i]   ),
              .i3     ( li3[i]   ),
              .i4     ( li4[i]   ),
              .oa     ( l2ca[i]  ),
              .addrx  ( addrx    ),
              .addry  ( addry    ),
              .arb_ra ( lack[i]  )
              );
 
         // --------------------- output buffers ---------------- //
         outp_buf #(.DW(DW), .PD(OPD))
         SOB (
              .o0     ( so0[i]   ),
              .o1     ( so1[i]   ),
              .o2     ( so2[i]   ),
              .o3     ( so3[i]   ),
              .o4     ( so4[i]   ),
              .oa     ( soa[i]   ),
              .i0     ( c2s0[i]  ),
              .i1     ( c2s1[i]  ),
              .i2     ( c2s2[i]  ),
              .i3     ( c2s3[i]  ),
              .i4     ( c2s4[i]  ),
              .ia     ( c2sa[i]  ),
              .rst_n  ( rst_n    )
              );
 
         outp_buf #(.DW(DW), .PD(OPD))
         WOB (
              .o0     ( wo0[i]   ),
              .o1     ( wo1[i]   ),
              .o2     ( wo2[i]   ),
              .o3     ( wo3[i]   ),
              .o4     ( wo4[i]   ),
              .oa     ( woa[i]   ),
              .i0     ( c2w0[i]  ),
              .i1     ( c2w1[i]  ),
              .i2     ( c2w2[i]  ),
              .i3     ( c2w3[i]  ),
              .i4     ( c2w4[i]  ),
              .ia     ( c2wa[i]  ),
              .rst_n  ( rst_n    )
              );
 
         outp_buf #(.DW(DW), .PD(OPD))
         NOB (
              .o0     ( no0[i]   ),
              .o1     ( no1[i]   ),
              .o2     ( no2[i]   ),
              .o3     ( no3[i]   ),
              .o4     ( no4[i]   ),
              .oa     ( noa[i]   ),
              .i0     ( c2n0[i]  ),
              .i1     ( c2n1[i]  ),
              .i2     ( c2n2[i]  ),
              .i3     ( c2n3[i]  ),
              .i4     ( c2n4[i]  ),
              .ia     ( c2na[i]  ),
              .rst_n  ( rst_n    )
              );
 
         outp_buf #(.DW(DW), .PD(OPD))
         EOB (
              .o0     ( eo0[i]   ),
              .o1     ( eo1[i]   ),
              .o2     ( eo2[i]   ),
              .o3     ( eo3[i]   ),
              .o4     ( eo4[i]   ),
              .oa     ( eoa[i]   ),
              .i0     ( c2e0[i]  ),
              .i1     ( c2e1[i]  ),
              .i2     ( c2e2[i]  ),
              .i3     ( c2e3[i]  ),
              .i4     ( c2e4[i]  ),
              .ia     ( c2ea[i]  ),
              .rst_n  ( rst_n    )
              );
 
         outp_buf #(.DW(DW), .PD(OPD))
         LOB (
              .o0     ( lo0[i]   ),
              .o1     ( lo1[i]   ),
              .o2     ( lo2[i]   ),
              .o3     ( lo3[i]   ),
              .o4     ( lo4[i]   ),
              .oa     ( loa[i]   ),
              .i0     ( c2l0[i]  ),
              .i1     ( c2l1[i]  ),
              .i2     ( c2l2[i]  ),
              .i3     ( c2l3[i]  ),
              .i4     ( c2l4[i]  ),
              .ia     ( c2la[i]  ),
              .rst_n  ( rst_n    )
              );
 
      end // block: SC
   endgenerate
 
`ifdef ENABLE_CLOS
   dclos #(.MN(VCN), .NN(VCN), .DW(DW))
   CB (
       .so0     ( c2s0      ),
       .so1     ( c2s1      ),
       .so2     ( c2s2      ),
       .so3     ( c2s3      ),
       .so4     ( c2s4      ),
       .soa     ( c2sa      ),
       .wo0     ( c2w0      ),
       .wo1     ( c2w1      ),
       .wo2     ( c2w2      ),
       .wo3     ( c2w3      ),
       .wo4     ( c2w4      ),
       .woa     ( c2wa      ),
       .no0     ( c2n0      ),
       .no1     ( c2n1      ),
       .no2     ( c2n2      ),
       .no3     ( c2n3      ),
       .no4     ( c2n4      ),
       .noa     ( c2na      ),
       .eo0     ( c2e0      ),
       .eo1     ( c2e1      ),
       .eo2     ( c2e2      ),
       .eo3     ( c2e3      ),
       .eo4     ( c2e4      ),
       .eoa     ( c2ea      ),
       .lo0     ( c2l0      ),
       .lo1     ( c2l1      ),
       .lo2     ( c2l2      ),
       .lo3     ( c2l3      ),
       .lo4     ( c2l4      ),
       .loa     ( c2la      ),
       .si0     ( s2c0      ),
       .si1     ( s2c1      ),
       .si2     ( s2c2      ),
       .si3     ( s2c3      ),
       .si4     ( s2c4      ),
       .sia     ( s2ca      ),
       .wi0     ( w2c0      ),
       .wi1     ( w2c1      ),
       .wi2     ( w2c2      ),
       .wi3     ( w2c3      ),
       .wi4     ( w2c4      ),
       .wia     ( w2ca      ),
       .ni0     ( n2c0      ),
       .ni1     ( n2c1      ),
       .ni2     ( n2c2      ),
       .ni3     ( n2c3      ),
       .ni4     ( n2c4      ),
       .nia     ( n2ca      ),
       .ei0     ( e2c0      ),
       .ei1     ( e2c1      ),
       .ei2     ( e2c2      ),
       .ei3     ( e2c3      ),
       .ei4     ( e2c4      ),
       .eia     ( e2ca      ),
       .li0     ( l2c0      ),
       .li1     ( l2c1      ),
       .li2     ( l2c2      ),
       .li3     ( l2c3      ),
       .li4     ( l2c4      ),
       .lia     ( l2ca      ),
       .imcfg   ( imcfg     ),
       .wcfg    ( wcfg      ),
       .ecfg    ( ecfg      ),
       .lcfg    ( lcfg      ),
       .scfg    ( scfg      ),
       .ncfg    ( ncfg      )
       ) ;
 
   clos_sch #(.M(VCN), .N(VCN))
   ALLOC (
          .sack  ( sack    ),
          .wack  ( wack    ),
          .nack  ( nack    ),
          .eack  ( eack    ),
          .lack  ( lack    ),
          .imc   ( imcfg   ),
          .scfg  ( scfg    ),
          .ncfg  ( ncfg    ),
          .wcfg  ( wcfg    ),
          .ecfg  ( ecfg    ),
          .lcfg  ( lcfg    ),
          .sreq  ( sreq    ),
          .nreq  ( nreq    ),
          .lreq  ( lreq    ),
          .wreq  ( wreq    ),
          .ereq  ( ereq    ),
          .rst_n ( rst_n   )
          );
`else  // Crossbar based SDM
 
   dcb_xy #(.VCN(VCN), .VCW(DW))
   CB (
       .so0     ( c2s0      ),
       .so1     ( c2s1      ),
       .so2     ( c2s2      ),
       .so3     ( c2s3      ),
       .so4     ( c2s4      ),
       .soa     ( c2sa      ),
       .wo0     ( c2w0      ),
       .wo1     ( c2w1      ),
       .wo2     ( c2w2      ),
       .wo3     ( c2w3      ),
       .wo4     ( c2w4      ),
       .woa     ( c2wa      ),
       .no0     ( c2n0      ),
       .no1     ( c2n1      ),
       .no2     ( c2n2      ),
       .no3     ( c2n3      ),
       .no4     ( c2n4      ),
       .noa     ( c2na      ),
       .eo0     ( c2e0      ),
       .eo1     ( c2e1      ),
       .eo2     ( c2e2      ),
       .eo3     ( c2e3      ),
       .eo4     ( c2e4      ),
       .eoa     ( c2ea      ),
       .lo0     ( c2l0      ),
       .lo1     ( c2l1      ),
       .lo2     ( c2l2      ),
       .lo3     ( c2l3      ),
       .lo4     ( c2l4      ),
       .loa     ( c2la      ),
       .si0     ( s2c0      ),
       .si1     ( s2c1      ),
       .si2     ( s2c2      ),
       .si3     ( s2c3      ),
       .si4     ( s2c4      ),
       .sia     ( s2ca      ),
       .wi0     ( w2c0      ),
       .wi1     ( w2c1      ),
       .wi2     ( w2c2      ),
       .wi3     ( w2c3      ),
       .wi4     ( w2c4      ),
       .wia     ( w2ca      ),
       .ni0     ( n2c0      ),
       .ni1     ( n2c1      ),
       .ni2     ( n2c2      ),
       .ni3     ( n2c3      ),
       .ni4     ( n2c4      ),
       .nia     ( n2ca      ),
       .ei0     ( e2c0      ),
       .ei1     ( e2c1      ),
       .ei2     ( e2c2      ),
       .ei3     ( e2c3      ),
       .ei4     ( e2c4      ),
       .eia     ( e2ca      ),
       .li0     ( l2c0      ),
       .li1     ( l2c1      ),
       .li2     ( l2c2      ),
       .li3     ( l2c3      ),
       .li4     ( l2c4      ),
       .lia     ( l2ca      ),
       .wcfg    ( wcfg      ),
       .ecfg    ( ecfg      ),
       .lcfg    ( lcfg      ),
       .scfg    ( scfg      ),
       .ncfg    ( ncfg      )
       ) ;
 
 
   sdm_sch #(.VCN(VCN))
   ALLOC (
          .sack  ( sack    ),
          .wack  ( wack    ),
          .nack  ( nack    ),
          .eack  ( eack    ),
          .lack  ( lack    ),
          .scfg  ( scfg    ),
          .ncfg  ( ncfg    ),
          .wcfg  ( wcfg    ),
          .ecfg  ( ecfg    ),
          .lcfg  ( lcfg    ),
          .sreq  ( sreq    ),
          .nreq  ( nreq    ),
          .lreq  ( lreq    ),
          .wreq  ( wreq    ),
          .ereq  ( ereq    ),
          .rst_n ( rst_n   )
          );
`endif
 
endmodule // router

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[/] [async_sdm_noc/] [trunk/] [sdm/] [src/] [router.v] - Blame information for rev 29

Line No.	Rev	Author	Line
1	13	wsong0210	`/*`
2			`Asynchronous SDM NoC`
3			`(C)2011 Wei Song`
4			`Advanced Processor Technologies Group`
5			`Computer Science, the Univ. of Manchester, UK`
6
7			`Authors:`
8			`Wei Song wsong83@gmail.com`
9
10			`License: LGPL 3.0 or later`
11
12			`Wormhole/SDM router top level module`
13			`* SystemVerilog is used *`
14
15			`History:`
16			`28/05/2009 Initial version. <wsong83@gmail.com>`
17			`23/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>`
18			`22/10/2010 Parameterize the number of pipelines in output buffers. <wsong83@gmail.com>`
19	19	wsong0210	`25/05/2011 Clean up for opensource. <wsong83@gmail.com>`
20	13	wsong0210
21			`*/`
22
23			`// the router structure definitions`
24			`include "define.v"
25
26			`module router(/AUTOARG/`
27			`// Outputs`
28			`so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,`
29			`eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,`
30			`wia, nia, eia, lia,`
31			`// Inputs`
32			`si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,`
33			`ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,`
34			`woa, noa, eoa, loa, addrx, addry, rst_n`
35			`);`
36
37			`parameter VCN = 1; // number of virtual circuits in each direction. When VCN == 1, it is a wormhole router`
38			`parameter DW = 32; // the datawidth of a single virtual circuit, the total data width of the router is DW*VCN`
39			`parameter IPD = 1; // the number of half-buffer stages in input buffers`
40			`parameter OPD = 2; // the number of half-buffer stages in output buffers`
41			`parameter SCN = DW/2; // the number of 1-of-4 sub-channel in each virtual circuit`
42
43			`input [VCN-1:0][SCN-1:0] si0, si1, si2, si3; // south input [0], X+1`
44			`input [VCN-1:0][SCN-1:0] wi0, wi1, wi2, wi3; // west input [1], Y-1`
45			`input [VCN-1:0][SCN-1:0] ni0, ni1, ni2, ni3; // north input [2], X-1`
46			`input [VCN-1:0][SCN-1:0] ei0, ei1, ei2, ei3; // east input [3], Y+1`
47			`input [VCN-1:0][SCN-1:0] li0, li1, li2, li3; // local input`
48			`output [VCN-1:0][SCN-1:0] so0, so1, so2, so3; // south output`
49			`output [VCN-1:0][SCN-1:0] wo0, wo1, wo2, wo3; // west output`
50			`output [VCN-1:0][SCN-1:0] no0, no1, no2, no3; // north output`
51			`output [VCN-1:0][SCN-1:0] eo0, eo1, eo2, eo3; // east output`
52			`output [VCN-1:0][SCN-1:0] lo0, lo1, lo2, lo3; // local output`
53
54			`// eof bits and ack lines`
55			`ifdef ENABLE_CHANNEL_SLICING
56			`input [VCN-1:0][SCN-1:0] si4, wi4, ni4, ei4, li4;`
57			`output [VCN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4;`
58			`output [VCN-1:0][SCN-1:0] sia, wia, nia, eia, lia;`
59			`input [VCN-1:0][SCN-1:0] soa, woa, noa, eoa, loa;`
60			`else
61			`input [VCN-1:0] si4, wi4, ni4, ei4, li4;`
62			`output [VCN-1:0] so4, wo4, no4, eo4, lo4;`
63			`output [VCN-1:0] sia, wia, nia, eia, lia;`
64			`input [VCN-1:0] soa, woa, noa, eoa, loa;`
65			`endif // !`ifdef ENABLE_CHANNEL_SLICING
66
67			`input [7:0] addrx, addry; // the local address of the router, coded in 1-of-4 coding`
68			`input rst_n; // active low reset signal`
69
70			`// internal wires, input buffers to switches (crossbar): [dir]2[cb][1-of-4 index]`
71			`wire [VCN-1:0][SCN-1:0] s2c0, s2c1, s2c2, s2c3; // south input to switch data`
72			`wire [VCN-1:0][SCN-1:0] w2c0, w2c1, w2c2, w2c3;`
73			`wire [VCN-1:0][SCN-1:0] n2c0, n2c1, n2c2, n2c3;`
74			`wire [VCN-1:0][SCN-1:0] e2c0, e2c1, e2c2, e2c3;`
75			`wire [VCN-1:0][SCN-1:0] l2c0, l2c1, l2c2, l2c3;`
76			`// internal wires, switches (crossbar) to output buffers: [cb]2[dir][1-of-4 index]`
77			`wire [VCN-1:0][SCN-1:0] c2s0, c2s1, c2s2, c2s3;`
78			`wire [VCN-1:0][SCN-1:0] c2w0, c2w1, c2w2, c2w3;`
79			`wire [VCN-1:0][SCN-1:0] c2n0, c2n1, c2n2, c2n3; // switch to north output`
80			`wire [VCN-1:0][SCN-1:0] c2e0, c2e1, c2e2, c2e3;`
81			`wire [VCN-1:0][SCN-1:0] c2l0, c2l1, c2l2, c2l3;`
82
83			`// internal wires for ack and eof bits`
84			`ifdef ENABLE_CHANNEL_SLICING
85			`wire [VCN-1:0][SCN-1:0] s2c4, w2c4, n2c4, e2c4, l2c4;`
86			`wire [VCN-1:0][SCN-1:0] c2s4, c2w4, c2n4, c2e4, c2l4;`
87			`wire [VCN-1:0][SCN-1:0] s2ca, w2ca, n2ca, e2ca, l2ca;`
88			`wire [VCN-1:0][SCN-1:0] c2sa, c2wa, c2na, c2ea, c2la;`
89			`else
90			`wire [VCN-1:0] s2c4, w2c4, n2c4, e2c4, l2c4;`
91			`wire [VCN-1:0] c2s4, c2w4, c2n4, c2e4, c2l4;`
92			`wire [VCN-1:0] s2ca, w2ca, n2ca, e2ca, l2ca;`
93			`wire [VCN-1:0] c2sa, c2wa, c2na, c2ea, c2la;`
94			`endif // !`ifdef ENABLE_CHANNEL_SLICING
95
96			`// the requests/acks from/to input buffers to switch allocators`
97			`wire [VCN-1:0][3:0] sreq, nreq, lreq;`
98			`wire [VCN-1:0][1:0] wreq, ereq;`
99			`wire [VCN-1:0] sack, wack, nack, eack, lack;`
100
101			`// configuration bits for the switches`
102			`ifdef ENABLE_CLOS
103			`wire [4:0][VCN-1:0][VCN-1:0] imcfg;`
104			`wire [VCN-1:0][1:0] scfg, ncfg;`
105			`wire [VCN-1:0][3:0] wcfg, ecfg, lcfg;`
106			`else // normal crossbar based SDM
107			`wire [VCN-1:0][2*VCN-1:0] scfg, ncfg;`
108			`wire [VCN-1:0][4*VCN-1:0] wcfg, ecfg, lcfg;`
109			`endif
110
111
112			`genvar i;`
113
114			`generate`
115			`for (i=0; i<VCN; i++) begin: SC`
116
117			`// --------------- input buffers ------------------- //`
118
119			`inp_buf #(.DIR(0), .RN(4), .DW(DW), .PD(IPD))`
120			`SIB (`
121			`.o0 ( s2c0[i] ),`
122			`.o1 ( s2c1[i] ),`
123			`.o2 ( s2c2[i] ),`
124			`.o3 ( s2c3[i] ),`
125			`.o4 ( s2c4[i] ),`
126			`.ia ( sia[i] ),`
127			`.arb_r ( sreq[i] ),`
128			`.rst_n ( rst_n ),`
129			`.i0 ( si0[i] ),`
130			`.i1 ( si1[i] ),`
131			`.i2 ( si2[i] ),`
132			`.i3 ( si3[i] ),`
133			`.i4 ( si4[i] ),`
134			`.oa ( s2ca[i] ),`
135			`.addrx ( addrx ),`
136			`.addry ( addry ),`
137			`.arb_ra ( sack[i] )`
138			`);`
139
140			`inp_buf #(.DIR(1), .RN(2), .DW(DW), .PD(IPD))`
141			`WIB (`
142			`.o0 ( w2c0[i] ),`
143			`.o1 ( w2c1[i] ),`
144			`.o2 ( w2c2[i] ),`
145			`.o3 ( w2c3[i] ),`
146			`.o4 ( w2c4[i] ),`
147			`.ia ( wia[i] ),`
148			`.arb_r ( wreq[i] ),`
149			`.rst_n ( rst_n ),`
150			`.i0 ( wi0[i] ),`
151			`.i1 ( wi1[i] ),`
152			`.i2 ( wi2[i] ),`
153			`.i3 ( wi3[i] ),`
154			`.i4 ( wi4[i] ),`
155			`.oa ( w2ca[i] ),`
156			`.addrx ( addrx ),`
157			`.addry ( addry ),`
158			`.arb_ra ( wack[i] )`
159			`);`
160
161			`inp_buf #(.DIR(2), .RN(4), .DW(DW), .PD(IPD))`
162			`NIB (`
163			`.o0 ( n2c0[i] ),`
164			`.o1 ( n2c1[i] ),`
165			`.o2 ( n2c2[i] ),`
166			`.o3 ( n2c3[i] ),`
167			`.o4 ( n2c4[i] ),`
168			`.ia ( nia[i] ),`
169			`.arb_r ( nreq[i] ),`
170			`.rst_n ( rst_n ),`
171			`.i0 ( ni0[i] ),`
172			`.i1 ( ni1[i] ),`
173			`.i2 ( ni2[i] ),`
174			`.i3 ( ni3[i] ),`
175			`.i4 ( ni4[i] ),`
176			`.oa ( n2ca[i] ),`
177			`.addrx ( addrx ),`
178			`.addry ( addry ),`
179			`.arb_ra ( nack[i] )`
180			`);`
181
182			`inp_buf #(.DIR(3), .RN(2), .DW(DW), .PD(IPD))`
183			`EIB (`
184			`.o0 ( e2c0[i] ),`
185			`.o1 ( e2c1[i] ),`
186			`.o2 ( e2c2[i] ),`
187			`.o3 ( e2c3[i] ),`
188			`.o4 ( e2c4[i] ),`
189			`.ia ( eia[i] ),`
190			`.arb_r ( ereq[i] ),`
191			`.rst_n ( rst_n ),`
192			`.i0 ( ei0[i] ),`
193			`.i1 ( ei1[i] ),`
194			`.i2 ( ei2[i] ),`
195			`.i3 ( ei3[i] ),`
196			`.i4 ( ei4[i] ),`
197			`.oa ( e2ca[i] ),`
198			`.addrx ( addrx ),`
199			`.addry ( addry ),`
200			`.arb_ra ( eack[i] )`
201			`);`
202
203			`inp_buf #(.DIR(4), .RN(4), .DW(DW), .PD(IPD))`
204			`LIB (`
205			`.o0 ( l2c0[i] ),`
206			`.o1 ( l2c1[i] ),`
207			`.o2 ( l2c2[i] ),`
208			`.o3 ( l2c3[i] ),`
209			`.o4 ( l2c4[i] ),`
210			`.ia ( lia[i] ),`
211			`.arb_r ( lreq[i] ),`
212			`.rst_n ( rst_n ),`
213			`.i0 ( li0[i] ),`
214			`.i1 ( li1[i] ),`
215			`.i2 ( li2[i] ),`
216			`.i3 ( li3[i] ),`
217			`.i4 ( li4[i] ),`
218			`.oa ( l2ca[i] ),`
219			`.addrx ( addrx ),`
220			`.addry ( addry ),`
221			`.arb_ra ( lack[i] )`
222			`);`
223
224			`// --------------------- output buffers ---------------- //`
225			`outp_buf #(.DW(DW), .PD(OPD))`
226			`SOB (`
227			`.o0 ( so0[i] ),`
228			`.o1 ( so1[i] ),`
229			`.o2 ( so2[i] ),`
230			`.o3 ( so3[i] ),`
231			`.o4 ( so4[i] ),`
232			`.oa ( soa[i] ),`
233			`.i0 ( c2s0[i] ),`
234			`.i1 ( c2s1[i] ),`
235			`.i2 ( c2s2[i] ),`
236			`.i3 ( c2s3[i] ),`
237			`.i4 ( c2s4[i] ),`
238			`.ia ( c2sa[i] ),`
239			`.rst_n ( rst_n )`
240			`);`
241
242			`outp_buf #(.DW(DW), .PD(OPD))`
243			`WOB (`
244			`.o0 ( wo0[i] ),`
245			`.o1 ( wo1[i] ),`
246			`.o2 ( wo2[i] ),`
247			`.o3 ( wo3[i] ),`
248			`.o4 ( wo4[i] ),`
249			`.oa ( woa[i] ),`
250			`.i0 ( c2w0[i] ),`
251			`.i1 ( c2w1[i] ),`
252			`.i2 ( c2w2[i] ),`
253			`.i3 ( c2w3[i] ),`
254			`.i4 ( c2w4[i] ),`
255			`.ia ( c2wa[i] ),`
256			`.rst_n ( rst_n )`
257			`);`
258
259			`outp_buf #(.DW(DW), .PD(OPD))`
260			`NOB (`
261			`.o0 ( no0[i] ),`
262			`.o1 ( no1[i] ),`
263			`.o2 ( no2[i] ),`
264			`.o3 ( no3[i] ),`
265			`.o4 ( no4[i] ),`
266			`.oa ( noa[i] ),`
267			`.i0 ( c2n0[i] ),`
268			`.i1 ( c2n1[i] ),`
269			`.i2 ( c2n2[i] ),`
270			`.i3 ( c2n3[i] ),`
271			`.i4 ( c2n4[i] ),`
272			`.ia ( c2na[i] ),`
273			`.rst_n ( rst_n )`
274			`);`
275
276			`outp_buf #(.DW(DW), .PD(OPD))`
277			`EOB (`
278			`.o0 ( eo0[i] ),`
279			`.o1 ( eo1[i] ),`
280			`.o2 ( eo2[i] ),`
281			`.o3 ( eo3[i] ),`
282			`.o4 ( eo4[i] ),`
283			`.oa ( eoa[i] ),`
284			`.i0 ( c2e0[i] ),`
285			`.i1 ( c2e1[i] ),`
286			`.i2 ( c2e2[i] ),`
287			`.i3 ( c2e3[i] ),`
288			`.i4 ( c2e4[i] ),`
289			`.ia ( c2ea[i] ),`
290			`.rst_n ( rst_n )`
291			`);`
292
293			`outp_buf #(.DW(DW), .PD(OPD))`
294			`LOB (`
295			`.o0 ( lo0[i] ),`
296			`.o1 ( lo1[i] ),`
297			`.o2 ( lo2[i] ),`
298			`.o3 ( lo3[i] ),`
299			`.o4 ( lo4[i] ),`
300			`.oa ( loa[i] ),`
301			`.i0 ( c2l0[i] ),`
302			`.i1 ( c2l1[i] ),`
303			`.i2 ( c2l2[i] ),`
304			`.i3 ( c2l3[i] ),`
305			`.i4 ( c2l4[i] ),`
306			`.ia ( c2la[i] ),`
307			`.rst_n ( rst_n )`
308			`);`
309
310			`end // block: SC`
311			`endgenerate`
312
313			`ifdef ENABLE_CLOS
314			`dclos #(.MN(VCN), .NN(VCN), .DW(DW))`
315			`CB (`
316			`.so0 ( c2s0 ),`
317			`.so1 ( c2s1 ),`
318			`.so2 ( c2s2 ),`
319			`.so3 ( c2s3 ),`
320			`.so4 ( c2s4 ),`
321			`.soa ( c2sa ),`
322			`.wo0 ( c2w0 ),`
323			`.wo1 ( c2w1 ),`
324			`.wo2 ( c2w2 ),`
325			`.wo3 ( c2w3 ),`
326			`.wo4 ( c2w4 ),`
327			`.woa ( c2wa ),`
328			`.no0 ( c2n0 ),`
329			`.no1 ( c2n1 ),`
330			`.no2 ( c2n2 ),`
331			`.no3 ( c2n3 ),`
332			`.no4 ( c2n4 ),`
333			`.noa ( c2na ),`
334			`.eo0 ( c2e0 ),`
335			`.eo1 ( c2e1 ),`
336			`.eo2 ( c2e2 ),`
337			`.eo3 ( c2e3 ),`
338			`.eo4 ( c2e4 ),`
339			`.eoa ( c2ea ),`
340			`.lo0 ( c2l0 ),`
341			`.lo1 ( c2l1 ),`
342			`.lo2 ( c2l2 ),`
343			`.lo3 ( c2l3 ),`
344			`.lo4 ( c2l4 ),`
345			`.loa ( c2la ),`
346			`.si0 ( s2c0 ),`
347			`.si1 ( s2c1 ),`
348			`.si2 ( s2c2 ),`
349			`.si3 ( s2c3 ),`
350			`.si4 ( s2c4 ),`
351			`.sia ( s2ca ),`
352			`.wi0 ( w2c0 ),`
353			`.wi1 ( w2c1 ),`
354			`.wi2 ( w2c2 ),`
355			`.wi3 ( w2c3 ),`
356			`.wi4 ( w2c4 ),`
357			`.wia ( w2ca ),`
358			`.ni0 ( n2c0 ),`
359			`.ni1 ( n2c1 ),`
360			`.ni2 ( n2c2 ),`
361			`.ni3 ( n2c3 ),`
362			`.ni4 ( n2c4 ),`
363			`.nia ( n2ca ),`
364			`.ei0 ( e2c0 ),`
365			`.ei1 ( e2c1 ),`
366			`.ei2 ( e2c2 ),`
367			`.ei3 ( e2c3 ),`
368			`.ei4 ( e2c4 ),`
369			`.eia ( e2ca ),`
370			`.li0 ( l2c0 ),`
371			`.li1 ( l2c1 ),`
372			`.li2 ( l2c2 ),`
373			`.li3 ( l2c3 ),`
374			`.li4 ( l2c4 ),`
375			`.lia ( l2ca ),`
376			`.imcfg ( imcfg ),`
377			`.wcfg ( wcfg ),`
378			`.ecfg ( ecfg ),`
379			`.lcfg ( lcfg ),`
380			`.scfg ( scfg ),`
381			`.ncfg ( ncfg )`
382			`) ;`
383
384			`clos_sch #(.M(VCN), .N(VCN))`
385			`ALLOC (`
386			`.sack ( sack ),`
387			`.wack ( wack ),`
388			`.nack ( nack ),`
389			`.eack ( eack ),`
390			`.lack ( lack ),`
391			`.imc ( imcfg ),`
392			`.scfg ( scfg ),`
393			`.ncfg ( ncfg ),`
394			`.wcfg ( wcfg ),`
395			`.ecfg ( ecfg ),`
396			`.lcfg ( lcfg ),`
397			`.sreq ( sreq ),`
398			`.nreq ( nreq ),`
399			`.lreq ( lreq ),`
400			`.wreq ( wreq ),`
401			`.ereq ( ereq ),`
402			`.rst_n ( rst_n )`
403			`);`
404			`else // Crossbar based SDM
405
406	28	wsong0210	`dcb_xy #(.VCN(VCN), .VCW(DW))`
407	13	wsong0210	`CB (`
408			`.so0 ( c2s0 ),`
409			`.so1 ( c2s1 ),`
410			`.so2 ( c2s2 ),`
411			`.so3 ( c2s3 ),`
412			`.so4 ( c2s4 ),`
413			`.soa ( c2sa ),`
414			`.wo0 ( c2w0 ),`
415			`.wo1 ( c2w1 ),`
416			`.wo2 ( c2w2 ),`
417			`.wo3 ( c2w3 ),`
418			`.wo4 ( c2w4 ),`
419			`.woa ( c2wa ),`
420			`.no0 ( c2n0 ),`
421			`.no1 ( c2n1 ),`
422			`.no2 ( c2n2 ),`
423			`.no3 ( c2n3 ),`
424			`.no4 ( c2n4 ),`
425			`.noa ( c2na ),`
426			`.eo0 ( c2e0 ),`
427			`.eo1 ( c2e1 ),`
428			`.eo2 ( c2e2 ),`
429			`.eo3 ( c2e3 ),`
430			`.eo4 ( c2e4 ),`
431			`.eoa ( c2ea ),`
432			`.lo0 ( c2l0 ),`
433			`.lo1 ( c2l1 ),`
434			`.lo2 ( c2l2 ),`
435			`.lo3 ( c2l3 ),`
436			`.lo4 ( c2l4 ),`
437			`.loa ( c2la ),`
438			`.si0 ( s2c0 ),`
439			`.si1 ( s2c1 ),`
440			`.si2 ( s2c2 ),`
441			`.si3 ( s2c3 ),`
442			`.si4 ( s2c4 ),`
443			`.sia ( s2ca ),`
444			`.wi0 ( w2c0 ),`
445			`.wi1 ( w2c1 ),`
446			`.wi2 ( w2c2 ),`
447			`.wi3 ( w2c3 ),`
448			`.wi4 ( w2c4 ),`
449			`.wia ( w2ca ),`
450			`.ni0 ( n2c0 ),`
451			`.ni1 ( n2c1 ),`
452			`.ni2 ( n2c2 ),`
453			`.ni3 ( n2c3 ),`
454			`.ni4 ( n2c4 ),`
455			`.nia ( n2ca ),`
456			`.ei0 ( e2c0 ),`
457			`.ei1 ( e2c1 ),`
458			`.ei2 ( e2c2 ),`
459			`.ei3 ( e2c3 ),`
460			`.ei4 ( e2c4 ),`
461			`.eia ( e2ca ),`
462			`.li0 ( l2c0 ),`
463			`.li1 ( l2c1 ),`
464			`.li2 ( l2c2 ),`
465			`.li3 ( l2c3 ),`
466			`.li4 ( l2c4 ),`
467			`.lia ( l2ca ),`
468			`.wcfg ( wcfg ),`
469			`.ecfg ( ecfg ),`
470			`.lcfg ( lcfg ),`
471			`.scfg ( scfg ),`
472			`.ncfg ( ncfg )`
473			`) ;`
474
475
476			`sdm_sch #(.VCN(VCN))`
477			`ALLOC (`
478			`.sack ( sack ),`
479			`.wack ( wack ),`
480			`.nack ( nack ),`
481			`.eack ( eack ),`
482			`.lack ( lack ),`
483			`.scfg ( scfg ),`
484			`.ncfg ( ncfg ),`
485			`.wcfg ( wcfg ),`
486			`.ecfg ( ecfg ),`
487			`.lcfg ( lcfg ),`
488			`.sreq ( sreq ),`
489			`.nreq ( nreq ),`
490			`.lreq ( lreq ),`
491			`.wreq ( wreq ),`
492	19	wsong0210	`.ereq ( ereq ),`
493			`.rst_n ( rst_n )`
494	13	wsong0210	`);`
495			`endif
496
497			`endmodule // router`