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/*
 Asynchronous SDM NoC
 (C)2011 Wei Song
 Advanced Processor Technologies Group
 Computer Science, the Univ. of Manchester, UK
 
 Authors:
 Wei Song     wsong83@gmail.com
 
 License: LGPL 3.0 or later
 
 Crossbar based SDM switch allocator
 *** SystemVerilog is used ***
 
 References
 For the detail structure, please refer to Section 6.3.1 of the thesis:
   Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011.
 
 History:
 28/09/2009  Initial version. <wsong83@gmail.com>
 27/05/2011  Clean up for opensource. <wsong83@gmail.com>
 
*/
 
// the router structure definitions
`include "define.v"
 
module sdm_sch (/*AUTOARG*/
   // Outputs
   sack, wack, nack, eack, lack, scfg, ncfg, wcfg, ecfg, lcfg,
   // Inputs
   sreq, nreq, lreq, wreq, ereq, rst_n
   );
 
   parameter VCN = 2;           // the number of virtual circuits per port
 
   // income requests
   input [VCN-1:0][3:0]            sreq, nreq, lreq;
   input [VCN-1:0][1:0]      wreq, ereq;
 
   // ack to input buffers
   output [VCN-1:0]                 sack, wack, nack, eack, lack;
 
   // configuration to the crossbar
   output [VCN-1:0][1:0][VCN-1:0]  scfg, ncfg;
   output [VCN-1:0][3:0][VCN-1:0]  wcfg, ecfg, lcfg;
 
   input                           rst_n; // active low global reset
 
   // requests to arbiters
`ifndef ENABLE_MRMA
   wire [1:0][VCN-1:0][VCN-1:0]    r2s, r2n; // shuffle the incoming request signals
   wire [3:0][VCN-1:0][VCN-1:0]    r2w, r2e, r2l;
`else
   wire [1:0][VCN-1:0]               r2s, r2n; // shuffle the incoming request signals
   wire [3:0][VCN-1:0]               r2w, r2e, r2l;
`endif
 
   // ack from arbiters
   wire [VCN-1:0][3:0]               a2s, a2n, a2l;
   wire [VCN-1:0][1:0]               a2w, a2e;
 
   // ack of the arbiters
   wire [1:0][VCN-1:0]               r2sa, r2na;
   wire [3:0][VCN-1:0]               r2wa, r2ea, r2la;
 
`ifdef ENABLE_MRMA
   wire [VCN:0]             OPrst_n; // the buffered resets to avoid metastability
   wire [VCN-1:0]                   SOPrdy, SOPblk; // OP ready and blocked status
   wire [VCN-1:0]                   WOPrdy, WOPblk; // OP ready and blocked status
   wire [VCN-1:0]                   NOPrdy, NOPblk; // OP ready and blocked status
   wire [VCN-1:0]                   EOPrdy, EOPblk; // OP ready and blocked status
   wire [VCN-1:0]                   LOPrdy, LOPblk; // OP ready and blocked status
`endif
 
   genvar                          i,j;
 
   // wire shuffle
   generate for(i=0; i<VCN; i++) begin: SHUF
`ifndef ENABLE_MRMA
      for(j=0; j<VCN; j++) begin: CO
         assign r2s[0][i][j] = nreq[i][0];
         assign r2s[1][i][j] = lreq[i][0];
         assign r2w[0][i][j] = sreq[i][0];
         assign r2w[1][i][j] = nreq[i][1];
         assign r2w[2][i][j] = ereq[i][0];
         assign r2w[3][i][j] = lreq[i][1];
         assign r2n[0][i][j] = sreq[i][1];
         assign r2n[1][i][j] = lreq[i][2];
         assign r2e[0][i][j] = sreq[i][2];
         assign r2e[1][i][j] = wreq[i][0];
         assign r2e[2][i][j] = nreq[i][2];
         assign r2e[3][i][j] = lreq[i][3];
         assign r2l[0][i][j] = sreq[i][3];
         assign r2l[1][i][j] = wreq[i][1];
         assign r2l[2][i][j] = nreq[i][3];
         assign r2l[3][i][j] = ereq[i][1];
      end // block: CO
`else // !`ifndef ENABLE_MRMA
      assign r2s[0][i] = nreq[i][0];
      assign r2s[1][i] = lreq[i][0];
      assign r2w[0][i] = sreq[i][0];
      assign r2w[1][i] = nreq[i][1];
      assign r2w[2][i] = ereq[i][0];
      assign r2w[3][i] = lreq[i][1];
      assign r2n[0][i] = sreq[i][1];
      assign r2n[1][i] = lreq[i][2];
      assign r2e[0][i] = sreq[i][2];
      assign r2e[1][i] = wreq[i][0];
      assign r2e[2][i] = nreq[i][2];
      assign r2e[3][i] = lreq[i][3];
      assign r2l[0][i] = sreq[i][3];
      assign r2l[1][i] = wreq[i][1];
      assign r2l[2][i] = nreq[i][3];
      assign r2l[3][i] = ereq[i][1];
`endif // !`ifndef ENABLE_MRMA
      assign a2s[i][0] = r2wa[0][i];
      assign a2s[i][1] = r2na[0][i];
      assign a2s[i][2] = r2ea[0][i];
      assign a2s[i][3] = r2la[0][i];
      assign a2w[i][0] = r2ea[1][i];
      assign a2w[i][1] = r2la[1][i];
      assign a2n[i][0] = r2sa[0][i];
      assign a2n[i][1] = r2wa[1][i];
      assign a2n[i][2] = r2ea[2][i];
      assign a2n[i][3] = r2la[2][i];
      assign a2e[i][0] = r2wa[2][i];
      assign a2e[i][1] = r2la[3][i];
      assign a2l[i][0] = r2sa[1][i];
      assign a2l[i][1] = r2wa[3][i];
      assign a2l[i][2] = r2na[1][i];
      assign a2l[i][3] = r2ea[3][i];
      assign sack[i] = |a2s[i];
      assign wack[i] = |a2w[i];
      assign nack[i] = |a2n[i];
      assign eack[i] = |a2e[i];
      assign lack[i] = |a2l[i];
 
   end // block: SHUF
   endgenerate
 
   // output port arbiter/allocators
`ifndef ENABLE_MRMA
   mnma #(.N(2*VCN), .M(VCN))
   SCBA (
         .r     ( r2s    ),
         .ra    ( r2sa   ),
         .cfg   ( scfg   )
         );
 
   mnma #(.N(4*VCN), .M(VCN))
   WCBA (
         .r     ( r2w    ),
         .ra    ( r2wa   ),
         .cfg   ( wcfg   )
         );
 
   mnma #(.N(2*VCN), .M(VCN))
   NCBA (
         .r     ( r2n    ),
         .ra    ( r2na   ),
         .cfg   ( ncfg   )
         );
 
   mnma #(.N(4*VCN), .M(VCN))
   ECBA (
         .r     ( r2e    ),
         .ra    ( r2ea   ),
         .cfg   ( ecfg   )
         );
 
   mnma #(.N(4*VCN), .M(VCN))
   LCBA (
         .r     ( r2l    ),
         .ra    ( r2la   ),
         .cfg   ( lcfg   )
         );
`else // !`ifndef ENABLE_MRMA
   mrma #(.N(2*VCN), .M(VCN))
   SCBA (
         .ca    ( r2sa   ),
         .ra    ( SOPblk ),
         .cfg   ( scfg   ),
         .c     ( r2s    ),
         .r     ( SOPrdy ),
         .rst_n ( rst_n  )
         );
 
   mrma #(.N(4*VCN), .M(VCN))
   WCBA (
         .ca    ( r2wa   ),
         .ra    ( WOPblk ),
         .cfg   ( wcfg   ),
         .c     ( r2w    ),
         .r     ( WOPrdy ),
         .rst_n ( rst_n  )
         );
 
   mrma #(.N(2*VCN), .M(VCN))
   NCBA (
         .ca    ( r2na   ),
         .ra    ( NOPblk ),
         .cfg   ( ncfg   ),
         .c     ( r2n    ),
         .r     ( NOPrdy ),
         .rst_n ( rst_n  )
         );
 
   mrma #(.N(4*VCN), .M(VCN))
   ECBA (
         .ca    ( r2ea   ),
         .ra    ( EOPblk ),
         .cfg   ( ecfg   ),
         .c     ( r2e    ),
         .r     ( EOPrdy ),
         .rst_n ( rst_n  )
         );
 
   mrma #(.N(4*VCN), .M(VCN))
   LCBA (
         .ca    ( r2la   ),
         .ra    ( LOPblk ),
         .cfg   ( lcfg   ),
         .c     ( r2l    ),
         .r     ( LOPrdy ),
         .rst_n ( rst_n  )
         );
 
   generate
      for(i=0; i<VCN; i++) begin: OPC
         delay DLY ( .q(OPrst_n[i+1]), .a(OPrst_n[i])); // dont touch
         assign SOPrdy[i] = (~SOPblk[i])&OPrst_n[i+1];
         assign WOPrdy[i] = (~WOPblk[i])&OPrst_n[i+1];
         assign NOPrdy[i] = (~NOPblk[i])&OPrst_n[i+1];
         assign EOPrdy[i] = (~EOPblk[i])&OPrst_n[i+1];
         assign LOPrdy[i] = (~LOPblk[i])&OPrst_n[i+1];
      end
   endgenerate
 
   assign OPrst_n[0] = rst_n;
 
`endif // !`ifndef ENABLE_MRMA
 
endmodule // sdm_sch

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[/] [async_sdm_noc/] [trunk/] [sdm/] [src/] [sdm_sch.v] - Blame information for rev 28

Line No.	Rev	Author	Line
1	19	wsong0210	`/*`
2			`Asynchronous SDM NoC`
3			`(C)2011 Wei Song`
4			`Advanced Processor Technologies Group`
5			`Computer Science, the Univ. of Manchester, UK`
6
7			`Authors:`
8			`Wei Song wsong83@gmail.com`
9
10			`License: LGPL 3.0 or later`
11
12			`Crossbar based SDM switch allocator`
13			`* SystemVerilog is used *`
14
15			`References`
16			`For the detail structure, please refer to Section 6.3.1 of the thesis:`
17			`Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011.`
18
19			`History:`
20			`28/09/2009 Initial version. <wsong83@gmail.com>`
21	28	wsong0210	`27/05/2011 Clean up for opensource. <wsong83@gmail.com>`
22	19	wsong0210
23			`*/`
24
25			`// the router structure definitions`
26			`include "define.v"
27
28			`module sdm_sch (/AUTOARG/`
29			`// Outputs`
30			`sack, wack, nack, eack, lack, scfg, ncfg, wcfg, ecfg, lcfg,`
31			`// Inputs`
32	28	wsong0210	`sreq, nreq, lreq, wreq, ereq, rst_n`
33	19	wsong0210	`);`
34
35			`parameter VCN = 2; // the number of virtual circuits per port`
36
37			`// income requests`
38			`input [VCN-1:0][3:0] sreq, nreq, lreq;`
39			`input [VCN-1:0][1:0] wreq, ereq;`
40
41			`// ack to input buffers`
42			`output [VCN-1:0] sack, wack, nack, eack, lack;`
43
44			`// configuration to the crossbar`
45			`output [VCN-1:0][1:0][VCN-1:0] scfg, ncfg;`
46			`output [VCN-1:0][3:0][VCN-1:0] wcfg, ecfg, lcfg;`
47
48			`input rst_n; // active low global reset`
49
50			`// requests to arbiters`
51			`ifndef ENABLE_MRMA
52			`wire [1:0][VCN-1:0][VCN-1:0] r2s, r2n; // shuffle the incoming request signals`
53			`wire [3:0][VCN-1:0][VCN-1:0] r2w, r2e, r2l;`
54			`else
55			`wire [1:0][VCN-1:0] r2s, r2n; // shuffle the incoming request signals`
56			`wire [3:0][VCN-1:0] r2w, r2e, r2l;`
57			`endif
58
59			`// ack from arbiters`
60			`wire [VCN-1:0][3:0] a2s, a2n, a2l;`
61			`wire [VCN-1:0][1:0] a2w, a2e;`
62
63			`// ack of the arbiters`
64			`wire [1:0][VCN-1:0] r2sa, r2na;`
65			`wire [3:0][VCN-1:0] r2wa, r2ea, r2la;`
66
67			`ifdef ENABLE_MRMA
68			`wire [VCN:0] OPrst_n; // the buffered resets to avoid metastability`
69			`wire [VCN-1:0] SOPrdy, SOPblk; // OP ready and blocked status`
70			`wire [VCN-1:0] WOPrdy, WOPblk; // OP ready and blocked status`
71			`wire [VCN-1:0] NOPrdy, NOPblk; // OP ready and blocked status`
72			`wire [VCN-1:0] EOPrdy, EOPblk; // OP ready and blocked status`
73			`wire [VCN-1:0] LOPrdy, LOPblk; // OP ready and blocked status`
74			`endif
75
76			`genvar i,j;`
77
78			`// wire shuffle`
79			`generate for(i=0; i<VCN; i++) begin: SHUF`
80			`ifndef ENABLE_MRMA
81			`for(j=0; j<VCN; j++) begin: CO`
82			`assign r2s[0][i][j] = nreq[i][0];`
83			`assign r2s[1][i][j] = lreq[i][0];`
84			`assign r2w[0][i][j] = sreq[i][0];`
85			`assign r2w[1][i][j] = nreq[i][1];`
86			`assign r2w[2][i][j] = ereq[i][0];`
87			`assign r2w[3][i][j] = lreq[i][1];`
88			`assign r2n[0][i][j] = sreq[i][1];`
89			`assign r2n[1][i][j] = lreq[i][2];`
90			`assign r2e[0][i][j] = sreq[i][2];`
91			`assign r2e[1][i][j] = wreq[i][0];`
92			`assign r2e[2][i][j] = nreq[i][2];`
93			`assign r2e[3][i][j] = lreq[i][3];`
94			`assign r2l[0][i][j] = sreq[i][3];`
95			`assign r2l[1][i][j] = wreq[i][1];`
96			`assign r2l[2][i][j] = nreq[i][3];`
97			`assign r2l[3][i][j] = ereq[i][1];`
98			`end // block: CO`
99			`else // !`ifndef ENABLE_MRMA
100			`assign r2s[0][i] = nreq[i][0];`
101			`assign r2s[1][i] = lreq[i][0];`
102			`assign r2w[0][i] = sreq[i][0];`
103			`assign r2w[1][i] = nreq[i][1];`
104			`assign r2w[2][i] = ereq[i][0];`
105			`assign r2w[3][i] = lreq[i][1];`
106			`assign r2n[0][i] = sreq[i][1];`
107			`assign r2n[1][i] = lreq[i][2];`
108			`assign r2e[0][i] = sreq[i][2];`
109			`assign r2e[1][i] = wreq[i][0];`
110			`assign r2e[2][i] = nreq[i][2];`
111			`assign r2e[3][i] = lreq[i][3];`
112			`assign r2l[0][i] = sreq[i][3];`
113			`assign r2l[1][i] = wreq[i][1];`
114			`assign r2l[2][i] = nreq[i][3];`
115			`assign r2l[3][i] = ereq[i][1];`
116			`endif // !`ifndef ENABLE_MRMA
117			`assign a2s[i][0] = r2wa[0][i];`
118			`assign a2s[i][1] = r2na[0][i];`
119			`assign a2s[i][2] = r2ea[0][i];`
120			`assign a2s[i][3] = r2la[0][i];`
121			`assign a2w[i][0] = r2ea[1][i];`
122			`assign a2w[i][1] = r2la[1][i];`
123			`assign a2n[i][0] = r2sa[0][i];`
124			`assign a2n[i][1] = r2wa[1][i];`
125			`assign a2n[i][2] = r2ea[2][i];`
126			`assign a2n[i][3] = r2la[2][i];`
127			`assign a2e[i][0] = r2wa[2][i];`
128			`assign a2e[i][1] = r2la[3][i];`
129			`assign a2l[i][0] = r2sa[1][i];`
130			`assign a2l[i][1] = r2wa[3][i];`
131			`assign a2l[i][2] = r2na[1][i];`
132			`assign a2l[i][3] = r2ea[3][i];`
133			`assign sack[i] = \|a2s[i];`
134			`assign wack[i] = \|a2w[i];`
135			`assign nack[i] = \|a2n[i];`
136			`assign eack[i] = \|a2e[i];`
137			`assign lack[i] = \|a2l[i];`
138
139			`end // block: SHUF`
140			`endgenerate`
141
142			`// output port arbiter/allocators`
143			`ifndef ENABLE_MRMA
144			`mnma #(.N(2*VCN), .M(VCN))`
145			`SCBA (`
146			`.r ( r2s ),`
147			`.ra ( r2sa ),`
148			`.cfg ( scfg )`
149			`);`
150
151			`mnma #(.N(4*VCN), .M(VCN))`
152			`WCBA (`
153			`.r ( r2w ),`
154			`.ra ( r2wa ),`
155			`.cfg ( wcfg )`
156			`);`
157
158			`mnma #(.N(2*VCN), .M(VCN))`
159			`NCBA (`
160			`.r ( r2n ),`
161			`.ra ( r2na ),`
162			`.cfg ( ncfg )`
163			`);`
164
165			`mnma #(.N(4*VCN), .M(VCN))`
166			`ECBA (`
167			`.r ( r2e ),`
168			`.ra ( r2ea ),`
169			`.cfg ( ecfg )`
170			`);`
171
172			`mnma #(.N(4*VCN), .M(VCN))`
173			`LCBA (`
174			`.r ( r2l ),`
175			`.ra ( r2la ),`
176			`.cfg ( lcfg )`
177			`);`
178			`else // !`ifndef ENABLE_MRMA
179			`mrma #(.N(2*VCN), .M(VCN))`
180			`SCBA (`
181			`.ca ( r2sa ),`
182			`.ra ( SOPblk ),`
183			`.cfg ( scfg ),`
184			`.c ( r2s ),`
185			`.r ( SOPrdy ),`
186			`.rst_n ( rst_n )`
187			`);`
188
189			`mrma #(.N(4*VCN), .M(VCN))`
190			`WCBA (`
191			`.ca ( r2wa ),`
192			`.ra ( WOPblk ),`
193			`.cfg ( wcfg ),`
194			`.c ( r2w ),`
195			`.r ( WOPrdy ),`
196			`.rst_n ( rst_n )`
197			`);`
198
199			`mrma #(.N(2*VCN), .M(VCN))`
200			`NCBA (`
201			`.ca ( r2na ),`
202			`.ra ( NOPblk ),`
203			`.cfg ( ncfg ),`
204			`.c ( r2n ),`
205			`.r ( NOPrdy ),`
206			`.rst_n ( rst_n )`
207			`);`
208
209			`mrma #(.N(4*VCN), .M(VCN))`
210			`ECBA (`
211			`.ca ( r2ea ),`
212			`.ra ( EOPblk ),`
213			`.cfg ( ecfg ),`
214			`.c ( r2e ),`
215			`.r ( EOPrdy ),`
216			`.rst_n ( rst_n )`
217			`);`
218
219			`mrma #(.N(4*VCN), .M(VCN))`
220			`LCBA (`
221			`.ca ( r2la ),`
222			`.ra ( LOPblk ),`
223			`.cfg ( lcfg ),`
224			`.c ( r2l ),`
225			`.r ( LOPrdy ),`
226			`.rst_n ( rst_n )`
227			`);`
228
229			`generate`
230			`for(i=0; i<VCN; i++) begin: OPC`
231			`delay DLY ( .q(OPrst_n[i+1]), .a(OPrst_n[i])); // dont touch`
232	28	wsong0210	`assign SOPrdy[i] = (~SOPblk[i])&OPrst_n[i+1];`
233			`assign WOPrdy[i] = (~WOPblk[i])&OPrst_n[i+1];`
234			`assign NOPrdy[i] = (~NOPblk[i])&OPrst_n[i+1];`
235			`assign EOPrdy[i] = (~EOPblk[i])&OPrst_n[i+1];`
236			`assign LOPrdy[i] = (~LOPblk[i])&OPrst_n[i+1];`
237	19	wsong0210	`end`
238			`endgenerate`
239	28	wsong0210
240			`assign OPrst_n[0] = rst_n;`
241	19	wsong0210
242			`endif // !`ifndef ENABLE_MRMA
243
244			`endmodule // sdm_sch`