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wsong0210 |
# Asynchronous SDM NoC
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# (C)2011 Wei Song
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# Advanced Processor Technologies Group
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# Computer Science, the Univ. of Manchester, UK
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#
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# Authors:
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# Wei Song wsong83@gmail.com
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#
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# License: LGPL 3.0 or later
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#
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# Constraints for wormhole/SDM routers
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#
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# History:
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# 26/05/2011 Initial version. <wsong83@gmail.com>
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# loading the baic cell constraints
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source ../../common/script/cell_constraint.tcl
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# ensure the basic blocks are not ungrouped for better debugging capability
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set_ungroup [get_references -hierarchical inp_buf*] false
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set_ungroup [get_references -hierarchical outp_buf*] false
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set_ungroup CB false
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set_ungroup ALLOC false
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######### break the timing loops in the design ##############
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# route decision address bus
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set_disable_timing [get_cells -hierarchical Px_* ] -from A -to Z
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set_disable_timing [get_cells -hierarchical Px_* ] -from B -to Z
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set_disable_timing [get_cells -hierarchical Py_* ] -from A -to Z
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set_disable_timing [get_cells -hierarchical Py_* ] -from B -to Z
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# input buffer control input
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foreach_in_collection celln [get_references -hierarchical inp_buf_*] {
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set_disable_timing [get_object_name $celln]/C_RTD0/U2 -from B -to Z
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set_disable_timing [get_object_name $celln]/C_RTD1/U2 -from B -to Z
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set_disable_timing [get_object_name $celln]/C_RT_XEQ/U2 -from B -to Z
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}
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# the delay cell in the lookahead pipeline
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# It is not a problem to get errors here if ENABLE_LOOKAHEAD is not defined.
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foreach_in_collection celln [get_references -hierarchical outp_buf_*] {
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set_disable_timing [get_object_name $celln]/DLY/U -from A -to Z
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}
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# set some timing path ending points
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set DPD []
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set DPA []
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foreach_in_collection celln [get_references -hierarchical dc2_*] {
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append_to_collection DPD [ get_pins [get_object_name $celln]/U1/B]
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append_to_collection DPD [ get_pins [get_object_name $celln]/U2/A]
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append_to_collection DPA [ get_pins [get_object_name $celln]/U1/A]
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append_to_collection DPA [ get_pins [get_object_name $celln]/U3/A]
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}
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set IODI [filter [get_ports *i*] "@port_direction == in"]
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set IODO [filter [get_ports *o*] "@port_direction == out"]
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set IOAI [filter [get_ports *i*] "@port_direction == out"]
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set IOAO [filter [get_ports *o*] "@port_direction == in"]
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# set the timing constraints for data paths and ack paths
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# For better speed performance, please tune these delay and factors according different cell libraries
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set DATA_dly 5
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set ACK_dly 8
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set_max_delay [expr ${DATA_dly} * 1.00] -from ${DPA} -to ${DPD} -group G_DATA
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set_max_delay [expr ${ACK_dly} * 1.00] -from ${DPA} -to ${DPA} -group G_ACK
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set_max_delay [expr ${DATA_dly} * 0.30] -from ${IODI} -to ${DPD} -group G_DATA
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set_max_delay [expr ${ACK_dly} * 0.75] -from ${DPA} -to ${IOAI} -group G_ACK
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set_max_delay [expr ${DATA_dly} * 0.70] -from ${DPA} -to ${IODO} -group G_DATA
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set_max_delay [expr ${ACK_dly} * 0.25] -from ${IOAO} -to ${DPA} -group G_ACK
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group_path -weight 1.5 -critical_range 40 -name G_DATA
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group_path -weight 1.5 -critical_range 40 -name G_ACK
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set_critical_range 20 ${current_design}
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set_max_leakage_power 0.0
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set_max_dynamic_power 0.0
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set_max_area 0
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# timing path disabled by user constraints
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suppress_message TIM-175
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