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1 32 wsong0210
/*
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 Asynchronous SDM NoC
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 (C)2011 Wei Song
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 Advanced Processor Technologies Group
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 Computer Science, the Univ. of Manchester, UK
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 Authors:
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 Wei Song     wsong83@gmail.com
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 License: LGPL 3.0 or later
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 The SystemC module of network node including the processing element and the network interface.
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 Currently the transmission FIFO is 500 frame deep.
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 History:
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 27/02/2011  Initial version. <wsong83@gmail.com>
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 30/05/2011  Clean up for opensource. <wsong83@gmail.com>
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*/
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`include "define.v"
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module NetNode (
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                dia, do4, doa, di4,
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                do0, do1, do2, do3,
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                di0, di1, di2, di3,
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                rst_n)
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   //
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   // The foreign attribute string value must be a SystemC value.
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   //
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   (* integer foreign = "SystemC";
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    *);
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   //
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   // Verilog port names must match port names exactly as they appear in the
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   // sc_module class in SystemC; they must also match in order, mode, and type.
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   //
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   parameter DW = 32;
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   parameter VCN = 1;
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   parameter x = 2;
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   parameter y = 2;
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   parameter SCN = DW/2;
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`ifdef ENABLE_CHANNEL_SLICING
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   input [VCN*SCN-1:0] dia;
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   input [VCN*SCN-1:0] do4;
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   output [VCN*SCN-1:0] doa;
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   output [VCN*SCN-1:0] di4;
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`else
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   input [VCN-1:0] dia;
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   input [VCN-1:0] do4;
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   output [VCN-1:0] doa;
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   output [VCN-1:0] di4;
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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   input [VCN*SCN-1:0] do0;
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   input [VCN*SCN-1:0] do1;
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   input [VCN*SCN-1:0] do2;
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   input [VCN*SCN-1:0] do3;
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   output [VCN*SCN-1:0] di0;
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   output [VCN*SCN-1:0] di1;
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   output [VCN*SCN-1:0] di2;
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   output [VCN*SCN-1:0] di3;
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   input                rst_n;
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endmodule // NetNode
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