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wsong0210 |
/*
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Asynchronous SDM NoC
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(C)2011 Wei Song
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Advanced Processor Technologies Group
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Computer Science, the Univ. of Manchester, UK
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Authors:
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Wei Song wsong83@gmail.com
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License: LGPL 3.0 or later
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A network node including a router, a NI and a processing element.
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History:
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03/03/2011 Initial version. <wsong83@gmail.com>
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30/05/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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// the router structure definitions
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`include "define.v"
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module node_top(/*AUTOARG*/
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// Outputs
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so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
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eo1, eo2, eo3, sia, wia, nia, eia, so4, wo4, no4, eo4,
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// Inputs
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si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
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ei1, ei2, ei3, si4, wi4, ni4, ei4, soa, woa, noa, eoa, rst_n
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);
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parameter DW = 32;
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parameter VCN = 1;
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parameter x = 0;
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parameter y = 0;
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parameter SCN = DW/2;
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input [VCN*SCN-1:0] si0, si1, si2, si3;
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input [VCN*SCN-1:0] wi0, wi1, wi2, wi3;
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input [VCN*SCN-1:0] ni0, ni1, ni2, ni3;
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input [VCN*SCN-1:0] ei0, ei1, ei2, ei3;
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output [VCN*SCN-1:0] so0, so1, so2, so3;
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output [VCN*SCN-1:0] wo0, wo1, wo2, wo3;
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output [VCN*SCN-1:0] no0, no1, no2, no3;
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output [VCN*SCN-1:0] eo0, eo1, eo2, eo3;
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wire [VCN*SCN-1:0] li0, li1, li2, li3;
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wire [VCN*SCN-1:0] lo0, lo1, lo2, lo3;
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`ifdef ENABLE_CHANNEL_SLICING
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input [VCN*SCN-1:0] si4, wi4, ni4, ei4;
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output [VCN*SCN-1:0] sia, wia, nia, eia;
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output [VCN*SCN-1:0] so4, wo4, no4, eo4;
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input [VCN*SCN-1:0] soa, woa, noa, eoa;
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wire [VCN*SCN-1:0] li4, lia, lo4, loa;
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`else
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input [VCN-1:0] si4, wi4, ni4, ei4;
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output [VCN-1:0] sia, wia, nia, eia;
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output [VCN-1:0] so4, wo4, no4, eo4;
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input [VCN-1:0] soa, woa, noa, eoa;
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wire [VCN-1:0] li4, lia, lo4, loa;
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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input rst_n;
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// the network node
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NetNode #(.DW(DW), .VCN(VCN), .x(x), .y(y))
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Node (
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.dia ( lia ),
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.do4 ( lo4 ),
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.doa ( loa ),
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.di4 ( li4 ),
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.do0 ( lo0 ),
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.do1 ( lo1 ),
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.do2 ( lo2 ),
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.do3 ( lo3 ),
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.di0 ( li0 ),
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.di1 ( li1 ),
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.di2 ( li2 ),
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.di3 ( li3 ),
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.rst_n ( rst_n )
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);
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// router wrapper
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router_hdl #(.DW(DW), .VCN(VCN))
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RTN (
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.so0(so0), .so1(so1), .so2(so2), .so3(so3), .so4(so4), .soa(soa),
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.wo0(wo0), .wo1(wo1), .wo2(wo2), .wo3(wo3), .wo4(wo4), .woa(woa),
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.no0(no0), .no1(no1), .no2(no2), .no3(no3), .no4(no4), .noa(noa),
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.eo0(eo0), .eo1(eo1), .eo2(eo2), .eo3(eo3), .eo4(eo4), .eoa(eoa),
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.lo0(lo0), .lo1(lo1), .lo2(lo2), .lo3(lo3), .lo4(lo4), .loa(loa),
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.si0(si0), .si1(si1), .si2(si2), .si3(si3), .si4(si4), .sia(sia),
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.wi0(wi0), .wi1(wi1), .wi2(wi2), .wi3(wi3), .wi4(wi4), .wia(wia),
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.ni0(ni0), .ni1(ni1), .ni2(ni2), .ni3(ni3), .ni4(ni4), .nia(nia),
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.ei0(ei0), .ei1(ei1), .ei2(ei2), .ei3(ei3), .ei4(ei4), .eia(eia),
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.li0(li0), .li1(li1), .li2(li2), .li3(li3), .li4(li4), .lia(lia),
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.addrx (b2chain(x)),
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.addry (b2chain(y)),
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.rst_n (rst_n)
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);
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// binary to 1-of-4 (Chain) converter
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function [7:0] b2chain;
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input [3:0] data;
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begin
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b2chain[0] = (data[1:0] == 2'b00);
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b2chain[1] = (data[1:0] == 2'b01);
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b2chain[2] = (data[1:0] == 2'b10);
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b2chain[3] = (data[1:0] == 2'b11);
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b2chain[4] = (data[3:2] == 2'b00);
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b2chain[5] = (data[3:2] == 2'b01);
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b2chain[6] = (data[3:2] == 2'b10);
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b2chain[7] = (data[3:2] == 2'b11);
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end
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endfunction
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endmodule // node_top
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