OpenCores
URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [trunk/] [vc/] [src/] [dcb_vc.v] - Blame information for rev 51

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 39 wsong0210
/*
2
 Asynchronous SDM NoC
3
 (C)2011 Wei Song
4
 Advanced Processor Technologies Group
5
 Computer Science, the Univ. of Manchester, UK
6
 
7
 Authors:
8
 Wei Song     wsong83@gmail.com
9
 
10
 License: LGPL 3.0 or later
11
 
12
 data crossbar for the VC router
13
 
14
 History:
15
 04/04/2010  Initial version. <wsong83@gmail.com>
16
 12/05/2010  Use MPxP crossbar. <wsong83@gmail.com>
17
 02/06/2011  Clean up for opensource. <wsong83@gmail.com>
18
 
19
*/
20
 
21
module dcb_vc (/*AUTOARG*/
22
   // Outputs
23
   dia, do0, do1, do2, do3, dot,
24
   // Inputs
25
   di0, di1, di2, di3, dit, srtg, nrtg, lrtg, wrtg, ertg, doa
26
   );
27
   parameter DW = 32;           // data width of a VC
28
   parameter FT = 3;            // wire count of the flit tyoe bus
29
   parameter VCN = 2;           // number of VC per direction
30
   parameter SCN = DW/2;
31
 
32
   input [4:0][VCN-1:0][SCN-1:0]   di0, di1, di2, di3; // data input
33
   input [4:0][VCN-1:0][FT-1:0]    dit;                   // flit type input
34
   output [4:0][VCN-1:0]     dia;                // input ack
35
   input [VCN-1:0][3:0]      srtg, nrtg, lrtg;   // routing guide
36
   input [VCN-1:0][1:0]      wrtg, ertg;
37
 
38
   output [4:0][SCN-1:0]     do0, do1, do2, do3; // data output
39
   output [4:0][FT-1:0]      dot;                // flit type output
40
   input [4:0]                      doa;                // output ack
41
 
42
   // internal wires
43
   wire [VCN-1:0][3:0][SCN-1:0]    s0, s1, s2, s3;
44
   wire [VCN-1:0][3:0][FT-1:0]        sft;
45
   wire [VCN-1:0][3:0]               sa;
46
   wire [VCN-1:0][1:0][SCN-1:0]    w0, w1, w2, w3;
47
   wire [VCN-1:0][1:0][FT-1:0]        wft;
48
   wire [VCN-1:0][1:0]               wa;
49
   wire [VCN-1:0][3:0][SCN-1:0]    n0, n1, n2, n3;
50
   wire [VCN-1:0][3:0][FT-1:0]        nft;
51
   wire [VCN-1:0][3:0]               na;
52
   wire [VCN-1:0][1:0][SCN-1:0]    e0, e1, e2, e3;
53
   wire [VCN-1:0][1:0][FT-1:0]        eft;
54
   wire [VCN-1:0][1:0]               ea;
55
   wire [VCN-1:0][3:0][SCN-1:0]    l0, l1, l2, l3;
56
   wire [VCN-1:0][3:0][FT-1:0]        lft;
57
   wire [VCN-1:0][3:0]               la;
58
 
59
   wire [3:0][SCN-1:0][VCN-1:0]    ss0, ss1, ss2, ss3;
60
   wire [3:0][FT-1:0][VCN-1:0]        ssft;
61
   wire [1:0][SCN-1:0][VCN-1:0]    sw0, sw1, sw2, sw3;
62
   wire [1:0][FT-1:0][VCN-1:0]        swft;
63
   wire [3:0][SCN-1:0][VCN-1:0]    sn0, sn1, sn2, sn3;
64
   wire [3:0][FT-1:0][VCN-1:0]        snft;
65
   wire [1:0][SCN-1:0][VCN-1:0]    se0, se1, se2, se3;
66
   wire [1:0][FT-1:0][VCN-1:0]        seft;
67
   wire [3:0][SCN-1:0][VCN-1:0]    sl0, sl1, sl2, sl3;
68
   wire [3:0][FT-1:0][VCN-1:0]        slft;
69
 
70
   wire [3:0][SCN-1:0]               ms0, ms1, ms2, ms3;
71
   wire [3:0][FT-1:0]                msft;
72
   wire [1:0][SCN-1:0]               mw0, mw1, mw2, mw3;
73
   wire [1:0][FT-1:0]                mwft;
74
   wire [3:0][SCN-1:0]               mn0, mn1, mn2, mn3;
75
   wire [3:0][FT-1:0]                mnft;
76
   wire [1:0][SCN-1:0]               me0, me1, me2, me3;
77
   wire [1:0][FT-1:0]                meft;
78
   wire [3:0][SCN-1:0]               ml0, ml1, ml2, ml3;
79
   wire [3:0][FT-1:0]                mlft;
80
 
81
   genvar                 i,j,k;
82
 
83
   generate
84
      // demux using the routing guides
85
      for(i=0; i<VCN; i++) begin: IMX
86
         vcdmux #(.DW(DW), .VCN(4))
87
         SDMX(
88
               .dia  ( dia[0][i]    ),
89
               .do0  ( s0[i]        ),
90
               .do1  ( s1[i]        ),
91
               .do2  ( s2[i]        ),
92
               .do3  ( s3[i]        ),
93
               .dot  ( sft[i]       ),
94
               .di0  ( di0[0][i]    ),
95
               .di1  ( di1[0][i]    ),
96
               .di2  ( di2[0][i]    ),
97
               .di3  ( di3[0][i]    ),
98
               .dit  ( dit[0][i]    ),
99
               .divc ( srtg[i]      ),
100
               .doa  ( sa[i]        )
101
               );
102
 
103
         vcdmux #(.DW(DW), .VCN(2))
104
         WDMX(
105
               .dia  ( dia[1][i]    ),
106
               .do0  ( w0[i]        ),
107
               .do1  ( w1[i]        ),
108
               .do2  ( w2[i]        ),
109
               .do3  ( w3[i]        ),
110
               .dot  ( wft[i]       ),
111
               .di0  ( di0[1][i]    ),
112
               .di1  ( di1[1][i]    ),
113
               .di2  ( di2[1][i]    ),
114
               .di3  ( di3[1][i]    ),
115
               .dit  ( dit[1][i]    ),
116
               .divc ( wrtg[i]      ),
117
               .doa  ( wa[i]        )
118
               );
119
 
120
         vcdmux #(.DW(DW), .VCN(4))
121
         NDMX(
122
               .dia  ( dia[2][i]    ),
123
               .do0  ( n0[i]        ),
124
               .do1  ( n1[i]        ),
125
               .do2  ( n2[i]        ),
126
               .do3  ( n3[i]        ),
127
               .dot  ( nft[i]       ),
128
               .di0  ( di0[2][i]    ),
129
               .di1  ( di1[2][i]    ),
130
               .di2  ( di2[2][i]    ),
131
               .di3  ( di3[2][i]    ),
132
               .dit  ( dit[2][i]    ),
133
               .divc ( nrtg[i]      ),
134
               .doa  ( na[i]        )
135
               );
136
 
137
         vcdmux #(.DW(DW), .VCN(2))
138
         EDMX(
139
               .dia  ( dia[3][i]    ),
140
               .do0  ( e0[i]        ),
141
               .do1  ( e1[i]        ),
142
               .do2  ( e2[i]        ),
143
               .do3  ( e3[i]        ),
144
               .dot  ( eft[i]       ),
145
               .di0  ( di0[3][i]    ),
146
               .di1  ( di1[3][i]    ),
147
               .di2  ( di2[3][i]    ),
148
               .di3  ( di3[3][i]    ),
149
               .dit  ( dit[3][i]    ),
150
               .divc ( ertg[i]      ),
151
               .doa  ( ea[i]        )
152
               );
153
 
154
         vcdmux #(.DW(DW), .VCN(4))
155
         LDMX(
156
               .dia  ( dia[4][i]    ),
157
               .do0  ( l0[i]        ),
158
               .do1  ( l1[i]        ),
159
               .do2  ( l2[i]        ),
160
               .do3  ( l3[i]        ),
161
               .dot  ( lft[i]       ),
162
               .di0  ( di0[4][i]    ),
163
               .di1  ( di1[4][i]    ),
164
               .di2  ( di2[4][i]    ),
165
               .di3  ( di3[4][i]    ),
166
               .dit  ( dit[4][i]    ),
167
               .divc ( lrtg[i]      ),
168
               .doa  ( la[i]        )
169
               );
170
 
171
         // acknowledgement
172
         c2 SA0 (.a0(srtg[i][0]), .a1(doa[1]), .q(sa[i][0]));
173
         c2 SA1 (.a0(srtg[i][1]), .a1(doa[2]), .q(sa[i][1]));
174
         c2 SA2 (.a0(srtg[i][2]), .a1(doa[3]), .q(sa[i][2]));
175
         c2 SA3 (.a0(srtg[i][3]), .a1(doa[4]), .q(sa[i][3]));
176
         c2 WA0 (.a0(wrtg[i][0]), .a1(doa[3]), .q(wa[i][0]));
177
         c2 WA1 (.a0(wrtg[i][1]), .a1(doa[4]), .q(wa[i][1]));
178
         c2 NA0 (.a0(nrtg[i][0]), .a1(doa[0]), .q(na[i][0]));
179
         c2 NA1 (.a0(nrtg[i][1]), .a1(doa[1]), .q(na[i][1]));
180
         c2 NA2 (.a0(nrtg[i][2]), .a1(doa[3]), .q(na[i][2]));
181
         c2 NA3 (.a0(nrtg[i][3]), .a1(doa[4]), .q(na[i][3]));
182
         c2 EA0 (.a0(ertg[i][0]), .a1(doa[1]), .q(ea[i][0]));
183
         c2 EA1 (.a0(ertg[i][1]), .a1(doa[4]), .q(ea[i][1]));
184
         c2 LA0 (.a0(lrtg[i][0]), .a1(doa[0]), .q(la[i][0]));
185
         c2 LA1 (.a0(lrtg[i][1]), .a1(doa[1]), .q(la[i][1]));
186
         c2 LA2 (.a0(lrtg[i][2]), .a1(doa[2]), .q(la[i][2]));
187
         c2 LA3 (.a0(lrtg[i][3]), .a1(doa[3]), .q(la[i][3]));
188
 
189
      end // block: IMX
190
   endgenerate
191
 
192
   generate
193
      for(i=0; i<VCN; i++) begin: V
194
         for(j=0; j<4; j++) begin: D0
195
            for(k=0; k<SCN; k++) begin: D
196
               assign ss0[j][k][i] = s0[i][j][k];
197
               assign ss1[j][k][i] = s1[i][j][k];
198
               assign ss2[j][k][i] = s2[i][j][k];
199
               assign ss3[j][k][i] = s3[i][j][k];
200
               assign sn0[j][k][i] = n0[i][j][k];
201
               assign sn1[j][k][i] = n1[i][j][k];
202
               assign sn2[j][k][i] = n2[i][j][k];
203
               assign sn3[j][k][i] = n3[i][j][k];
204
               assign sl0[j][k][i] = l0[i][j][k];
205
               assign sl1[j][k][i] = l1[i][j][k];
206
               assign sl2[j][k][i] = l2[i][j][k];
207
               assign sl3[j][k][i] = l3[i][j][k];
208
            end // block: D
209
            for(k=0; k<FT; k++) begin: T
210
               assign ssft[j][k][i] = sft[i][j][k];
211
               assign snft[j][k][i] = nft[i][j][k];
212
               assign slft[j][k][i] = lft[i][j][k];
213
            end // block: T
214
         end // block: D0
215
 
216
         for(j=0; j<2; j++) begin: D1
217
            for(k=0; k<SCN; k++) begin: D
218
               assign sw0[j][k][i] = w0[i][j][k];
219
               assign sw1[j][k][i] = w1[i][j][k];
220
               assign sw2[j][k][i] = w2[i][j][k];
221
               assign sw3[j][k][i] = w3[i][j][k];
222
               assign se0[j][k][i] = e0[i][j][k];
223
               assign se1[j][k][i] = e1[i][j][k];
224
               assign se2[j][k][i] = e2[i][j][k];
225
               assign se3[j][k][i] = e3[i][j][k];
226
            end // block: D
227
            for(k=0; k<FT; k++) begin: T
228
               assign swft[j][k][i] = wft[i][j][k];
229
               assign seft[j][k][i] = eft[i][j][k];
230
            end // block: T
231
         end // block: D1
232
      end
233
 
234
      for(j=0; j<4; j++) begin: D2
235
         for(k=0; k<SCN; k++) begin: D
236
            assign ms0[j][k] = |ss0[j][k];
237
            assign ms1[j][k] = |ss1[j][k];
238
            assign ms2[j][k] = |ss2[j][k];
239
            assign ms3[j][k] = |ss3[j][k];
240
            assign mn0[j][k] = |sn0[j][k];
241
            assign mn1[j][k] = |sn1[j][k];
242
            assign mn2[j][k] = |sn2[j][k];
243
            assign mn3[j][k] = |sn3[j][k];
244
            assign ml0[j][k] = |sl0[j][k];
245
            assign ml1[j][k] = |sl1[j][k];
246
            assign ml2[j][k] = |sl2[j][k];
247
            assign ml3[j][k] = |sl3[j][k];
248
         end // block: D
249
         for(k=0; k<FT; k++) begin: T
250
            assign msft[j][k] = |ssft[j][k];
251
            assign mnft[j][k] = |snft[j][k];
252
            assign mlft[j][k] = |slft[j][k];
253
         end
254
      end // block: D2
255
 
256
      for(j=0; j<2; j++) begin: D4
257
         for(k=0; k<SCN; k++) begin: D
258
            assign mw0[j][k] = |sw0[j][k];
259
            assign mw1[j][k] = |sw1[j][k];
260
            assign mw2[j][k] = |sw2[j][k];
261
            assign mw3[j][k] = |sw3[j][k];
262
            assign me0[j][k] = |se0[j][k];
263
            assign me1[j][k] = |se1[j][k];
264
            assign me2[j][k] = |se2[j][k];
265
            assign me3[j][k] = |se3[j][k];
266
         end // block: D
267
         for(k=0; k<FT; k++) begin: T
268
            assign mwft[j][k] = |swft[j][k];
269
            assign meft[j][k] = |seft[j][k];
270
         end // block: T
271
      end // block: D4
272
   endgenerate
273
 
274
   // south output
275
   assign do0[0] = mn0[0]|ml0[0];
276
   assign do1[0] = mn1[0]|ml1[0];
277
   assign do2[0] = mn2[0]|ml2[0];
278
   assign do3[0] = mn3[0]|ml3[0];
279
   assign dot[0] = mnft[0]|mlft[0];
280
 
281
   // west output
282
   assign do0[1] = ms0[0]|mn0[1]|me0[0]|ml0[1];
283
   assign do1[1] = ms1[0]|mn1[1]|me1[0]|ml1[1];
284
   assign do2[1] = ms2[0]|mn2[1]|me2[0]|ml2[1];
285
   assign do3[1] = ms3[0]|mn3[1]|me3[0]|ml3[1];
286
   assign dot[1] = msft[0]|mnft[1]|meft[0]|mlft[1];
287
 
288
   // south output
289
   assign do0[2] = ms0[1]|ml0[2];
290
   assign do1[2] = ms1[1]|ml1[2];
291
   assign do2[2] = ms2[1]|ml2[2];
292
   assign do3[2] = ms3[1]|ml3[2];
293
   assign dot[2] = msft[1]|mlft[2];
294
 
295
   // east output
296
   assign do0[3] = ms0[2]|mw0[0]|mn0[2]|ml0[3];
297
   assign do1[3] = ms1[2]|mw1[0]|mn1[2]|ml1[3];
298
   assign do2[3] = ms2[2]|mw2[0]|mn2[2]|ml2[3];
299
   assign do3[3] = ms3[2]|mw3[0]|mn3[2]|ml3[3];
300
   assign dot[3] = msft[2]|mwft[0]|mnft[2]|mlft[3];
301
 
302
   // local output
303
   assign do0[4] = ms0[3]|mw0[1]|mn0[3]|me0[1];
304
   assign do1[4] = ms1[3]|mw1[1]|mn1[3]|me1[1];
305
   assign do2[4] = ms2[3]|mw2[1]|mn2[3]|me2[1];
306
   assign do3[4] = ms3[3]|mw3[1]|mn3[3]|me3[1];
307
   assign dot[4] = msft[3]|mwft[1]|mnft[3]|meft[1];
308
 
309
 
310
endmodule // dcb_vc

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.