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/*
 Asynchronous SDM NoC
 (C)2011 Wei Song
 Advanced Processor Technologies Group
 Computer Science, the Univ. of Manchester, UK
 
 Authors:
 Wei Song     wsong83@gmail.com
 
 License: LGPL 3.0 or later
 
 The input buffer for VC routers.
 
 History:
 01/04/2010  Initial version. <wsong83@gmail.com>
 12/05/2010  Use MPxP crossbars. <wsong83@gmail.com>
 17/04/2010  Remove unnecessary pipeline stages. <wsong83@gmail.com>
 02/06/2011  Clean up for opensource. <wsong83@gmail.com>
 09/06/2011  Remove the C-elements as muxes already have C-elements inside. <wsong83@gmail.com>
 
*/
 
module inpbuf (/*AUTOARG*/
   // Outputs
   dia, cor, do0, do1, do2, do3, dot, dortg, vcr, swr,
   // Inputs
   di0, di1, di2, di3, dit, divc, coa, doa, vcra, swrt, addrx, addry,
   rst_n
   );
 
   parameter DW = 32;           // data width
   parameter VCN = 2;           // VC number
   parameter DIR = 0;           // 0-4 south, west, north, east, local
   parameter SN = 2;            // maximal output port number
   parameter PD = 3;            // the depth of the input buffer pipeline
   parameter SCN = DW/2;        // number of 1-of-4 sub-channels
   parameter FT = 3;            // flit type, now 3, HOF, BOF, EOF
 
   // data IP
   input [SCN-1:0] di0, di1, di2, di3;
   input [FT-1:0]  dit;
   input [VCN-1:0] divc;
   output          dia;
 
   // credit flow-control
   output [VCN-1:0] cor;
   input [VCN-1:0]  coa;
 
   // data to crossbar
   output [VCN-1:0][SCN-1:0] do0,do1,do2,do3;
   output [VCN-1:0][FT-1:0]  dot;
   output [VCN-1:0][SN-1:0]  dortg;
   input  [VCN-1:0]          doa;
 
   // request to VC allocator
   output [VCN-1:0][SN-1:0] vcr;
   input [VCN-1:0]           vcra;
 
   // output to SW allocator
   output [VCN-1:0][1:0]    swr;
 
   // routing guide for SW DEMUX
   input [VCN-1:0][SN-1:0]  swrt;
 
   // local addresses
   input [7:0]               addrx, addry;
 
   input                    rst_n;
 
   //-----------------------------                  
   // VC_MUX
   wire                     ivma, rua;
   wire [SCN-1:0]            di0m, di1m, di2m, di3m;
   wire [FT-1:0]             ditm;
   wire [VCN-1:0]            divcm;
   wire [VCN-1:0]            muxa;
 
   // VC_BUF
   wire [2*PD:0][VCN-1:0][SCN-1:0] vcd0, vcd1, vcd2, vcd3; // VC data
   wire [2*PD:0][VCN-1:0][FT-1:0]  vcdt;              // VC flit type
   wire [2*PD:0][VCN-1:0][SCN-1:0] vcdad, vcdadn;          // VC ack
   wire [2*PD:0][VCN-1:0]            vcdat, vcdatn;          // VC data ack and type ack
   wire [1:0][VCN-1:0]               vcda;                   // the comman ack               
 
   // control path
   wire [2*PD:2*PD-2][VCN-1:0][1:0] vcft;            // flit type on control path
   wire [2*PD:2*PD-2][VCN-1:0]      vcfta, vcftan;          // flit type ack, on control path
   wire [VCN-1:0]                   vcdam;                  // need an extra ack internal signal
   wire [VCN-1:0][SN-1:0]            rtg;                    // routing direction guide
   wire [VCN-1:0]                   doan;
 
   // last stage of input buffer
   wire [VCN-1:0]                   vcor;
   wire [VCN-1:0]                   vcog;
   wire [VCN-1:0]                   swa;
 
   genvar                          gbd, gvc, gsub, i;
 
   //---------------------------------------------
   // the input VCDMUX
   vcdmux #(.VCN(VCN), .DW(DW))
   IVM (
         .dia   ( ivma     ),
         .do0   ( vcd0[0]  ),
         .do1   ( vcd1[0]  ),
         .do2   ( vcd2[0]  ),
         .do3   ( vcd3[0]  ),
         .dot   ( vcdt[0]  ),
         .di0   ( di0m     ),
         .di1   ( di1m     ),
         .di2   ( di2m     ),
         .di3   ( di3m     ),
         .dit   ( ditm     ),
         .divc  ( divcm    ),
         .doa   ( muxa     )
         );
 
   //c2 IVMA (.a0(ivma), .a1(rua), .q(dia)); divc is not checked
   ctree #(.DW(2)) ACKT(.ci({ivma, rua}), .co(dia));
 
   assign di0m = rst_n ? di0 : 0;
   assign di1m = rst_n ? di1 : 0;
   assign di2m = rst_n ? di2 : 0;
   assign di3m = rst_n ? di3 : 0;
   assign ditm = rst_n ? dit : 0;
   assign divcm = rst_n ? divc : 0;
 
   //---------------------------------------------
   // the VC buffers
   generate
      for(gbd=0; gbd<PD*2-2; gbd++) begin:BFN
         for(gvc=0; gvc<VCN; gvc++) begin:V
            for(gsub=0; gsub<SCN; gsub++) begin:SC
               pipe4 #(.DW(2))
               DP (
                   .ia ( vcdad[gbd][gvc][gsub]  ),
                   .o0 ( vcd0[gbd+1][gvc][gsub] ),
                   .o1 ( vcd1[gbd+1][gvc][gsub] ),
                   .o2 ( vcd2[gbd+1][gvc][gsub] ),
                   .o3 ( vcd3[gbd+1][gvc][gsub] ),
                   .i0 ( vcd0[gbd][gvc][gsub]   ),
                   .i1 ( vcd1[gbd][gvc][gsub]   ),
                   .i2 ( vcd2[gbd][gvc][gsub]   ),
                   .i3 ( vcd3[gbd][gvc][gsub]   ),
                   .oa ( vcdadn[gbd+1][gvc][gsub] )
                   );
               assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rst_n;
            end // block: SC
 
            pipen #(.DW(FT))
            TP (
                .d_in    ( vcdt[gbd][gvc]     ),
                .d_in_a  ( vcdat[gbd][gvc]    ),
                .d_out   ( vcdt[gbd+1][gvc]   ),
                .d_out_a ( vcdatn[gbd+1][gvc]  )
                );
            assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rst_n;
 
         end // block: V
      end // block: BFN
 
      for(gvc=0; gvc<VCN; gvc++) begin:BFNV
         if(PD>1) begin:ACKG
            ctree #(.DW(SCN+1)) ACKT(.ci({vcdat[0],vcdad[0]}), .co(muxa[gvc]));
            assign vcdad[PD*2-2][gvc] = {SCN{vcda[0][gvc]}};
            assign vcdat[PD*2-2] = vcda[0][gvc];
         end else begin
            assign muxa[gvc] = vcda[0][gvc];
         end
      end // block: V
 
   endgenerate
 
   // the last two stages of VC buffers, separate flit type and data
   generate
      for(gbd=PD*2-2; gbd<PD*2; gbd++) begin:BFL2
         for(gvc=0; gvc<VCN; gvc++) begin:V
            for(gsub=0; gsub<SCN; gsub++) begin:SC
               pipe4 #(.DW(2))
               DP (
                   .ia ( vcdad[gbd][gvc][gsub]    ),
                   .o0 ( vcd0[gbd+1][gvc][gsub]   ),
                   .o1 ( vcd1[gbd+1][gvc][gsub]   ),
                   .o2 ( vcd2[gbd+1][gvc][gsub]   ),
                   .o3 ( vcd3[gbd+1][gvc][gsub]   ),
                   .i0 ( vcd0[gbd][gvc][gsub]     ),
                   .i1 ( vcd1[gbd][gvc][gsub]     ),
                   .i2 ( vcd2[gbd][gvc][gsub]     ),
                   .i3 ( vcd3[gbd][gvc][gsub]     ),
                   .oa ( vcdadn[gbd+1][gvc][gsub] )
                   );
               assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rst_n;
            end // block: SC
 
            pipen #(.DW(FT))
            TP (
                .d_in    ( vcdt[gbd][gvc]     ),
                .d_in_a  ( vcdat[gbd][gvc]    ),
                .d_out   ( vcdt[gbd+1][gvc]   ),
                .d_out_a ( vcdatn[gbd+1][gvc]  )
                );
 
            assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rst_n;
 
            pipen #(.DW(2))
            CTP (
                .d_in    ( vcft[gbd][gvc]     ),
                .d_in_a  ( vcfta[gbd][gvc]    ),
                .d_out   ( vcft[gbd+1][gvc]   ),
                .d_out_a ( vcftan[gbd+1][gvc] )
                );
 
            assign vcftan[gbd+1][gvc] = (~vcfta[gbd+1][gvc])&rst_n;
         end // block: V
      end // block: BFL2
 
      for(gvc=0; gvc<VCN; gvc++) begin:BFL2V
         ctree #(.DW(SCN+2)) ACKT(.ci({vcfta[PD*2-2][gvc], vcdat[PD*2-2][gvc], vcdad[PD*2-2][gvc]}), .co(vcda[0][gvc]));
         assign vcdat[PD*2][gvc] = vcda[1][gvc];
         assign vcdad[PD*2][gvc] = {SCN{vcda[1][gvc]}};
         assign vcfta[PD*2][gvc] = swa[gvc];
         assign vcft[PD*2-2][gvc] = {vcdt[PD*2-2][gvc][FT-1], |vcdt[PD*2-2][gvc][FT-2:0]};
         assign swr[gvc] = vcft[PD*2][gvc];
      end
 
   endgenerate
 
 
   // the routing guide pipeline stage
   generate
      for(gvc=0; gvc<VCN; gvc++) begin:R
         pipen #(.DW(SN))
         RP (
             .d_in     ( swrt[gvc]          ),
             .d_in_a   ( swa[gvc]           ),
             .d_out    ( rtg[gvc]           ),
             .d_out_a  ( (~vcda[1][gvc])&rst_n   )
             );
      end
   endgenerate
 
   generate
      for(gvc=0; gvc<VCN; gvc++) begin:LPS
 
         // credit control
         dc2 FCP (.q(cor[gvc]), .d(|rtg[gvc]), .a((~coa[gvc])&rst_n));
 
         // output name conversation
         assign do0[gvc] = vcd0[PD*2][gvc];
         assign do1[gvc] = vcd1[PD*2][gvc];
         assign do2[gvc] = vcd2[PD*2][gvc];
         assign do3[gvc] = vcd3[PD*2][gvc];
 
         assign dot[gvc] = vcdt[PD*2][gvc];
         assign dortg[gvc] = rtg[gvc];
 
         c2 AC (.q(vcda[1][gvc]), .a0(cor[gvc]), .a1(doa[gvc]));
 
      end // block: LPS
   endgenerate
 
   // routing unit
   rtu #(.VCN(VCN), .DIR(DIR), .SN(SN), .PD(PD))
   RTC (
        .dia   ( rua       ),
        .dort  ( vcr       ),
        .rst_n ( rst_n     ),
        .di0   ( di0m[3:0] ),
        .di1   ( di1m[3:0] ),
        .di2   ( di2m[3:0] ),
        .di3   ( di3m[3:0] ),
        .dit   ( ditm      ),
        .divc  ( divcm     ),
        .addrx ( addrx     ),
        .addry ( addry     ),
        .doa   ( vcra      )
   );
 
endmodule // inpbuf
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	40	wsong0210	`/*`
2			`Asynchronous SDM NoC`
3			`(C)2011 Wei Song`
4			`Advanced Processor Technologies Group`
5			`Computer Science, the Univ. of Manchester, UK`
6
7			`Authors:`
8			`Wei Song wsong83@gmail.com`
9
10			`License: LGPL 3.0 or later`
11
12			`The input buffer for VC routers.`
13
14			`History:`
15			`01/04/2010 Initial version. <wsong83@gmail.com>`
16			`12/05/2010 Use MPxP crossbars. <wsong83@gmail.com>`
17			`17/04/2010 Remove unnecessary pipeline stages. <wsong83@gmail.com>`
18			`02/06/2011 Clean up for opensource. <wsong83@gmail.com>`
19	53	wsong0210	`09/06/2011 Remove the C-elements as muxes already have C-elements inside. <wsong83@gmail.com>`
20	40	wsong0210
21			`*/`
22
23			`module inpbuf (/AUTOARG/`
24			`// Outputs`
25			`dia, cor, do0, do1, do2, do3, dot, dortg, vcr, swr,`
26			`// Inputs`
27			`di0, di1, di2, di3, dit, divc, coa, doa, vcra, swrt, addrx, addry,`
28	45	wsong0210	`rst_n`
29	40	wsong0210	`);`
30
31			`parameter DW = 32; // data width`
32			`parameter VCN = 2; // VC number`
33			`parameter DIR = 0; // 0-4 south, west, north, east, local`
34			`parameter SN = 2; // maximal output port number`
35			`parameter PD = 3; // the depth of the input buffer pipeline`
36			`parameter SCN = DW/2; // number of 1-of-4 sub-channels`
37			`parameter FT = 3; // flit type, now 3, HOF, BOF, EOF`
38
39			`// data IP`
40			`input [SCN-1:0] di0, di1, di2, di3;`
41			`input [FT-1:0] dit;`
42			`input [VCN-1:0] divc;`
43			`output dia;`
44
45			`// credit flow-control`
46			`output [VCN-1:0] cor;`
47			`input [VCN-1:0] coa;`
48
49			`// data to crossbar`
50			`output [VCN-1:0][SCN-1:0] do0,do1,do2,do3;`
51			`output [VCN-1:0][FT-1:0] dot;`
52			`output [VCN-1:0][SN-1:0] dortg;`
53			`input [VCN-1:0] doa;`
54
55			`// request to VC allocator`
56			`output [VCN-1:0][SN-1:0] vcr;`
57			`input [VCN-1:0] vcra;`
58
59			`// output to SW allocator`
60			`output [VCN-1:0][1:0] swr;`
61
62			`// routing guide for SW DEMUX`
63			`input [VCN-1:0][SN-1:0] swrt;`
64
65			`// local addresses`
66			`input [7:0] addrx, addry;`
67
68	45	wsong0210	`input rst_n;`
69	40	wsong0210
70			`//-----------------------------`
71			`// VC_MUX`
72			`wire ivma, rua;`
73			`wire [SCN-1:0] di0m, di1m, di2m, di3m;`
74			`wire [FT-1:0] ditm;`
75			`wire [VCN-1:0] divcm;`
76			`wire [VCN-1:0] muxa;`
77
78			`// VC_BUF`
79			`wire [2*PD:0][VCN-1:0][SCN-1:0] vcd0, vcd1, vcd2, vcd3; // VC data`
80			`wire [2*PD:0][VCN-1:0][FT-1:0] vcdt; // VC flit type`
81			`wire [2*PD:0][VCN-1:0][SCN-1:0] vcdad, vcdadn; // VC ack`
82			`wire [2*PD:0][VCN-1:0] vcdat, vcdatn; // VC data ack and type ack`
83			`wire [1:0][VCN-1:0] vcda; // the comman ack`
84
85			`// control path`
86			`wire [2PD:2PD-2][VCN-1:0][1:0] vcft; // flit type on control path`
87			`wire [2PD:2PD-2][VCN-1:0] vcfta, vcftan; // flit type ack, on control path`
88			`wire [VCN-1:0] vcdam; // need an extra ack internal signal`
89			`wire [VCN-1:0][SN-1:0] rtg; // routing direction guide`
90			`wire [VCN-1:0] doan;`
91
92			`// last stage of input buffer`
93			`wire [VCN-1:0] vcor;`
94			`wire [VCN-1:0] vcog;`
95			`wire [VCN-1:0] swa;`
96
97			`genvar gbd, gvc, gsub, i;`
98
99			`//---------------------------------------------`
100			`// the input VCDMUX`
101			`vcdmux #(.VCN(VCN), .DW(DW))`
102			`IVM (`
103			`.dia ( ivma ),`
104			`.do0 ( vcd0[0] ),`
105			`.do1 ( vcd1[0] ),`
106			`.do2 ( vcd2[0] ),`
107			`.do3 ( vcd3[0] ),`
108			`.dot ( vcdt[0] ),`
109			`.di0 ( di0m ),`
110			`.di1 ( di1m ),`
111			`.di2 ( di2m ),`
112			`.di3 ( di3m ),`
113			`.dit ( ditm ),`
114			`.divc ( divcm ),`
115			`.doa ( muxa )`
116			`);`
117
118			`//c2 IVMA (.a0(ivma), .a1(rua), .q(dia)); divc is not checked`
119	53	wsong0210	`ctree #(.DW(2)) ACKT(.ci({ivma, rua}), .co(dia));`
120	40	wsong0210
121	45	wsong0210	`assign di0m = rst_n ? di0 : 0;`
122			`assign di1m = rst_n ? di1 : 0;`
123			`assign di2m = rst_n ? di2 : 0;`
124			`assign di3m = rst_n ? di3 : 0;`
125			`assign ditm = rst_n ? dit : 0;`
126			`assign divcm = rst_n ? divc : 0;`
127	40	wsong0210
128			`//---------------------------------------------`
129			`// the VC buffers`
130			`generate`
131			`for(gbd=0; gbd<PD*2-2; gbd++) begin:BFN`
132			`for(gvc=0; gvc<VCN; gvc++) begin:V`
133			`for(gsub=0; gsub<SCN; gsub++) begin:SC`
134			`pipe4 #(.DW(2))`
135			`DP (`
136	42	wsong0210	`.ia ( vcdad[gbd][gvc][gsub] ),`
137			`.o0 ( vcd0[gbd+1][gvc][gsub] ),`
138			`.o1 ( vcd1[gbd+1][gvc][gsub] ),`
139			`.o2 ( vcd2[gbd+1][gvc][gsub] ),`
140			`.o3 ( vcd3[gbd+1][gvc][gsub] ),`
141			`.i0 ( vcd0[gbd][gvc][gsub] ),`
142			`.i1 ( vcd1[gbd][gvc][gsub] ),`
143			`.i2 ( vcd2[gbd][gvc][gsub] ),`
144			`.i3 ( vcd3[gbd][gvc][gsub] ),`
145			`.oa ( vcdadn[gbd+1][gvc][gsub] )`
146	40	wsong0210	`);`
147	45	wsong0210	`assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rst_n;`
148	40	wsong0210	`end // block: SC`
149
150			`pipen #(.DW(FT))`
151			`TP (`
152			`.d_in ( vcdt[gbd][gvc] ),`
153			`.d_in_a ( vcdat[gbd][gvc] ),`
154			`.d_out ( vcdt[gbd+1][gvc] ),`
155			`.d_out_a ( vcdatn[gbd+1][gvc] )`
156			`);`
157	45	wsong0210	`assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rst_n;`
158	40	wsong0210
159			`end // block: V`
160			`end // block: BFN`
161
162			`for(gvc=0; gvc<VCN; gvc++) begin:BFNV`
163			`if(PD>1) begin:ACKG`
164			`ctree #(.DW(SCN+1)) ACKT(.ci({vcdat[0],vcdad[0]}), .co(muxa[gvc]));`
165			`assign vcdad[PD*2-2][gvc] = {SCN{vcda[0][gvc]}};`
166			`assign vcdat[PD*2-2] = vcda[0][gvc];`
167			`end else begin`
168			`assign muxa[gvc] = vcda[0][gvc];`
169			`end`
170			`end // block: V`
171
172			`endgenerate`
173
174			`// the last two stages of VC buffers, separate flit type and data`
175			`generate`
176			`for(gbd=PD2-2; gbd<PD2; gbd++) begin:BFL2`
177			`for(gvc=0; gvc<VCN; gvc++) begin:V`
178			`for(gsub=0; gsub<SCN; gsub++) begin:SC`
179			`pipe4 #(.DW(2))`
180			`DP (`
181	42	wsong0210	`.ia ( vcdad[gbd][gvc][gsub] ),`
182			`.o0 ( vcd0[gbd+1][gvc][gsub] ),`
183			`.o1 ( vcd1[gbd+1][gvc][gsub] ),`
184			`.o2 ( vcd2[gbd+1][gvc][gsub] ),`
185			`.o3 ( vcd3[gbd+1][gvc][gsub] ),`
186			`.i0 ( vcd0[gbd][gvc][gsub] ),`
187			`.i1 ( vcd1[gbd][gvc][gsub] ),`
188			`.i2 ( vcd2[gbd][gvc][gsub] ),`
189			`.i3 ( vcd3[gbd][gvc][gsub] ),`
190			`.oa ( vcdadn[gbd+1][gvc][gsub] )`
191	40	wsong0210	`);`
192	45	wsong0210	`assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rst_n;`
193	40	wsong0210	`end // block: SC`
194
195			`pipen #(.DW(FT))`
196			`TP (`
197			`.d_in ( vcdt[gbd][gvc] ),`
198			`.d_in_a ( vcdat[gbd][gvc] ),`
199			`.d_out ( vcdt[gbd+1][gvc] ),`
200			`.d_out_a ( vcdatn[gbd+1][gvc] )`
201			`);`
202
203	45	wsong0210	`assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rst_n;`
204	40	wsong0210
205			`pipen #(.DW(2))`
206			`CTP (`
207			`.d_in ( vcft[gbd][gvc] ),`
208			`.d_in_a ( vcfta[gbd][gvc] ),`
209			`.d_out ( vcft[gbd+1][gvc] ),`
210			`.d_out_a ( vcftan[gbd+1][gvc] )`
211			`);`
212
213	45	wsong0210	`assign vcftan[gbd+1][gvc] = (~vcfta[gbd+1][gvc])&rst_n;`
214	40	wsong0210	`end // block: V`
215			`end // block: BFL2`
216
217			`for(gvc=0; gvc<VCN; gvc++) begin:BFL2V`
218			`ctree #(.DW(SCN+2)) ACKT(.ci({vcfta[PD2-2][gvc], vcdat[PD2-2][gvc], vcdad[PD*2-2][gvc]}), .co(vcda[0][gvc]));`
219			`assign vcdat[PD*2][gvc] = vcda[1][gvc];`
220			`assign vcdad[PD*2][gvc] = {SCN{vcda[1][gvc]}};`
221			`assign vcfta[PD*2][gvc] = swa[gvc];`
222			`assign vcft[PD2-2][gvc] = {vcdt[PD2-2][gvc][FT-1], \|vcdt[PD*2-2][gvc][FT-2:0]};`
223			`assign swr[gvc] = vcft[PD*2][gvc];`
224			`end`
225
226			`endgenerate`
227
228
229			`// the routing guide pipeline stage`
230			`generate`
231			`for(gvc=0; gvc<VCN; gvc++) begin:R`
232			`pipen #(.DW(SN))`
233			`RP (`
234			`.d_in ( swrt[gvc] ),`
235			`.d_in_a ( swa[gvc] ),`
236			`.d_out ( rtg[gvc] ),`
237	45	wsong0210	`.d_out_a ( (~vcda[1][gvc])&rst_n )`
238	40	wsong0210	`);`
239			`end`
240			`endgenerate`
241
242			`generate`
243			`for(gvc=0; gvc<VCN; gvc++) begin:LPS`
244
245			`// credit control`
246	45	wsong0210	`dc2 FCP (.q(cor[gvc]), .d(\|rtg[gvc]), .a((~coa[gvc])&rst_n));`
247	40	wsong0210
248			`// output name conversation`
249			`assign do0[gvc] = vcd0[PD*2][gvc];`
250			`assign do1[gvc] = vcd1[PD*2][gvc];`
251			`assign do2[gvc] = vcd2[PD*2][gvc];`
252			`assign do3[gvc] = vcd3[PD*2][gvc];`
253
254			`assign dot[gvc] = vcdt[PD*2][gvc];`
255			`assign dortg[gvc] = rtg[gvc];`
256
257			`c2 AC (.q(vcda[1][gvc]), .a0(cor[gvc]), .a1(doa[gvc]));`
258
259			`end // block: LPS`
260			`endgenerate`
261
262			`// routing unit`
263	46	wsong0210	`rtu #(.VCN(VCN), .DIR(DIR), .SN(SN), .PD(PD))`
264	40	wsong0210	`RTC (`
265			`.dia ( rua ),`
266			`.dort ( vcr ),`
267	45	wsong0210	`.rst_n ( rst_n ),`
268	40	wsong0210	`.di0 ( di0m[3:0] ),`
269			`.di1 ( di1m[3:0] ),`
270			`.di2 ( di2m[3:0] ),`
271			`.di3 ( di3m[3:0] ),`
272			`.dit ( ditm ),`
273			`.divc ( divcm ),`
274			`.addrx ( addrx ),`
275			`.addry ( addry ),`
276			`.doa ( vcra )`
277			`);`
278
279			`endmodule // inpbuf`
280
281
282
283
284
285
286	46	wsong0210

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