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[/] [ata/] [trunk/] [bench/] [verilog/] [ata_device.v] - Blame information for rev 16

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  ATA (IDE) Device Model                                     ////
////  This Model Supports PIO cycles only !                      ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ata/       ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ata_device.v,v 1.1 2001-08-16 10:01:05 rudi Exp $
//
//  $Date: 2001-08-16 10:01:05 $
//  $Revision: 1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//
//                        
 
`timescale 1ns / 10ps
 
module ata_device(      ata_rst_, ata_data, ata_da, ata_cs0, ata_cs1,
                        ata_dior_, ata_diow_, ata_iordy, ata_intrq );
input           ata_rst_;
inout   [15:0]   ata_data;
input   [2:0]    ata_da;
input           ata_cs0, ata_cs1;
input           ata_dior_, ata_diow_;
output          ata_iordy;
output          ata_intrq;
 
integer         mode;
integer         n;
reg             ata_iordy;
reg             iordy_enable;
integer         iordy_delay;
 
reg     [15:0]   mem[32:0];
reg     [15:0]   dout;
reg             dout_en;
wire            ata_rst_m0, ata_rst_m1, ata_rst_m2, ata_rst_m3, ata_rst_m4;
wire    [4:0]    addr;
wire            ata_dior, ata_diow;
 
initial
   begin
        dout_en = 0;
        mode = 0;
        iordy_enable = 0;
        iordy_delay  = 0;
        ata_iordy    = 1;
   end
 
assign ata_dior = !ata_dior_;
assign ata_diow = !ata_diow_;
 
assign ata_intrq = 0;
 
assign ata_data = dout_en ? dout : 16'hzzzz;
 
assign addr = {~ata_cs1, ~ata_cs0, ata_da};
 
always @(posedge ata_rst_)
        dout_en = 0;
 
always @(posedge ata_dior)
   begin
        dout = mem[ addr ];
        dout_en = 1;
   end
 
always @(negedge ata_dior)
   begin
        dout_en = 0;
   end
 
always @(posedge ata_diow)
   begin
        mem[ addr ] = ata_data;
   end
 
always @(posedge ata_dior or posedge ata_diow)
   begin
        ata_iordy = 1'b0;
        #(iordy_delay);
        ata_iordy = 1'b1;
   end
 
task init_mem;
 
begin
 
for(n=0;n<32;n=n+1)
        mem[n] = n;
end
endtask
 
assign ata_rst_m0 = ata_rst_ & (mode==0);
assign ata_rst_m1 = ata_rst_ & (mode==1);
assign ata_rst_m2 = ata_rst_ & (mode==2);
assign ata_rst_m3 = ata_rst_ & (mode==3);
assign ata_rst_m4 = ata_rst_ & (mode==4);
 
specify
        specparam       // ATA Mode 0 Timing
                        M0_DioCycle     = 600,                  // T0
                        M0_AddrSetup    = 70,                   // T1
                        M0_DioHigh      = 290,                  // T2
                        M0_WrSetup      = 60,                   // T3
                        M0_WrHold       = 30,                   // T4
                        M0_DoutSetup    = 50,                   // T5
                        M0_DoutHold     = 5,                    // T6
                        M0_AddrHold     = 20,                   // T9
 
                        // ATA Mode 1 Timing
                        M1_DioCycle     = 383,                  // T0
                        M1_AddrSetup    = 50,                   // T1
                        M1_DioHigh      = 290,                  // T2
                        M1_WrSetup      = 45,                   // T3
                        M1_WrHold       = 20,                   // T4
                        M1_DoutSetup    = 35,                   // T5
                        M1_DoutHold     = 5,                    // T6
                        M1_AddrHold     = 15,                   // T9
 
                        // ATA Mode 2 Timing
                        M2_DioCycle     = 330,                  // T0
                        M2_AddrSetup    = 30,                   // T1
                        M2_DioHigh      = 290,                  // T2
                        M2_WrSetup      = 30,                   // T3
                        M2_WrHold       = 15,                   // T4
                        M2_DoutSetup    = 20,                   // T5
                        M2_DoutHold     = 5,                    // T6
                        M2_AddrHold     = 10,                   // T9
 
                        // ATA Mode 3 Timing
                        M3_DioCycle     = 180,                  // T0
                        M3_AddrSetup    = 30,                   // T1
                        M3_DioHigh      = 80,                   // T2
                        M3_DioLow       = 70,                   // T2i
                        M3_WrSetup      = 30,                   // T3
                        M3_WrHold       = 10,                   // T4
                        M3_DoutSetup    = 20,                   // T5
                        M3_DoutHold     = 5,                    // T6
                        M3_AddrHold     = 10,                   // T9
 
                        // ATA Mode 4 Timing
                        M4_DioCycle     = 120,                  // T0
                        M4_AddrSetup    = 25,                   // T1
                        M4_DioHigh      = 70,                   // T2
                        M4_DioLow       = 25,                   // T2i
                        M4_WrSetup      = 20,                   // T3
                        M4_WrHold       = 10,                   // T4
                        M4_DoutSetup    = 20,                   // T5
                        M4_DoutHold     = 5,                    // T6
                        M4_AddrHold     = 10;                   // T9
 
 
 
        /////////////////////////////////////////////////////
        // ATA Mode 0 Timing                               //
        /////////////////////////////////////////////////////
 
        // Output Delay Path
        if(mode==0) (ata_dior_ => ata_data) =    //(01,10,0z,z1,1z,z0)
                                        (0,0,
                                        M0_DoutHold, (M0_DioHigh - M0_DoutSetup),
                                        M0_DoutHold, (M0_DioHigh - M0_DoutSetup) );
 
        // Write Data Setup/Hold Check
        $setuphold(negedge ata_diow, ata_data, M0_WrSetup, M0_WrHold, , ,ata_rst_m0 );
 
        // DioX Active time Check
        $width(posedge ata_dior &&& ata_rst_m0, M0_DioHigh );
        $width(posedge ata_diow &&& ata_rst_m0, M0_DioHigh );
 
        // DioX Min Cycle Width Check
        $period(posedge ata_dior &&& ata_rst_m0, M0_DioCycle );
        $period(posedge ata_diow &&& ata_rst_m0, M0_DioCycle );
 
        // Address Setup Hold Checks
        $setup(ata_da,  posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);
        $setup(ata_cs0, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);
        $setup(ata_cs1, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);
        $setup(ata_da,  posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);
        $setup(ata_cs0, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);
        $setup(ata_cs1, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);
 
        $hold(ata_da,  negedge ata_dior &&& ata_rst_m0, M0_AddrHold);
        $hold(ata_cs0, negedge ata_dior &&& ata_rst_m0, M0_AddrHold);
        $hold(ata_cs1, negedge ata_dior &&& ata_rst_m0, M0_AddrHold);
        $hold(ata_da,  negedge ata_diow &&& ata_rst_m0, M0_AddrHold);
        $hold(ata_cs0, negedge ata_diow &&& ata_rst_m0, M0_AddrHold);
        $hold(ata_cs1, negedge ata_diow &&& ata_rst_m0, M0_AddrHold);
 
 
        /////////////////////////////////////////////////////
        // ATA Mode 1 Timing                               //
        /////////////////////////////////////////////////////
 
        // Output Delay Path
        if(mode==1) (ata_dior_ => ata_data) =   //(01,10,0z,z1,1z,z0)
                                        (0,0,
                                        M1_DoutHold, (M1_DioHigh - M1_DoutSetup),
                                        M1_DoutHold, (M1_DioHigh - M1_DoutSetup) );
 
        // Write Data Setup/Hold Check
        $setuphold(negedge ata_diow, ata_data, M1_WrSetup, M1_WrHold, , ,ata_rst_m1 );
 
        // DioX Active time Check
        $width(posedge ata_dior &&& ata_rst_m1, M1_DioHigh );
        $width(posedge ata_diow &&& ata_rst_m1, M1_DioHigh );
 
        // DioX Min Cycle Width Check
        $period(posedge ata_dior &&& ata_rst_m1, M1_DioCycle );
        $period(posedge ata_diow &&& ata_rst_m1, M1_DioCycle );
 
        // Address Setup Hold Checks
        $setup(ata_da,  posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);
        $setup(ata_cs0, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);
        $setup(ata_cs1, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);
        $setup(ata_da,  posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);
        $setup(ata_cs0, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);
        $setup(ata_cs1, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);
 
        $hold(ata_da,  negedge ata_dior &&& ata_rst_m1, M1_AddrHold);
        $hold(ata_cs0, negedge ata_dior &&& ata_rst_m1, M1_AddrHold);
        $hold(ata_cs1, negedge ata_dior &&& ata_rst_m1, M1_AddrHold);
        $hold(ata_da,  negedge ata_diow &&& ata_rst_m1, M1_AddrHold);
        $hold(ata_cs0, negedge ata_diow &&& ata_rst_m1, M1_AddrHold);
        $hold(ata_cs1, negedge ata_diow &&& ata_rst_m1, M1_AddrHold);
 
 
        /////////////////////////////////////////////////////
        // ATA Mode 2 Timing                               //
        /////////////////////////////////////////////////////
 
        // Output Delay Path
        if(mode==2) (ata_dior_ => ata_data) =   //(01,10,0z,z1,1z,z0)
                                        (0,0,
                                        M2_DoutHold, (M2_DioHigh - M2_DoutSetup),
                                        M2_DoutHold, (M2_DioHigh - M2_DoutSetup) );
 
        // Write Data Setup/Hold Check
        $setuphold(negedge ata_diow, ata_data, M2_WrSetup, M2_WrHold, , ,ata_rst_m2 );
 
        // DioX Active time Check
        $width(posedge ata_dior &&& ata_rst_m2, M2_DioHigh );
        $width(posedge ata_diow &&& ata_rst_m2, M2_DioHigh );
 
        // DioX Min Cycle Width Check
        $period(posedge ata_dior &&& ata_rst_m2, M2_DioCycle );
        $period(posedge ata_diow &&& ata_rst_m2, M2_DioCycle );
 
        // Address Setup Hold Checks
        $setup(ata_da,  posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);
        $setup(ata_cs0, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);
        $setup(ata_cs1, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);
        $setup(ata_da,  posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);
        $setup(ata_cs0, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);
        $setup(ata_cs1, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);
 
        $hold(ata_da,  negedge ata_dior &&& ata_rst_m2, M2_AddrHold);
        $hold(ata_cs0, negedge ata_dior &&& ata_rst_m2, M2_AddrHold);
        $hold(ata_cs1, negedge ata_dior &&& ata_rst_m2, M2_AddrHold);
        $hold(ata_da,  negedge ata_diow &&& ata_rst_m2, M2_AddrHold);
        $hold(ata_cs0, negedge ata_diow &&& ata_rst_m2, M2_AddrHold);
        $hold(ata_cs1, negedge ata_diow &&& ata_rst_m2, M2_AddrHold);
 
        /////////////////////////////////////////////////////
        // ATA Mode 3 Timing                               //
        /////////////////////////////////////////////////////
 
        // Output Delay Path
        if(mode==3) (ata_dior_ => ata_data) =   //(01,10,0z,z1,1z,z0)
                                        (0,0,
                                        M3_DoutHold, (M3_DioHigh - M3_DoutSetup),
                                        M3_DoutHold, (M3_DioHigh - M3_DoutSetup) );
 
        // Write Data Setup/Hold Check
        $setuphold(negedge ata_diow, ata_data, M3_WrSetup, M3_WrHold, , ,ata_rst_m3 );
 
        // DioX Active time Check
        $width(posedge ata_dior &&& ata_rst_m3, M3_DioHigh );
        $width(posedge ata_diow &&& ata_rst_m3, M3_DioHigh );
 
        $width(negedge ata_dior &&& ata_rst_m3, M3_DioLow );
        $width(negedge ata_diow &&& ata_rst_m3, M3_DioLow );
 
        // DioX Min Cycle Width Check
        $period(posedge ata_dior &&& ata_rst_m3, M3_DioCycle );
        $period(posedge ata_diow &&& ata_rst_m3, M3_DioCycle );
 
        // Address Setup Hold Checks
        $setup(ata_da,  posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);
        $setup(ata_cs0, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);
        $setup(ata_cs1, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);
        $setup(ata_da,  posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);
        $setup(ata_cs0, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);
        $setup(ata_cs1, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);
 
        $hold(ata_da,  negedge ata_dior &&& ata_rst_m3, M3_AddrHold);
        $hold(ata_cs0, negedge ata_dior &&& ata_rst_m3, M3_AddrHold);
        $hold(ata_cs1, negedge ata_dior &&& ata_rst_m3, M3_AddrHold);
        $hold(ata_da,  negedge ata_diow &&& ata_rst_m3, M3_AddrHold);
        $hold(ata_cs0, negedge ata_diow &&& ata_rst_m3, M3_AddrHold);
        $hold(ata_cs1, negedge ata_diow &&& ata_rst_m3, M3_AddrHold);
 
 
        /////////////////////////////////////////////////////
        // ATA Mode 4 Timing                               //
        /////////////////////////////////////////////////////
 
        // Output Delay Path
        if(mode==4) (ata_dior_ => ata_data) =   //(01,10,0z,z1,1z,z0)
                                        (0,0,
                                        M4_DoutHold, (M4_DioHigh - M4_DoutSetup),
                                        M4_DoutHold, (M4_DioHigh - M4_DoutSetup) );
 
        // Write Data Setup/Hold Check
        $setuphold(negedge ata_diow, ata_data, M4_WrSetup, M4_WrHold, , ,ata_rst_m4 );
 
        // DioX Active time Check
        $width(posedge ata_dior &&& ata_rst_m4, M4_DioHigh );
        $width(posedge ata_diow &&& ata_rst_m4, M4_DioHigh );
 
        $width(negedge ata_dior &&& ata_rst_m4, M4_DioLow );
        $width(negedge ata_diow &&& ata_rst_m4, M4_DioLow );
 
        // DioX Min Cycle Width Check
        $period(posedge ata_dior &&& ata_rst_m4, M4_DioCycle );
        $period(posedge ata_diow &&& ata_rst_m4, M4_DioCycle );
 
        // Address Setup Hold Checks
        $setup(ata_da,  posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);
        $setup(ata_cs0, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);
        $setup(ata_cs1, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);
        $setup(ata_da,  posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);
        $setup(ata_cs0, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);
        $setup(ata_cs1, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);
 
        $hold(ata_da,  negedge ata_dior &&& ata_rst_m4, M4_AddrHold);
        $hold(ata_cs0, negedge ata_dior &&& ata_rst_m4, M4_AddrHold);
        $hold(ata_cs1, negedge ata_dior &&& ata_rst_m4, M4_AddrHold);
        $hold(ata_da,  negedge ata_diow &&& ata_rst_m4, M4_AddrHold);
        $hold(ata_cs0, negedge ata_diow &&& ata_rst_m4, M4_AddrHold);
        $hold(ata_cs1, negedge ata_diow &&& ata_rst_m4, M4_AddrHold);
 
 
 
endspecify
 
 
endmodule
 

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[/] [ata/] [trunk/] [bench/] [verilog/] [ata_device.v] - Blame information for rev 16

Line No.	Rev	Author	Line
1	16	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ATA (IDE) Device Model ////`
4			`//// This Model Supports PIO cycles only ! ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ata/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2001 Rudolf Usselmann ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: ata_device.v,v 1.1 2001-08-16 10:01:05 rudi Exp $`
42			`//`
43			`// $Date: 2001-08-16 10:01:05 $`
44			`// $Revision: 1.1 $`
45			`// $Author: rudi $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`//`
52			`//`
53			`//`
54			`//`
55
56			`timescale 1ns / 10ps
57
58			`module ata_device( ata_rst_, ata_data, ata_da, ata_cs0, ata_cs1,`
59			`ata_dior_, ata_diow_, ata_iordy, ata_intrq );`
60			`input ata_rst_;`
61			`inout [15:0] ata_data;`
62			`input [2:0] ata_da;`
63			`input ata_cs0, ata_cs1;`
64			`input ata_dior_, ata_diow_;`
65			`output ata_iordy;`
66			`output ata_intrq;`
67
68			`integer mode;`
69			`integer n;`
70			`reg ata_iordy;`
71			`reg iordy_enable;`
72			`integer iordy_delay;`
73
74			`reg [15:0] mem[32:0];`
75			`reg [15:0] dout;`
76			`reg dout_en;`
77			`wire ata_rst_m0, ata_rst_m1, ata_rst_m2, ata_rst_m3, ata_rst_m4;`
78			`wire [4:0] addr;`
79			`wire ata_dior, ata_diow;`
80
81			`initial`
82			`begin`
83			`dout_en = 0;`
84			`mode = 0;`
85			`iordy_enable = 0;`
86			`iordy_delay = 0;`
87			`ata_iordy = 1;`
88			`end`
89
90			`assign ata_dior = !ata_dior_;`
91			`assign ata_diow = !ata_diow_;`
92
93			`assign ata_intrq = 0;`
94
95			`assign ata_data = dout_en ? dout : 16'hzzzz;`
96
97			`assign addr = {~ata_cs1, ~ata_cs0, ata_da};`
98
99			`always @(posedge ata_rst_)`
100			`dout_en = 0;`
101
102			`always @(posedge ata_dior)`
103			`begin`
104			`dout = mem[ addr ];`
105			`dout_en = 1;`
106			`end`
107
108			`always @(negedge ata_dior)`
109			`begin`
110			`dout_en = 0;`
111			`end`
112
113			`always @(posedge ata_diow)`
114			`begin`
115			`mem[ addr ] = ata_data;`
116			`end`
117
118			`always @(posedge ata_dior or posedge ata_diow)`
119			`begin`
120			`ata_iordy = 1'b0;`
121			`#(iordy_delay);`
122			`ata_iordy = 1'b1;`
123			`end`
124
125			`task init_mem;`
126
127			`begin`
128
129			`for(n=0;n<32;n=n+1)`
130			`mem[n] = n;`
131			`end`
132			`endtask`
133
134			`assign ata_rst_m0 = ata_rst_ & (mode==0);`
135			`assign ata_rst_m1 = ata_rst_ & (mode==1);`
136			`assign ata_rst_m2 = ata_rst_ & (mode==2);`
137			`assign ata_rst_m3 = ata_rst_ & (mode==3);`
138			`assign ata_rst_m4 = ata_rst_ & (mode==4);`
139
140			`specify`
141			`specparam // ATA Mode 0 Timing`
142			`M0_DioCycle = 600, // T0`
143			`M0_AddrSetup = 70, // T1`
144			`M0_DioHigh = 290, // T2`
145			`M0_WrSetup = 60, // T3`
146			`M0_WrHold = 30, // T4`
147			`M0_DoutSetup = 50, // T5`
148			`M0_DoutHold = 5, // T6`
149			`M0_AddrHold = 20, // T9`
150
151			`// ATA Mode 1 Timing`
152			`M1_DioCycle = 383, // T0`
153			`M1_AddrSetup = 50, // T1`
154			`M1_DioHigh = 290, // T2`
155			`M1_WrSetup = 45, // T3`
156			`M1_WrHold = 20, // T4`
157			`M1_DoutSetup = 35, // T5`
158			`M1_DoutHold = 5, // T6`
159			`M1_AddrHold = 15, // T9`
160
161			`// ATA Mode 2 Timing`
162			`M2_DioCycle = 330, // T0`
163			`M2_AddrSetup = 30, // T1`
164			`M2_DioHigh = 290, // T2`
165			`M2_WrSetup = 30, // T3`
166			`M2_WrHold = 15, // T4`
167			`M2_DoutSetup = 20, // T5`
168			`M2_DoutHold = 5, // T6`
169			`M2_AddrHold = 10, // T9`
170
171			`// ATA Mode 3 Timing`
172			`M3_DioCycle = 180, // T0`
173			`M3_AddrSetup = 30, // T1`
174			`M3_DioHigh = 80, // T2`
175			`M3_DioLow = 70, // T2i`
176			`M3_WrSetup = 30, // T3`
177			`M3_WrHold = 10, // T4`
178			`M3_DoutSetup = 20, // T5`
179			`M3_DoutHold = 5, // T6`
180			`M3_AddrHold = 10, // T9`
181
182			`// ATA Mode 4 Timing`
183			`M4_DioCycle = 120, // T0`
184			`M4_AddrSetup = 25, // T1`
185			`M4_DioHigh = 70, // T2`
186			`M4_DioLow = 25, // T2i`
187			`M4_WrSetup = 20, // T3`
188			`M4_WrHold = 10, // T4`
189			`M4_DoutSetup = 20, // T5`
190			`M4_DoutHold = 5, // T6`
191			`M4_AddrHold = 10; // T9`
192
193
194
195			`/////////////////////////////////////////////////////`
196			`// ATA Mode 0 Timing //`
197			`/////////////////////////////////////////////////////`
198
199			`// Output Delay Path`
200			`if(mode==0) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)`
201			`(0,0,`
202			`M0_DoutHold, (M0_DioHigh - M0_DoutSetup),`
203			`M0_DoutHold, (M0_DioHigh - M0_DoutSetup) );`
204
205			`// Write Data Setup/Hold Check`
206			`$setuphold(negedge ata_diow, ata_data, M0_WrSetup, M0_WrHold, , ,ata_rst_m0 );`
207
208			`// DioX Active time Check`
209			`$width(posedge ata_dior &&& ata_rst_m0, M0_DioHigh );`
210			`$width(posedge ata_diow &&& ata_rst_m0, M0_DioHigh );`
211
212			`// DioX Min Cycle Width Check`
213			`$period(posedge ata_dior &&& ata_rst_m0, M0_DioCycle );`
214			`$period(posedge ata_diow &&& ata_rst_m0, M0_DioCycle );`
215
216			`// Address Setup Hold Checks`
217			`$setup(ata_da, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);`
218			`$setup(ata_cs0, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);`
219			`$setup(ata_cs1, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);`
220			`$setup(ata_da, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);`
221			`$setup(ata_cs0, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);`
222			`$setup(ata_cs1, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);`
223
224			`$hold(ata_da, negedge ata_dior &&& ata_rst_m0, M0_AddrHold);`
225			`$hold(ata_cs0, negedge ata_dior &&& ata_rst_m0, M0_AddrHold);`
226			`$hold(ata_cs1, negedge ata_dior &&& ata_rst_m0, M0_AddrHold);`
227			`$hold(ata_da, negedge ata_diow &&& ata_rst_m0, M0_AddrHold);`
228			`$hold(ata_cs0, negedge ata_diow &&& ata_rst_m0, M0_AddrHold);`
229			`$hold(ata_cs1, negedge ata_diow &&& ata_rst_m0, M0_AddrHold);`
230
231
232			`/////////////////////////////////////////////////////`
233			`// ATA Mode 1 Timing //`
234			`/////////////////////////////////////////////////////`
235
236			`// Output Delay Path`
237			`if(mode==1) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)`
238			`(0,0,`
239			`M1_DoutHold, (M1_DioHigh - M1_DoutSetup),`
240			`M1_DoutHold, (M1_DioHigh - M1_DoutSetup) );`
241
242			`// Write Data Setup/Hold Check`
243			`$setuphold(negedge ata_diow, ata_data, M1_WrSetup, M1_WrHold, , ,ata_rst_m1 );`
244
245			`// DioX Active time Check`
246			`$width(posedge ata_dior &&& ata_rst_m1, M1_DioHigh );`
247			`$width(posedge ata_diow &&& ata_rst_m1, M1_DioHigh );`
248
249			`// DioX Min Cycle Width Check`
250			`$period(posedge ata_dior &&& ata_rst_m1, M1_DioCycle );`
251			`$period(posedge ata_diow &&& ata_rst_m1, M1_DioCycle );`
252
253			`// Address Setup Hold Checks`
254			`$setup(ata_da, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);`
255			`$setup(ata_cs0, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);`
256			`$setup(ata_cs1, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);`
257			`$setup(ata_da, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);`
258			`$setup(ata_cs0, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);`
259			`$setup(ata_cs1, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);`
260
261			`$hold(ata_da, negedge ata_dior &&& ata_rst_m1, M1_AddrHold);`
262			`$hold(ata_cs0, negedge ata_dior &&& ata_rst_m1, M1_AddrHold);`
263			`$hold(ata_cs1, negedge ata_dior &&& ata_rst_m1, M1_AddrHold);`
264			`$hold(ata_da, negedge ata_diow &&& ata_rst_m1, M1_AddrHold);`
265			`$hold(ata_cs0, negedge ata_diow &&& ata_rst_m1, M1_AddrHold);`
266			`$hold(ata_cs1, negedge ata_diow &&& ata_rst_m1, M1_AddrHold);`
267
268
269			`/////////////////////////////////////////////////////`
270			`// ATA Mode 2 Timing //`
271			`/////////////////////////////////////////////////////`
272
273			`// Output Delay Path`
274			`if(mode==2) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)`
275			`(0,0,`
276			`M2_DoutHold, (M2_DioHigh - M2_DoutSetup),`
277			`M2_DoutHold, (M2_DioHigh - M2_DoutSetup) );`
278
279			`// Write Data Setup/Hold Check`
280			`$setuphold(negedge ata_diow, ata_data, M2_WrSetup, M2_WrHold, , ,ata_rst_m2 );`
281
282			`// DioX Active time Check`
283			`$width(posedge ata_dior &&& ata_rst_m2, M2_DioHigh );`
284			`$width(posedge ata_diow &&& ata_rst_m2, M2_DioHigh );`
285
286			`// DioX Min Cycle Width Check`
287			`$period(posedge ata_dior &&& ata_rst_m2, M2_DioCycle );`
288			`$period(posedge ata_diow &&& ata_rst_m2, M2_DioCycle );`
289
290			`// Address Setup Hold Checks`
291			`$setup(ata_da, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);`
292			`$setup(ata_cs0, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);`
293			`$setup(ata_cs1, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);`
294			`$setup(ata_da, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);`
295			`$setup(ata_cs0, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);`
296			`$setup(ata_cs1, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);`
297
298			`$hold(ata_da, negedge ata_dior &&& ata_rst_m2, M2_AddrHold);`
299			`$hold(ata_cs0, negedge ata_dior &&& ata_rst_m2, M2_AddrHold);`
300			`$hold(ata_cs1, negedge ata_dior &&& ata_rst_m2, M2_AddrHold);`
301			`$hold(ata_da, negedge ata_diow &&& ata_rst_m2, M2_AddrHold);`
302			`$hold(ata_cs0, negedge ata_diow &&& ata_rst_m2, M2_AddrHold);`
303			`$hold(ata_cs1, negedge ata_diow &&& ata_rst_m2, M2_AddrHold);`
304
305			`/////////////////////////////////////////////////////`
306			`// ATA Mode 3 Timing //`
307			`/////////////////////////////////////////////////////`
308
309			`// Output Delay Path`
310			`if(mode==3) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)`
311			`(0,0,`
312			`M3_DoutHold, (M3_DioHigh - M3_DoutSetup),`
313			`M3_DoutHold, (M3_DioHigh - M3_DoutSetup) );`
314
315			`// Write Data Setup/Hold Check`
316			`$setuphold(negedge ata_diow, ata_data, M3_WrSetup, M3_WrHold, , ,ata_rst_m3 );`
317
318			`// DioX Active time Check`
319			`$width(posedge ata_dior &&& ata_rst_m3, M3_DioHigh );`
320			`$width(posedge ata_diow &&& ata_rst_m3, M3_DioHigh );`
321
322			`$width(negedge ata_dior &&& ata_rst_m3, M3_DioLow );`
323			`$width(negedge ata_diow &&& ata_rst_m3, M3_DioLow );`
324
325			`// DioX Min Cycle Width Check`
326			`$period(posedge ata_dior &&& ata_rst_m3, M3_DioCycle );`
327			`$period(posedge ata_diow &&& ata_rst_m3, M3_DioCycle );`
328
329			`// Address Setup Hold Checks`
330			`$setup(ata_da, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);`
331			`$setup(ata_cs0, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);`
332			`$setup(ata_cs1, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);`
333			`$setup(ata_da, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);`
334			`$setup(ata_cs0, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);`
335			`$setup(ata_cs1, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);`
336
337			`$hold(ata_da, negedge ata_dior &&& ata_rst_m3, M3_AddrHold);`
338			`$hold(ata_cs0, negedge ata_dior &&& ata_rst_m3, M3_AddrHold);`
339			`$hold(ata_cs1, negedge ata_dior &&& ata_rst_m3, M3_AddrHold);`
340			`$hold(ata_da, negedge ata_diow &&& ata_rst_m3, M3_AddrHold);`
341			`$hold(ata_cs0, negedge ata_diow &&& ata_rst_m3, M3_AddrHold);`
342			`$hold(ata_cs1, negedge ata_diow &&& ata_rst_m3, M3_AddrHold);`
343
344
345			`/////////////////////////////////////////////////////`
346			`// ATA Mode 4 Timing //`
347			`/////////////////////////////////////////////////////`
348
349			`// Output Delay Path`
350			`if(mode==4) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)`
351			`(0,0,`
352			`M4_DoutHold, (M4_DioHigh - M4_DoutSetup),`
353			`M4_DoutHold, (M4_DioHigh - M4_DoutSetup) );`
354
355			`// Write Data Setup/Hold Check`
356			`$setuphold(negedge ata_diow, ata_data, M4_WrSetup, M4_WrHold, , ,ata_rst_m4 );`
357
358			`// DioX Active time Check`
359			`$width(posedge ata_dior &&& ata_rst_m4, M4_DioHigh );`
360			`$width(posedge ata_diow &&& ata_rst_m4, M4_DioHigh );`
361
362			`$width(negedge ata_dior &&& ata_rst_m4, M4_DioLow );`
363			`$width(negedge ata_diow &&& ata_rst_m4, M4_DioLow );`
364
365			`// DioX Min Cycle Width Check`
366			`$period(posedge ata_dior &&& ata_rst_m4, M4_DioCycle );`
367			`$period(posedge ata_diow &&& ata_rst_m4, M4_DioCycle );`
368
369			`// Address Setup Hold Checks`
370			`$setup(ata_da, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);`
371			`$setup(ata_cs0, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);`
372			`$setup(ata_cs1, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);`
373			`$setup(ata_da, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);`
374			`$setup(ata_cs0, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);`
375			`$setup(ata_cs1, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);`
376
377			`$hold(ata_da, negedge ata_dior &&& ata_rst_m4, M4_AddrHold);`
378			`$hold(ata_cs0, negedge ata_dior &&& ata_rst_m4, M4_AddrHold);`
379			`$hold(ata_cs1, negedge ata_dior &&& ata_rst_m4, M4_AddrHold);`
380			`$hold(ata_da, negedge ata_diow &&& ata_rst_m4, M4_AddrHold);`
381			`$hold(ata_cs0, negedge ata_diow &&& ata_rst_m4, M4_AddrHold);`
382			`$hold(ata_cs1, negedge ata_diow &&& ata_rst_m4, M4_AddrHold);`
383
384
385
386			`endspecify`
387
388
389			`endmodule`
390