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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  ATA (IDE) Device Model                                     ////
////  This Model Supports PIO cycles only !                      ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/ata/       ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: ata_device.v,v 1.2 2002-02-25 06:07:21 rherveille Exp $
//
//  $Date: 2002-02-25 06:07:21 $
//  $Revision: 1.2 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1  2001/08/16 10:01:05  rudi
//
//               - Added Test Bench
//               - Added Synthesis scripts for Design Compiler
//               - Fixed minor bug in atahost_top
//
//
//
//
//                        
 
`timescale 1ns / 10ps
 
module ata_device(      ata_rst_, ata_data, ata_da, ata_cs0, ata_cs1,
                        ata_dior_, ata_diow_, ata_iordy, ata_intrq );
input           ata_rst_;
inout   [15:0]   ata_data;
input   [2:0]    ata_da;
input           ata_cs0, ata_cs1;
input           ata_dior_, ata_diow_;
output          ata_iordy;
output          ata_intrq;
 
integer         mode;
integer         n;
reg             ata_iordy;
reg             iordy_enable;
integer         iordy_delay;
 
reg     [15:0]   mem[32:0];
reg     [15:0]   dout;
reg             dout_en;
wire            ata_rst_m0, ata_rst_m1, ata_rst_m2, ata_rst_m3, ata_rst_m4;
wire    [4:0]    addr;
wire            ata_dior, ata_diow;
 
initial
   begin
        dout_en = 0;
        mode = 0;
        iordy_enable = 0;
        iordy_delay  = 0;
        ata_iordy    = 1;
   end
 
assign ata_dior = !ata_dior_;
assign ata_diow = !ata_diow_;
 
assign ata_intrq = 0;
 
assign ata_data = dout_en ? dout : 16'hzzzz;
 
assign addr = {~ata_cs1, ~ata_cs0, ata_da};
 
always @(posedge ata_rst_)
        dout_en = 0;
 
always @(posedge ata_dior)
   begin
        dout = mem[ addr ];
        dout_en = 1;
   end
 
always @(posedge ata_dior)
   begin
        dout_en = 0;
   end
 
always @(posedge ata_diow)
   begin
        mem[ addr ] = ata_data;
   end
 
always @(posedge ata_dior or posedge ata_diow)
   begin
        ata_iordy = 1'b0;
        #(iordy_delay);
        ata_iordy = 1'b1;
   end
 
task init_mem;
 
begin
 
for(n=0;n<32;n=n+1)
        mem[n] = n;
end
endtask
 
assign ata_rst_m0 = ata_rst_ & (mode==0);
assign ata_rst_m1 = ata_rst_ & (mode==1);
assign ata_rst_m2 = ata_rst_ & (mode==2);
assign ata_rst_m3 = ata_rst_ & (mode==3);
assign ata_rst_m4 = ata_rst_ & (mode==4);
 
specify
        specparam       // ATA Mode 0 Timing
                        M0_DioCycle     = 600,                  // T0
                        M0_AddrSetup    = 70,                   // T1
                        M0_DioHigh      = 290,                  // T2
                        M0_WrSetup      = 60,                   // T3
                        M0_WrHold       = 30,                   // T4
                        M0_DoutSetup    = 50,                   // T5
                        M0_DoutHold     = 5,                    // T6
                        M0_AddrHold     = 20,                   // T9
 
                        // ATA Mode 1 Timing
                        M1_DioCycle     = 383,                  // T0
                        M1_AddrSetup    = 50,                   // T1
                        M1_DioHigh      = 290,                  // T2
                        M1_WrSetup      = 45,                   // T3
                        M1_WrHold       = 20,                   // T4
                        M1_DoutSetup    = 35,                   // T5
                        M1_DoutHold     = 5,                    // T6
                        M1_AddrHold     = 15,                   // T9
 
                        // ATA Mode 2 Timing
                        M2_DioCycle     = 330,                  // T0
                        M2_AddrSetup    = 30,                   // T1
                        M2_DioHigh      = 290,                  // T2
                        M2_WrSetup      = 30,                   // T3
                        M2_WrHold       = 15,                   // T4
                        M2_DoutSetup    = 20,                   // T5
                        M2_DoutHold     = 5,                    // T6
                        M2_AddrHold     = 10,                   // T9
 
                        // ATA Mode 3 Timing
                        M3_DioCycle     = 180,                  // T0
                        M3_AddrSetup    = 30,                   // T1
                        M3_DioHigh      = 80,                   // T2
                        M3_DioLow       = 70,                   // T2i
                        M3_WrSetup      = 30,                   // T3
                        M3_WrHold       = 10,                   // T4
                        M3_DoutSetup    = 20,                   // T5
                        M3_DoutHold     = 5,                    // T6
                        M3_AddrHold     = 10,                   // T9
 
                        // ATA Mode 4 Timing
                        M4_DioCycle     = 120,                  // T0
                        M4_AddrSetup    = 25,                   // T1
                        M4_DioHigh      = 70,                   // T2
                        M4_DioLow       = 25,                   // T2i
                        M4_WrSetup      = 20,                   // T3
                        M4_WrHold       = 10,                   // T4
                        M4_DoutSetup    = 20,                   // T5
                        M4_DoutHold     = 5,                    // T6
                        M4_AddrHold     = 10;                   // T9
 
 
 
        /////////////////////////////////////////////////////
        // ATA Mode 0 Timing                               //
        /////////////////////////////////////////////////////
 
        // Output Delay Path
        if(mode==0) (ata_dior_ => ata_data) =    //(01,10,0z,z1,1z,z0)
                                        (0,0,
                                        M0_DoutHold, (M0_DioHigh - M0_DoutSetup),
                                        M0_DoutHold, (M0_DioHigh - M0_DoutSetup) );
 
        // Write Data Setup/Hold Check
        $setuphold(negedge ata_diow, ata_data, M0_WrSetup, M0_WrHold, , ,ata_rst_m0 );
 
        // DioX Active time Check
        $width(posedge ata_dior &&& ata_rst_m0, M0_DioHigh );
        $width(posedge ata_diow &&& ata_rst_m0, M0_DioHigh );
 
        // DioX Min Cycle Width Check
        $period(posedge ata_dior &&& ata_rst_m0, M0_DioCycle );
        $period(posedge ata_diow &&& ata_rst_m0, M0_DioCycle );
 
        // Address Setup Hold Checks
        $setup(ata_da,  posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);
        $setup(ata_cs0, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);
        $setup(ata_cs1, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);
        $setup(ata_da,  posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);
        $setup(ata_cs0, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);
        $setup(ata_cs1, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);
 
        $hold(ata_da,  negedge ata_dior &&& ata_rst_m0, M0_AddrHold);
        $hold(ata_cs0, negedge ata_dior &&& ata_rst_m0, M0_AddrHold);
        $hold(ata_cs1, negedge ata_dior &&& ata_rst_m0, M0_AddrHold);
        $hold(ata_da,  negedge ata_diow &&& ata_rst_m0, M0_AddrHold);
        $hold(ata_cs0, negedge ata_diow &&& ata_rst_m0, M0_AddrHold);
        $hold(ata_cs1, negedge ata_diow &&& ata_rst_m0, M0_AddrHold);
 
 
        /////////////////////////////////////////////////////
        // ATA Mode 1 Timing                               //
        /////////////////////////////////////////////////////
 
        // Output Delay Path
        if(mode==1) (ata_dior_ => ata_data) =   //(01,10,0z,z1,1z,z0)
                                        (0,0,
                                        M1_DoutHold, (M1_DioHigh - M1_DoutSetup),
                                        M1_DoutHold, (M1_DioHigh - M1_DoutSetup) );
 
        // Write Data Setup/Hold Check
        $setuphold(negedge ata_diow, ata_data, M1_WrSetup, M1_WrHold, , ,ata_rst_m1 );
 
        // DioX Active time Check
        $width(posedge ata_dior &&& ata_rst_m1, M1_DioHigh );
        $width(posedge ata_diow &&& ata_rst_m1, M1_DioHigh );
 
        // DioX Min Cycle Width Check
        $period(posedge ata_dior &&& ata_rst_m1, M1_DioCycle );
        $period(posedge ata_diow &&& ata_rst_m1, M1_DioCycle );
 
        // Address Setup Hold Checks
        $setup(ata_da,  posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);
        $setup(ata_cs0, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);
        $setup(ata_cs1, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);
        $setup(ata_da,  posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);
        $setup(ata_cs0, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);
        $setup(ata_cs1, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);
 
        $hold(ata_da,  negedge ata_dior &&& ata_rst_m1, M1_AddrHold);
        $hold(ata_cs0, negedge ata_dior &&& ata_rst_m1, M1_AddrHold);
        $hold(ata_cs1, negedge ata_dior &&& ata_rst_m1, M1_AddrHold);
        $hold(ata_da,  negedge ata_diow &&& ata_rst_m1, M1_AddrHold);
        $hold(ata_cs0, negedge ata_diow &&& ata_rst_m1, M1_AddrHold);
        $hold(ata_cs1, negedge ata_diow &&& ata_rst_m1, M1_AddrHold);
 
 
        /////////////////////////////////////////////////////
        // ATA Mode 2 Timing                               //
        /////////////////////////////////////////////////////
 
        // Output Delay Path
        if(mode==2) (ata_dior_ => ata_data) =   //(01,10,0z,z1,1z,z0)
                                        (0,0,
                                        M2_DoutHold, (M2_DioHigh - M2_DoutSetup),
                                        M2_DoutHold, (M2_DioHigh - M2_DoutSetup) );
 
        // Write Data Setup/Hold Check
        $setuphold(negedge ata_diow, ata_data, M2_WrSetup, M2_WrHold, , ,ata_rst_m2 );
 
        // DioX Active time Check
        $width(posedge ata_dior &&& ata_rst_m2, M2_DioHigh );
        $width(posedge ata_diow &&& ata_rst_m2, M2_DioHigh );
 
        // DioX Min Cycle Width Check
        $period(posedge ata_dior &&& ata_rst_m2, M2_DioCycle );
        $period(posedge ata_diow &&& ata_rst_m2, M2_DioCycle );
 
        // Address Setup Hold Checks
        $setup(ata_da,  posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);
        $setup(ata_cs0, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);
        $setup(ata_cs1, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);
        $setup(ata_da,  posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);
        $setup(ata_cs0, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);
        $setup(ata_cs1, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);
 
        $hold(ata_da,  negedge ata_dior &&& ata_rst_m2, M2_AddrHold);
        $hold(ata_cs0, negedge ata_dior &&& ata_rst_m2, M2_AddrHold);
        $hold(ata_cs1, negedge ata_dior &&& ata_rst_m2, M2_AddrHold);
        $hold(ata_da,  negedge ata_diow &&& ata_rst_m2, M2_AddrHold);
        $hold(ata_cs0, negedge ata_diow &&& ata_rst_m2, M2_AddrHold);
        $hold(ata_cs1, negedge ata_diow &&& ata_rst_m2, M2_AddrHold);
 
        /////////////////////////////////////////////////////
        // ATA Mode 3 Timing                               //
        /////////////////////////////////////////////////////
 
        // Output Delay Path
        if(mode==3) (ata_dior_ => ata_data) =   //(01,10,0z,z1,1z,z0)
                                        (0,0,
                                        M3_DoutHold, (M3_DioHigh - M3_DoutSetup),
                                        M3_DoutHold, (M3_DioHigh - M3_DoutSetup) );
 
        // Write Data Setup/Hold Check
        $setuphold(negedge ata_diow, ata_data, M3_WrSetup, M3_WrHold, , ,ata_rst_m3 );
 
        // DioX Active time Check
        $width(posedge ata_dior &&& ata_rst_m3, M3_DioHigh );
        $width(posedge ata_diow &&& ata_rst_m3, M3_DioHigh );
 
        $width(negedge ata_dior &&& ata_rst_m3, M3_DioLow );
        $width(negedge ata_diow &&& ata_rst_m3, M3_DioLow );
 
        // DioX Min Cycle Width Check
        $period(posedge ata_dior &&& ata_rst_m3, M3_DioCycle );
        $period(posedge ata_diow &&& ata_rst_m3, M3_DioCycle );
 
        // Address Setup Hold Checks
        $setup(ata_da,  posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);
        $setup(ata_cs0, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);
        $setup(ata_cs1, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);
        $setup(ata_da,  posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);
        $setup(ata_cs0, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);
        $setup(ata_cs1, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);
 
        $hold(ata_da,  negedge ata_dior &&& ata_rst_m3, M3_AddrHold);
        $hold(ata_cs0, negedge ata_dior &&& ata_rst_m3, M3_AddrHold);
        $hold(ata_cs1, negedge ata_dior &&& ata_rst_m3, M3_AddrHold);
        $hold(ata_da,  negedge ata_diow &&& ata_rst_m3, M3_AddrHold);
        $hold(ata_cs0, negedge ata_diow &&& ata_rst_m3, M3_AddrHold);
        $hold(ata_cs1, negedge ata_diow &&& ata_rst_m3, M3_AddrHold);
 
 
        /////////////////////////////////////////////////////
        // ATA Mode 4 Timing                               //
        /////////////////////////////////////////////////////
 
        // Output Delay Path
        if(mode==4) (ata_dior_ => ata_data) =   //(01,10,0z,z1,1z,z0)
                                        (0,0,
                                        M4_DoutHold, (M4_DioHigh - M4_DoutSetup),
                                        M4_DoutHold, (M4_DioHigh - M4_DoutSetup) );
 
        // Write Data Setup/Hold Check
        $setuphold(negedge ata_diow, ata_data, M4_WrSetup, M4_WrHold, , ,ata_rst_m4 );
 
        // DioX Active time Check
        $width(posedge ata_dior &&& ata_rst_m4, M4_DioHigh );
        $width(posedge ata_diow &&& ata_rst_m4, M4_DioHigh );
 
        $width(negedge ata_dior &&& ata_rst_m4, M4_DioLow );
        $width(negedge ata_diow &&& ata_rst_m4, M4_DioLow );
 
        // DioX Min Cycle Width Check
        $period(posedge ata_dior &&& ata_rst_m4, M4_DioCycle );
        $period(posedge ata_diow &&& ata_rst_m4, M4_DioCycle );
 
        // Address Setup Hold Checks
        $setup(ata_da,  posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);
        $setup(ata_cs0, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);
        $setup(ata_cs1, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);
        $setup(ata_da,  posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);
        $setup(ata_cs0, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);
        $setup(ata_cs1, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);
 
        $hold(ata_da,  negedge ata_dior &&& ata_rst_m4, M4_AddrHold);
        $hold(ata_cs0, negedge ata_dior &&& ata_rst_m4, M4_AddrHold);
        $hold(ata_cs1, negedge ata_dior &&& ata_rst_m4, M4_AddrHold);
        $hold(ata_da,  negedge ata_diow &&& ata_rst_m4, M4_AddrHold);
        $hold(ata_cs0, negedge ata_diow &&& ata_rst_m4, M4_AddrHold);
        $hold(ata_cs1, negedge ata_diow &&& ata_rst_m4, M4_AddrHold);
 
 
 
endspecify
 
 
endmodule
 
 

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[/] [ata/] [trunk/] [bench/] [verilog/] [ata_device.v] - Blame information for rev 35

Line No.	Rev	Author	Line
1	16	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ATA (IDE) Device Model ////`
4			`//// This Model Supports PIO cycles only ! ////`
5			`//// ////`
6			`//// ////`
7			`//// Author: Rudolf Usselmann ////`
8			`//// rudi@asics.ws ////`
9			`//// ////`
10			`//// ////`
11			`//// Downloaded from: http://www.opencores.org/cores/ata/ ////`
12			`//// ////`
13			`/////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2001 Rudolf Usselmann ////`
16			`//// rudi@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41	30	rherveille	`// $Id: ata_device.v,v 1.2 2002-02-25 06:07:21 rherveille Exp $`
42	16	rudi	`//`
43	30	rherveille	`// $Date: 2002-02-25 06:07:21 $`
44			`// $Revision: 1.2 $`
45			`// $Author: rherveille $`
46	16	rudi	`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51	30	rherveille	`// Revision 1.1 2001/08/16 10:01:05 rudi`
52	16	rudi	`//`
53	30	rherveille	`// - Added Test Bench`
54			`// - Added Synthesis scripts for Design Compiler`
55			`// - Fixed minor bug in atahost_top`
56	16	rudi	`//`
57			`//`
58	30	rherveille	`//`
59			`//`
60	16	rudi	`//`
61
62			`timescale 1ns / 10ps
63
64			`module ata_device( ata_rst_, ata_data, ata_da, ata_cs0, ata_cs1,`
65			`ata_dior_, ata_diow_, ata_iordy, ata_intrq );`
66			`input ata_rst_;`
67			`inout [15:0] ata_data;`
68			`input [2:0] ata_da;`
69			`input ata_cs0, ata_cs1;`
70			`input ata_dior_, ata_diow_;`
71			`output ata_iordy;`
72			`output ata_intrq;`
73
74			`integer mode;`
75			`integer n;`
76			`reg ata_iordy;`
77			`reg iordy_enable;`
78			`integer iordy_delay;`
79
80			`reg [15:0] mem[32:0];`
81			`reg [15:0] dout;`
82			`reg dout_en;`
83			`wire ata_rst_m0, ata_rst_m1, ata_rst_m2, ata_rst_m3, ata_rst_m4;`
84			`wire [4:0] addr;`
85			`wire ata_dior, ata_diow;`
86
87			`initial`
88			`begin`
89			`dout_en = 0;`
90			`mode = 0;`
91			`iordy_enable = 0;`
92			`iordy_delay = 0;`
93			`ata_iordy = 1;`
94			`end`
95
96			`assign ata_dior = !ata_dior_;`
97			`assign ata_diow = !ata_diow_;`
98
99			`assign ata_intrq = 0;`
100
101			`assign ata_data = dout_en ? dout : 16'hzzzz;`
102
103			`assign addr = {~ata_cs1, ~ata_cs0, ata_da};`
104
105			`always @(posedge ata_rst_)`
106			`dout_en = 0;`
107
108			`always @(posedge ata_dior)`
109			`begin`
110			`dout = mem[ addr ];`
111			`dout_en = 1;`
112			`end`
113
114	30	rherveille	`always @(posedge ata_dior)`
115	16	rudi	`begin`
116			`dout_en = 0;`
117			`end`
118
119			`always @(posedge ata_diow)`
120			`begin`
121			`mem[ addr ] = ata_data;`
122			`end`
123
124			`always @(posedge ata_dior or posedge ata_diow)`
125			`begin`
126			`ata_iordy = 1'b0;`
127			`#(iordy_delay);`
128			`ata_iordy = 1'b1;`
129			`end`
130
131			`task init_mem;`
132
133			`begin`
134
135			`for(n=0;n<32;n=n+1)`
136			`mem[n] = n;`
137			`end`
138			`endtask`
139
140			`assign ata_rst_m0 = ata_rst_ & (mode==0);`
141			`assign ata_rst_m1 = ata_rst_ & (mode==1);`
142			`assign ata_rst_m2 = ata_rst_ & (mode==2);`
143			`assign ata_rst_m3 = ata_rst_ & (mode==3);`
144			`assign ata_rst_m4 = ata_rst_ & (mode==4);`
145
146			`specify`
147			`specparam // ATA Mode 0 Timing`
148			`M0_DioCycle = 600, // T0`
149			`M0_AddrSetup = 70, // T1`
150			`M0_DioHigh = 290, // T2`
151			`M0_WrSetup = 60, // T3`
152			`M0_WrHold = 30, // T4`
153			`M0_DoutSetup = 50, // T5`
154			`M0_DoutHold = 5, // T6`
155			`M0_AddrHold = 20, // T9`
156
157			`// ATA Mode 1 Timing`
158			`M1_DioCycle = 383, // T0`
159			`M1_AddrSetup = 50, // T1`
160			`M1_DioHigh = 290, // T2`
161			`M1_WrSetup = 45, // T3`
162			`M1_WrHold = 20, // T4`
163			`M1_DoutSetup = 35, // T5`
164			`M1_DoutHold = 5, // T6`
165			`M1_AddrHold = 15, // T9`
166
167			`// ATA Mode 2 Timing`
168			`M2_DioCycle = 330, // T0`
169			`M2_AddrSetup = 30, // T1`
170			`M2_DioHigh = 290, // T2`
171			`M2_WrSetup = 30, // T3`
172			`M2_WrHold = 15, // T4`
173			`M2_DoutSetup = 20, // T5`
174			`M2_DoutHold = 5, // T6`
175			`M2_AddrHold = 10, // T9`
176
177			`// ATA Mode 3 Timing`
178			`M3_DioCycle = 180, // T0`
179			`M3_AddrSetup = 30, // T1`
180			`M3_DioHigh = 80, // T2`
181			`M3_DioLow = 70, // T2i`
182			`M3_WrSetup = 30, // T3`
183			`M3_WrHold = 10, // T4`
184			`M3_DoutSetup = 20, // T5`
185			`M3_DoutHold = 5, // T6`
186			`M3_AddrHold = 10, // T9`
187
188			`// ATA Mode 4 Timing`
189			`M4_DioCycle = 120, // T0`
190			`M4_AddrSetup = 25, // T1`
191			`M4_DioHigh = 70, // T2`
192			`M4_DioLow = 25, // T2i`
193			`M4_WrSetup = 20, // T3`
194			`M4_WrHold = 10, // T4`
195			`M4_DoutSetup = 20, // T5`
196			`M4_DoutHold = 5, // T6`
197			`M4_AddrHold = 10; // T9`
198
199
200
201			`/////////////////////////////////////////////////////`
202			`// ATA Mode 0 Timing //`
203			`/////////////////////////////////////////////////////`
204
205			`// Output Delay Path`
206			`if(mode==0) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)`
207			`(0,0,`
208			`M0_DoutHold, (M0_DioHigh - M0_DoutSetup),`
209			`M0_DoutHold, (M0_DioHigh - M0_DoutSetup) );`
210
211			`// Write Data Setup/Hold Check`
212			`$setuphold(negedge ata_diow, ata_data, M0_WrSetup, M0_WrHold, , ,ata_rst_m0 );`
213
214			`// DioX Active time Check`
215			`$width(posedge ata_dior &&& ata_rst_m0, M0_DioHigh );`
216			`$width(posedge ata_diow &&& ata_rst_m0, M0_DioHigh );`
217
218			`// DioX Min Cycle Width Check`
219			`$period(posedge ata_dior &&& ata_rst_m0, M0_DioCycle );`
220			`$period(posedge ata_diow &&& ata_rst_m0, M0_DioCycle );`
221
222			`// Address Setup Hold Checks`
223			`$setup(ata_da, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);`
224			`$setup(ata_cs0, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);`
225			`$setup(ata_cs1, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);`
226			`$setup(ata_da, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);`
227			`$setup(ata_cs0, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);`
228			`$setup(ata_cs1, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);`
229
230			`$hold(ata_da, negedge ata_dior &&& ata_rst_m0, M0_AddrHold);`
231			`$hold(ata_cs0, negedge ata_dior &&& ata_rst_m0, M0_AddrHold);`
232			`$hold(ata_cs1, negedge ata_dior &&& ata_rst_m0, M0_AddrHold);`
233			`$hold(ata_da, negedge ata_diow &&& ata_rst_m0, M0_AddrHold);`
234			`$hold(ata_cs0, negedge ata_diow &&& ata_rst_m0, M0_AddrHold);`
235			`$hold(ata_cs1, negedge ata_diow &&& ata_rst_m0, M0_AddrHold);`
236
237
238			`/////////////////////////////////////////////////////`
239			`// ATA Mode 1 Timing //`
240			`/////////////////////////////////////////////////////`
241
242			`// Output Delay Path`
243			`if(mode==1) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)`
244			`(0,0,`
245			`M1_DoutHold, (M1_DioHigh - M1_DoutSetup),`
246			`M1_DoutHold, (M1_DioHigh - M1_DoutSetup) );`
247
248			`// Write Data Setup/Hold Check`
249			`$setuphold(negedge ata_diow, ata_data, M1_WrSetup, M1_WrHold, , ,ata_rst_m1 );`
250
251			`// DioX Active time Check`
252			`$width(posedge ata_dior &&& ata_rst_m1, M1_DioHigh );`
253			`$width(posedge ata_diow &&& ata_rst_m1, M1_DioHigh );`
254
255			`// DioX Min Cycle Width Check`
256			`$period(posedge ata_dior &&& ata_rst_m1, M1_DioCycle );`
257			`$period(posedge ata_diow &&& ata_rst_m1, M1_DioCycle );`
258
259			`// Address Setup Hold Checks`
260			`$setup(ata_da, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);`
261			`$setup(ata_cs0, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);`
262			`$setup(ata_cs1, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);`
263			`$setup(ata_da, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);`
264			`$setup(ata_cs0, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);`
265			`$setup(ata_cs1, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);`
266
267			`$hold(ata_da, negedge ata_dior &&& ata_rst_m1, M1_AddrHold);`
268			`$hold(ata_cs0, negedge ata_dior &&& ata_rst_m1, M1_AddrHold);`
269			`$hold(ata_cs1, negedge ata_dior &&& ata_rst_m1, M1_AddrHold);`
270			`$hold(ata_da, negedge ata_diow &&& ata_rst_m1, M1_AddrHold);`
271			`$hold(ata_cs0, negedge ata_diow &&& ata_rst_m1, M1_AddrHold);`
272			`$hold(ata_cs1, negedge ata_diow &&& ata_rst_m1, M1_AddrHold);`
273
274
275			`/////////////////////////////////////////////////////`
276			`// ATA Mode 2 Timing //`
277			`/////////////////////////////////////////////////////`
278
279			`// Output Delay Path`
280			`if(mode==2) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)`
281			`(0,0,`
282			`M2_DoutHold, (M2_DioHigh - M2_DoutSetup),`
283			`M2_DoutHold, (M2_DioHigh - M2_DoutSetup) );`
284
285			`// Write Data Setup/Hold Check`
286			`$setuphold(negedge ata_diow, ata_data, M2_WrSetup, M2_WrHold, , ,ata_rst_m2 );`
287
288			`// DioX Active time Check`
289			`$width(posedge ata_dior &&& ata_rst_m2, M2_DioHigh );`
290			`$width(posedge ata_diow &&& ata_rst_m2, M2_DioHigh );`
291
292			`// DioX Min Cycle Width Check`
293			`$period(posedge ata_dior &&& ata_rst_m2, M2_DioCycle );`
294			`$period(posedge ata_diow &&& ata_rst_m2, M2_DioCycle );`
295
296			`// Address Setup Hold Checks`
297			`$setup(ata_da, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);`
298			`$setup(ata_cs0, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);`
299			`$setup(ata_cs1, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);`
300			`$setup(ata_da, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);`
301			`$setup(ata_cs0, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);`
302			`$setup(ata_cs1, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);`
303
304			`$hold(ata_da, negedge ata_dior &&& ata_rst_m2, M2_AddrHold);`
305			`$hold(ata_cs0, negedge ata_dior &&& ata_rst_m2, M2_AddrHold);`
306			`$hold(ata_cs1, negedge ata_dior &&& ata_rst_m2, M2_AddrHold);`
307			`$hold(ata_da, negedge ata_diow &&& ata_rst_m2, M2_AddrHold);`
308			`$hold(ata_cs0, negedge ata_diow &&& ata_rst_m2, M2_AddrHold);`
309			`$hold(ata_cs1, negedge ata_diow &&& ata_rst_m2, M2_AddrHold);`
310
311			`/////////////////////////////////////////////////////`
312			`// ATA Mode 3 Timing //`
313			`/////////////////////////////////////////////////////`
314
315			`// Output Delay Path`
316			`if(mode==3) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)`
317			`(0,0,`
318			`M3_DoutHold, (M3_DioHigh - M3_DoutSetup),`
319			`M3_DoutHold, (M3_DioHigh - M3_DoutSetup) );`
320
321			`// Write Data Setup/Hold Check`
322			`$setuphold(negedge ata_diow, ata_data, M3_WrSetup, M3_WrHold, , ,ata_rst_m3 );`
323
324			`// DioX Active time Check`
325			`$width(posedge ata_dior &&& ata_rst_m3, M3_DioHigh );`
326			`$width(posedge ata_diow &&& ata_rst_m3, M3_DioHigh );`
327
328			`$width(negedge ata_dior &&& ata_rst_m3, M3_DioLow );`
329			`$width(negedge ata_diow &&& ata_rst_m3, M3_DioLow );`
330
331			`// DioX Min Cycle Width Check`
332			`$period(posedge ata_dior &&& ata_rst_m3, M3_DioCycle );`
333			`$period(posedge ata_diow &&& ata_rst_m3, M3_DioCycle );`
334
335			`// Address Setup Hold Checks`
336			`$setup(ata_da, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);`
337			`$setup(ata_cs0, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);`
338			`$setup(ata_cs1, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);`
339			`$setup(ata_da, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);`
340			`$setup(ata_cs0, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);`
341			`$setup(ata_cs1, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);`
342
343			`$hold(ata_da, negedge ata_dior &&& ata_rst_m3, M3_AddrHold);`
344			`$hold(ata_cs0, negedge ata_dior &&& ata_rst_m3, M3_AddrHold);`
345			`$hold(ata_cs1, negedge ata_dior &&& ata_rst_m3, M3_AddrHold);`
346			`$hold(ata_da, negedge ata_diow &&& ata_rst_m3, M3_AddrHold);`
347			`$hold(ata_cs0, negedge ata_diow &&& ata_rst_m3, M3_AddrHold);`
348			`$hold(ata_cs1, negedge ata_diow &&& ata_rst_m3, M3_AddrHold);`
349
350
351			`/////////////////////////////////////////////////////`
352			`// ATA Mode 4 Timing //`
353			`/////////////////////////////////////////////////////`
354
355			`// Output Delay Path`
356			`if(mode==4) (ata_dior_ => ata_data) = //(01,10,0z,z1,1z,z0)`
357			`(0,0,`
358			`M4_DoutHold, (M4_DioHigh - M4_DoutSetup),`
359			`M4_DoutHold, (M4_DioHigh - M4_DoutSetup) );`
360
361			`// Write Data Setup/Hold Check`
362			`$setuphold(negedge ata_diow, ata_data, M4_WrSetup, M4_WrHold, , ,ata_rst_m4 );`
363
364			`// DioX Active time Check`
365			`$width(posedge ata_dior &&& ata_rst_m4, M4_DioHigh );`
366			`$width(posedge ata_diow &&& ata_rst_m4, M4_DioHigh );`
367
368			`$width(negedge ata_dior &&& ata_rst_m4, M4_DioLow );`
369			`$width(negedge ata_diow &&& ata_rst_m4, M4_DioLow );`
370
371			`// DioX Min Cycle Width Check`
372			`$period(posedge ata_dior &&& ata_rst_m4, M4_DioCycle );`
373			`$period(posedge ata_diow &&& ata_rst_m4, M4_DioCycle );`
374
375			`// Address Setup Hold Checks`
376			`$setup(ata_da, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);`
377			`$setup(ata_cs0, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);`
378			`$setup(ata_cs1, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);`
379			`$setup(ata_da, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);`
380			`$setup(ata_cs0, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);`
381			`$setup(ata_cs1, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);`
382
383			`$hold(ata_da, negedge ata_dior &&& ata_rst_m4, M4_AddrHold);`
384			`$hold(ata_cs0, negedge ata_dior &&& ata_rst_m4, M4_AddrHold);`
385			`$hold(ata_cs1, negedge ata_dior &&& ata_rst_m4, M4_AddrHold);`
386			`$hold(ata_da, negedge ata_diow &&& ata_rst_m4, M4_AddrHold);`
387			`$hold(ata_cs0, negedge ata_diow &&& ata_rst_m4, M4_AddrHold);`
388			`$hold(ata_cs1, negedge ata_diow &&& ata_rst_m4, M4_AddrHold);`
389
390
391
392			`endspecify`
393
394
395			`endmodule`
396
397	30	rherveille