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1 16 rudi
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Top Level Test Bench                                       ////
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////                                                             ////
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////                                                             ////
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////  Author: Rudolf Usselmann                                   ////
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////          rudi@asics.ws                                      ////
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////                                                             ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org/cores/vga_lcd/   ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2001 Rudolf Usselmann                         ////
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////                    rudi@asics.ws                            ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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//  CVS Log
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//
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//  $Id: test_bench_top.v,v 1.1 2001-08-16 10:01:05 rudi Exp $
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//
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//  $Date: 2001-08-16 10:01:05 $
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//  $Revision: 1.1 $
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//  $Author: rudi $
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//  $Locker:  $
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//  $State: Exp $
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//
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// Change History:
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//               $Log: not supported by cvs2svn $
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//
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//
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//
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//                        
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`timescale 1ns / 10ps
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module test;
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reg             clk;
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reg             rst;
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wire            int;
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wire    [31:0]   wb_addr_i;
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wire    [31:0]   wb_data_i;
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wire    [31:0]   wb_data_o;
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wire    [3:0]    wb_sel_i;
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wire            wb_we_i;
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wire            wb_stb_i;
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wire            wb_cyc_i;
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wire            wb_ack_o;
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wire            wb_err_o;
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wire            ata_rst_;
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wire    [15:0]   ata_dout;
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wire    [15:0]   ata_din;
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wire    [15:0]   ata_data;
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wire            ata_doe;
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wire    [2:0]    ata_da;
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wire            ata_cs0, ata_cs1;
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wire            ata_dior, ata_diow;
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wire            ata_iordy;
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wire            ata_intrq;
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reg             ata_intrq_r;
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// Test Bench Variables
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integer         wd_cnt;
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integer         error_cnt;
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integer         verbose;
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// Misc Variables
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/////////////////////////////////////////////////////////////////////
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//
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// Defines 
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//
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`define CTRL            32'h0000_0000
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`define STAT            32'h0000_0004
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`define PCTR            32'h0000_0008
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`define ATA_DEV         32'h0000_0040
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/////////////////////////////////////////////////////////////////////
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//
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// Simulation Initialization and Start up Section
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//
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initial
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   begin
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        $display("\n\n");
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        $display("******************************************************");
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        $display("* WISHBONE ATA 1 Controller Simulation started ...   *");
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        $display("******************************************************");
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        $display("\n");
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`ifdef WAVES
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        $shm_open("waves");
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        $shm_probe("AS",test,"AS");
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        $display("INFO: Signal dump enabled ...\n\n");
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`endif
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        wd_cnt = 0;
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        error_cnt = 0;
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        clk = 0;
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        rst = 0;
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        verbose = 1;
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        ata_intrq_r=0;
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        repeat(10)      @(posedge clk);
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        rst = 1;
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        repeat(10)      @(posedge clk);
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        // HERE IS WHERE THE TEST CASES GO ...
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if(1)   // Full Regression Run
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   begin
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        io_test1;
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        io_test2;
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        int_test;
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        rst_test;
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   end
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else
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   begin
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        //
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        // TEST DEVELOPMENT AREA
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        //
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$display("\n\n");
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$display("*****************************************************");
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$display("*** DEVELOPMENT Test                              ***");
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$display("*****************************************************\n");
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show_errors;
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$display("*****************************************************");
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$display("*** Test DONE ...                                 ***");
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$display("*****************************************************\n\n");
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   end
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        repeat(100)     @(posedge clk);
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        $finish;
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   end
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/////////////////////////////////////////////////////////////////////
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//
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// System Clock (100Mhz)
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//
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always #5       clk = ~clk;
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/////////////////////////////////////////////////////////////////////
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//
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// Watchdog Counter
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// Terminate simulation if nothing happens ...
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//
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always @(wb_cyc_i or wb_ack_o)
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        wd_cnt <= #5 0;
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always @(posedge clk)
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        wd_cnt <= #1 wd_cnt + 1;
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always @(wd_cnt)
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        if(wd_cnt>5000)
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           begin
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                $display("\n\n*************************************\n");
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                $display("ERROR: Watch Dog Counter Expired\n");
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                $display("*************************************\n\n\n");
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                $finish;
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           end
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/////////////////////////////////////////////////////////////////////
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//
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// DUT & Models
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//
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// Create an external Tri-State Bus to the ATA Device
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assign ata_din  = ata_data;
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assign ata_data = ata_doe ? ata_dout : 16'hzzzz;
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// DUT: ATA Host
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atahost_top u0( //-- WISHBONE SYSCON signals
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                .wb_clk_i(              clk             ),
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                .rst_nreset_i(          rst             ),
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                .wb_rst_i(              ~rst            ),
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                //-- WISHBONE SLAVE signals
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                .wb_cyc_i(              wb_cyc_i        ),
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                .wb_stb_i(              wb_stb_i        ),
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                .wb_ack_o(              wb_ack_o        ),
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                .wb_err_o(              wb_err_o        ),
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                .wb_adr_i(              wb_addr_i[6:2]  ),
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                .wb_dat_i(              wb_data_i       ),
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                .wb_dat_o(              wb_data_o       ),
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                .wb_sel_i(              wb_sel_i        ),
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                .wb_we_i(               wb_we_i         ),
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                .wb_inta_o(             int             ),
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                //-- ATA signals
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                .ata_resetn_pad_o(      ata_rst_        ),
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                .ata_dd_pad_i(          ata_din         ),
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                .ata_dd_pad_o(          ata_dout        ),
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                .ata_dd_pad_oe(         ata_doe         ),
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                .ata_da_pad_o(          ata_da          ),
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                .ata_cs0n_pad_o(        ata_cs0         ),
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                .ata_cs1n_pad_o(        ata_cs1         ),
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                .ata_diorn_pad_o(       ata_dior_       ),
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                .ata_diown_pad_o(       ata_diow_       ),
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                .ata_iordy_pad_i(       ata_iordy       ),
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                .ata_intrq_pad_i(       ata_intrq_r     )
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                );
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// ATA Device Model
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ata_device a0(  .ata_rst_(      ata_rst_        ),
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                .ata_data(      ata_data        ),
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                .ata_da(        ata_da          ),
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                .ata_cs0(       ata_cs0         ),
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                .ata_cs1(       ata_cs1         ),
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                .ata_dior_(     ata_dior_       ),
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                .ata_diow_(     ata_diow_       ),
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                .ata_iordy(     ata_iordy       ),
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                .ata_intrq(     ata_intrq       ) );
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// WISHBONE Master Model
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wb_mast m0(     .clk(           clk             ),
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                .rst(           rst             ),
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                .adr(           wb_addr_i       ),
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                .din(           wb_data_o       ),
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                .dout(          wb_data_i       ),
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                .cyc(           wb_cyc_i        ),
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                .stb(           wb_stb_i        ),
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                .sel(           wb_sel_i        ),
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                .we(            wb_we_i         ),
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                .ack(           wb_ack_o        ),
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                .err(           wb_err_o        ),
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                .rty(           1'b0            ) );
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// External Tests
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`include "tests.v"
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endmodule
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