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[/] [ata/] [trunk/] [bench/] [verilog/] [tests.v] - Blame information for rev 35

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Tests Library                                              ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/vga_lcd/   ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: tests.v,v 1.1 2001-08-16 10:01:05 rudi Exp $
//
//  $Date: 2001-08-16 10:01:05 $
//  $Revision: 1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//
//                        
 
 
task show_errors;
begin
 
$display("\n");
$display("     +--------------------+");
$display("     |  Total ERRORS: %0d   |", error_cnt);
$display("     +--------------------+");
 
end
endtask
 
 
task reg_test;
 
reg     [31:0]   data;
reg     [31:0]   pattern;
integer         n;
 
begin
$display("\n\n");
$display("*****************************************************");
$display("*** Register Test                                 ***");
$display("*****************************************************\n");
 
 
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
 
task io_test1;
 
reg     [31:0]   data;
reg     [31:0]   data1;
reg     [31:0]   data2;
reg     [31:0]   data3;
integer         n;
integer         id;
integer         del;
integer         del_max;
integer         iordy_del;
 
begin
$display("\n\n");
$display("*****************************************************");
$display("*** IO Test 1                                     ***");
$display("*** Testing WISHBONE wait state insertion, and    ***");
$display("*** iordy assertion.                              ***");
$display("*****************************************************\n");
 
id = 0;
del_max = 16;
for(del=0;del<del_max;del=del+1)
for(id=0;id<2;id=id+1)
begin
        if(!verbose)
        $display("*** MODE SELECT: 'iordy' enable: %0d, wb-delay: %0d\n", id, del);
 
for(iordy_del=0;iordy_del<(id ? 600 : 1);iordy_del=iordy_del+10)
   begin
 
        if(verbose)
        $display("*** MODE SELECT: 'iordy' enable: %0d, wb-delay: %0d iordy_del: %0d\n",
                id, del, iordy_del);
 
        a0.iordy_enable = id;
        a0.iordy_delay = 600;   // Delay in nS
        a0.init_mem;
 
        if(id==1)       data1 = 32'h0000_0082;
        else            data1 = 32'h0000_0080;
        m0.wb_wr1( `CTRL, 4'hf, data1);
        m0.wb_rd1( `CTRL, 4'hf, data );
        if(data != data1 )
           begin
                $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)",
                        data1, data, $time);
                error_cnt = error_cnt + 1;
           end
 
        m0.wb_rd1( `STAT, 4'hf, data );
        m0.wb_rd1( `PCTR, 4'hf, data );
 
        repeat(10)      @(posedge clk);
 
        // Read only Test of ATA registers
        if(verbose)     $display(">>> Running Read Only test 1 ... (%0t)", $time);
        for(n=0;n<16;n=n+1)
           begin
                m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data );
                if(data[15:0] != (n+8) )
                   begin
                        $display("ERROR: Read 1 Mismatch: Expected: %h Got: %h (%0t)",
                                (n+8), data[15:0], $time);
                        error_cnt = error_cnt + 1;
                   end
           end
        if(verbose)     $display("");
 
        // Write Then Read Test of ATA registers
        if(verbose)     $display(">>> Running Read/Write test 1 ... (%0t)", $time);
 
        for(n=0;n<16;n=n+1)
           begin
                m0.wb_wr1( `ATA_DEV + (n*4) , 4'hf, ~n[15:0] );
                if(a0.mem[n+8] != ~n[15:0] )
                   begin
                        $display("ERROR: Write 1 Mismatch: Expected: %h Got: %h (%0t)",
                                ~n[15:0], a0.mem[n+8], $time);
                        error_cnt = error_cnt + 1;
                   end
           end
 
        for(n=0;n<16;n=n+1)
           begin
                m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data );
                if(data[15:0] != ~n[15:0] )
                   begin
                        $display("ERROR: Read 2 Mismatch: Expected: %h Got: %h (%0t)",
                                ~n[15:0], data[15:0], $time);
                        error_cnt = error_cnt + 1;
                   end
           end
        if(verbose)     $display("");
 
        // Write Then Read Test of ATA registers
        if(verbose)     $display(">>> Running Read/Write test 2 ... (%0t)", $time);
 
        for(n=0;n<16;n=n+1)
           begin
                m0.wb_wr1( `ATA_DEV + (n*4) , 4'hf, n[15:0] );
                m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data );
                if(data[15:0] != n[15:0] )
                   begin
                        $display("ERROR: Read 3 Mismatch: Expected: %h Got: %h (%0t)",
                                n[15:0], data[15:0], $time);
                        error_cnt = error_cnt + 1;
                   end
           end
        if(verbose)     $display("");
 
 
        // Write Then Read Test of ATA registers
        if(verbose)     $display(">>> Running Read/Write test 3 ... (%0t)", $time);
 
        for(n=0;n<16;n=n+4)
           begin
                m0.wb_wr4( `ATA_DEV + (n*4) , 4'hf, del,
                                {16'h0, ~n[13:0], 2'h3},
                                {16'h0, ~n[13:0], 2'h2},
                                {16'h0, ~n[13:0], 2'h1},
                                {16'h0, ~n[13:0], 2'h0}          );
 
                m0.wb_rd4( `ATA_DEV + (n*4) , 4'hf, del, data, data1, data2, data3 );
 
                if(     (data[15:0]  != {~n[13:0], 2'h3}) |
                        (data1[15:0] != {~n[13:0], 2'h2}) |
                        (data2[15:0] != {~n[13:0], 2'h1}) |
                        (data3[15:0] != {~n[13:0], 2'h0}) )
                   begin
                        $display("ERROR: Read 3 Mismatch: Expected: %h Got: %h (%0t)",
                                n[15:0], data[15:0], $time);
                        error_cnt = error_cnt + 1;
                   end
           end
        if(verbose)     $display("");
 
 
        // Write Then Read Test of ATA registers
        if(verbose)     $display(">>> Running Read/Write test 4 (RMW) ... (%0t)", $time);
 
        a0.init_mem;
 
        for(n=0;n<16;n=n+1)
           begin
                m0.wr_mem[n] = n[15:0];
                m0.wb_rmw( `ATA_DEV + (n*4) , 4'hf, del, 1, 1);
                data = m0.rd_mem[n];
 
                data2[15:0] =  n[15:0] + 8;
 
                data1 = a0.mem[n+8];
                data3 = n[15:0];
 
                if(     (data[15:0]  != data2[15:0] ) |
                        (data1[15:0] != data3[15:0]) )
                   begin
                        $display("ERROR: Read 4a Mismatch: Expected: %h Got: %h (%0t)",
                                data2[15:0], data[15:0], $time);
                        $display("ERROR: Read 4b Mismatch: Expected: %h Got: %h (%0t)",
                                data1[15:0], data3[15:0], $time);
                        error_cnt = error_cnt + 1;
                   end
           end
        if(verbose)     $display("");
 
   end
end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
task io_test2;
 
reg     [31:0]   data;
reg     [31:0]   data1;
reg     [31:0]   data2;
reg     [31:0]   data3;
integer         n;
integer         id;
integer         del;
integer         del_max;
integer         pio_mode;
integer         iordy_del;
 
begin
$display("\n\n");
$display("*****************************************************");
$display("*** IO Test 2                                     ***");
$display("*** Testing PIO Modes, iordy assertion and        ***");
$display("*** iordy delays.                                 ***");
$display("*****************************************************\n");
 
id = 0;
del = 1;
verbose = 0;
iordy_del = 0;
pio_mode=4;
 
for(pio_mode=0;pio_mode<5;pio_mode=pio_mode+1)
for(id=0;id<2;id=id+1)
begin
        if(!verbose)
        $display("*** MODE SELECT: PIO mode: %0d iordy enable: %0d", pio_mode, id);
 
for(iordy_del=0;iordy_del < (id ? 600 : 1); iordy_del=iordy_del+1)
   begin
 
        if(verbose)
        $display("*** MODE SELECT: PIO mode: %0d, 'iordy' enable: %0d iordy del: %0d\n",
                pio_mode, id, iordy_del );
 
        a0.mode = pio_mode;
        a0.iordy_enable = id;
        a0.iordy_delay = iordy_del;     // Delay in nS
        a0.init_mem;
 
        data1 = 32'h0000_0001;
        m0.wb_wr1( `CTRL, 4'hf, data1);
        m0.wb_rd1( `CTRL, 4'hf, data );
        if(data != data1 )
           begin
                $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)",
                        data1, data, $time);
                error_cnt = error_cnt + 1;
           end
 
        data1 = 32'h1000_0000;
        m0.wb_rd1( `STAT, 4'hf, data );
        if(data != data1 )
           begin
                $display("ERROR: STAT Register read Mismatch: Expected: %h Got: %h (%0t)",
                        data1, data, $time);
                error_cnt = error_cnt + 1;
           end
 
        case(pio_mode)
           0: data1 = {8'h18, 8'h02, 8'h1c, 8'h04};      // Teoc, T4, T2, T1
           1: data1 = {8'h05, 8'h01, 8'h1c, 8'h02};     // Teoc, T4, T2, T1
           2: data1 = {8'h01, 8'h01, 8'h1c, 8'h00};     // Teoc, T4, T2, T1
           3: data1 = {8'h07, 8'h00, 8'h07, 8'h00};     // Teoc, T4, T2, T1
           4: data1 = {8'h02, 8'h00, 8'h06, 8'h00};     // Teoc, T4, T2, T1
        endcase
        m0.wb_wr1( `PCTR, 4'hf, data1);
        m0.wb_rd1( `PCTR, 4'hf, data );
        if(data != data1 )
           begin
                $display("ERROR: PCTR Register write Mismatch: Expected: %h Got: %h (%0t)",
                        data1, data, $time);
                error_cnt = error_cnt + 1;
           end
 
        if(id==1)       data1 = 32'h0000_0082;
        else            data1 = 32'h0000_0080;
        m0.wb_wr1( `CTRL, 4'hf, data1);
        m0.wb_rd1( `CTRL, 4'hf, data );
        if(data != data1 )
           begin
                $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)",
                        data1, data, $time);
                error_cnt = error_cnt + 1;
           end
 
        repeat(10)      @(posedge clk);
 
        // Read only Test of ATA registers
        if(verbose)     $display(">>> Running Read Only test 1 ... (%0t)", $time);
        for(n=0;n<16;n=n+1)
           begin
                m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data );
                if(data[15:0] != (n+8) )
                   begin
                        $display("ERROR: Read 1 Mismatch: Expected: %h Got: %h (%0t)",
                                (n+8), data[15:0], $time);
                        error_cnt = error_cnt + 1;
                   end
           end
        if(verbose)     $display("");
 
        // Write Then Read Test of ATA registers
        if(verbose)     $display(">>> Running Read/Write test 1 ... (%0t)", $time);
 
        for(n=0;n<16;n=n+1)
           begin
                m0.wb_wr1( `ATA_DEV + (n*4) , 4'hf, ~n[15:0] );
                if(a0.mem[n+8] != ~n[15:0] )
                   begin
                        $display("ERROR: Write 1 Mismatch: Expected: %h Got: %h (%0t)",
                                ~n[15:0], a0.mem[n+8], $time);
                        error_cnt = error_cnt + 1;
                   end
           end
 
        for(n=0;n<16;n=n+1)
           begin
                m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data );
                if(data[15:0] != ~n[15:0] )
                   begin
                        $display("ERROR: Read 2 Mismatch: Expected: %h Got: %h (%0t)",
                                ~n[15:0], data[15:0], $time);
                        error_cnt = error_cnt + 1;
                   end
           end
        if(verbose)     $display("");
 
        // Write Then Read Test of ATA registers
        if(verbose)     $display(">>> Running Read/Write test 2 ... (%0t)", $time);
 
        for(n=0;n<16;n=n+1)
           begin
                m0.wb_wr1( `ATA_DEV + (n*4) , 4'hf, n[15:0] );
                m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data );
                if(data[15:0] != n[15:0] )
                   begin
                        $display("ERROR: Read 3 Mismatch: Expected: %h Got: %h (%0t)",
                                n[15:0], data[15:0], $time);
                        error_cnt = error_cnt + 1;
                   end
           end
        if(verbose)     $display("");
 
 
        // Write Then Read Test of ATA registers
        if(verbose)     $display(">>> Running Read/Write test 3 ... (%0t)", $time);
 
        for(n=0;n<16;n=n+4)
           begin
                m0.wb_wr4( `ATA_DEV + (n*4) , 4'hf, del,
                                {16'h0, ~n[13:0], 2'h3},
                                {16'h0, ~n[13:0], 2'h2},
                                {16'h0, ~n[13:0], 2'h1},
                                {16'h0, ~n[13:0], 2'h0}          );
 
                m0.wb_rd4( `ATA_DEV + (n*4) , 4'hf, del, data, data1, data2, data3 );
 
                if(     (data[15:0]  != {~n[13:0], 2'h3}) |
                        (data1[15:0] != {~n[13:0], 2'h2}) |
                        (data2[15:0] != {~n[13:0], 2'h1}) |
                        (data3[15:0] != {~n[13:0], 2'h0}) )
                   begin
                        $display("ERROR: Read 3 Mismatch: Expected: %h Got: %h (%0t)",
                                n[15:0], data[15:0], $time);
                        error_cnt = error_cnt + 1;
                   end
           end
        if(verbose)     $display("");
 
 
        // Write Then Read Test of ATA registers
        if(verbose)     $display(">>> Running Read/Write test 4 (RMW) ... (%0t)", $time);
 
        a0.init_mem;
 
        for(n=0;n<16;n=n+1)
           begin
                m0.wr_mem[n] = n[15:0];
                m0.wb_rmw( `ATA_DEV + (n*4) , 4'hf, del, 1, 1);
                data = m0.rd_mem[n];
 
                data2[15:0] =  n[15:0] + 8;
 
                data1 = a0.mem[n+8];
                data3 = n[15:0];
 
                if(     (data[15:0]  != data2[15:0] ) |
                        (data1[15:0] != data3[15:0]) )
                   begin
                        $display("ERROR: Read 4a Mismatch: Expected: %h Got: %h (%0t)",
                                data2[15:0], data[15:0], $time);
                        $display("ERROR: Read 4b Mismatch: Expected: %h Got: %h (%0t)",
                                data1[15:0], data3[15:0], $time);
                        error_cnt = error_cnt + 1;
                   end
           end
        if(verbose)     $display("");
 
   end
end
 
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
 
task rst_test;
reg     [31:0]   data;
reg     [31:0]   data1;
 
begin
$display("\n\n");
$display("*****************************************************");
$display("*** RST Test                                      ***");
$display("***                                               ***");
$display("*****************************************************\n");
 
 
        a0.iordy_enable = 0;
        a0.iordy_delay = 0;      // Delay in nS
        a0.init_mem;
 
        data1 = 32'h0000_0080;
        m0.wb_wr1( `CTRL, 4'hf, data1);
        m0.wb_rd1( `CTRL, 4'hf, data );
        if(data != data1 )
           begin
                $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)",
                        data1, data, $time);
                error_cnt = error_cnt + 1;
           end
 
        m0.wb_rd1( `STAT, 4'hf, data );
        m0.wb_rd1( `PCTR, 4'hf, data );
 
        if(ata_rst_ !== 1'b1)
           begin
                $display("ERROR: ATA Reset not deasserted ... (%0t)", $time);
                error_cnt = error_cnt + 1;
           end
        repeat(500)     @(posedge clk);
 
        data1[0] = 1;
        m0.wb_wr1( `CTRL, 4'hf, data1);
        m0.wb_rd1( `CTRL, 4'hf, data );
        if(data != data1 )
           begin
                $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)",
                        data1, data, $time);
                error_cnt = error_cnt + 1;
           end
 
        repeat(100)
           begin
                if(ata_rst_ !== 1'b0)
                   begin
                        $display("ERROR: ATA Reset not asserted ... (%0t)", $time);
                        error_cnt = error_cnt + 1;
                   end
 
                @(posedge clk);
           end
 
        data1[0] = 0;
        m0.wb_wr1( `CTRL, 4'hf, data1);
        m0.wb_rd1( `CTRL, 4'hf, data );
        if(data != data1 )
           begin
                $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)",
                        data1, data, $time);
                error_cnt = error_cnt + 1;
           end
 
        if(ata_rst_ !== 1'b1)
           begin
                $display("ERROR: ATA Reset not deasserted ... (%0t)", $time);
                error_cnt = error_cnt + 1;
           end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
 
task int_test;
reg     [31:0]   data;
reg     [31:0]   data1;
 
begin
$display("\n\n");
$display("*****************************************************");
$display("*** INT Test                                      ***");
$display("***                                               ***");
$display("*****************************************************\n");
 
        a0.iordy_enable = 0;
        a0.iordy_delay = 0;
        a0.init_mem;
 
        data1 = 32'h0000_0080;
        m0.wb_wr1( `CTRL, 4'hf, data1);
        m0.wb_rd1( `CTRL, 4'hf, data );
        if(data != data1 )
           begin
                $display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)",
                        data1, data, $time);
                error_cnt = error_cnt + 1;
           end
 
        // No interrupts at this point
        m0.wb_rd1( `STAT, 4'hf, data );
        data1 = 32'h1000_0000;
        if(data !== data1)
           begin
                $display("ERROR: ATA STATUS mismatch (1), Expected: %0h Got: %0h (%0t)", $time, data1, data);
                error_cnt = error_cnt + 1;
           end
 
        repeat(20)      @(posedge clk);
 
 
        // No interrupts at this point
        m0.wb_rd1( `STAT, 4'hf, data );
        data1 = 32'h1000_0000;
        if(data !== data1)
           begin
                $display("ERROR: ATA STATUS mismatch (2), Expected: %0h Got: %0h (%0t)", $time, data1, data);
                error_cnt = error_cnt + 1;
           end
 
        // Assert Interrup
        ata_intrq_r = 1;
        repeat(10)      @(posedge clk);
        ata_intrq_r = 0;
 
 
        // Check to see if int bit is set
        m0.wb_rd1( `STAT, 4'hf, data );
        data1 = 32'h1000_0001;
        if(data !== data1)
           begin
                $display("ERROR: ATA STATUS mismatch (3), Expected: %0h Got: %0h (%0t)", data1, data, $time);
                error_cnt = error_cnt + 1;
           end
 
        repeat(10)      @(posedge clk);
 
        // Make sure it is not cleared after another read
        m0.wb_rd1( `STAT, 4'hf, data );
        data1 = 32'h1000_0001;
        if(data !== data1)
           begin
                $display("ERROR: ATA STATUS mismatch (4), Expected: %0h Got: %0h (%0t)", data1, data, $time);
                error_cnt = error_cnt + 1;
           end
 
        // Clear interrupt
        data1 = 32'h0000_0000;
        m0.wb_wr1( `STAT, 4'hf, data1 );
 
 
        // Should be cleared now ...
        m0.wb_rd1( `STAT, 4'hf, data );
        data1 = 32'h1000_0000;
        if(data !== data1)
           begin
                $display("ERROR: ATA STATUS mismatch (5), Expected: %0h Got: %0h (%0t)", data1, data, $time);
                error_cnt = error_cnt + 1;
           end
 
        // Check again ....
        m0.wb_rd1( `STAT, 4'hf, data );
        data1 = 32'h1000_0000;
        if(data !== data1)
           begin
                $display("ERROR: ATA STATUS mismatch (6), Expected: %0h Got: %0h (%0t)", data1, data, $time);
                error_cnt = error_cnt + 1;
           end
 
        repeat(100)     @(posedge clk);
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 

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[/] [ata/] [trunk/] [bench/] [verilog/] [tests.v] - Blame information for rev 35

Line No.	Rev	Author	Line
1	16	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Tests Library ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// ////`
10			`//// Downloaded from: http://www.opencores.org/cores/vga_lcd/ ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Rudolf Usselmann ////`
15			`//// rudi@asics.ws ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37
38			`// CVS Log`
39			`//`
40			`// $Id: tests.v,v 1.1 2001-08-16 10:01:05 rudi Exp $`
41			`//`
42			`// $Date: 2001-08-16 10:01:05 $`
43			`// $Revision: 1.1 $`
44			`// $Author: rudi $`
45			`// $Locker: $`
46			`// $State: Exp $`
47			`//`
48			`// Change History:`
49			`// $Log: not supported by cvs2svn $`
50			`//`
51			`//`
52			`//`
53			`//`
54
55
56			`task show_errors;`
57			`begin`
58
59			`$display("\n");`
60			`$display(" +--------------------+");`
61			`$display(" \| Total ERRORS: %0d \|", error_cnt);`
62			`$display(" +--------------------+");`
63
64			`end`
65			`endtask`
66
67
68			`task reg_test;`
69
70			`reg [31:0] data;`
71			`reg [31:0] pattern;`
72			`integer n;`
73
74			`begin`
75			`$display("\n\n");`
76			`$display("*****************************************************");`
77			`$display("* Register Test *");`
78			`$display("*****************************************************\n");`
79
80
81
82			`show_errors;`
83			`$display("*****************************************************");`
84			`$display("* Test DONE ... *");`
85			`$display("*****************************************************\n\n");`
86
87			`end`
88			`endtask`
89
90
91
92			`task io_test1;`
93
94			`reg [31:0] data;`
95			`reg [31:0] data1;`
96			`reg [31:0] data2;`
97			`reg [31:0] data3;`
98			`integer n;`
99			`integer id;`
100			`integer del;`
101			`integer del_max;`
102			`integer iordy_del;`
103
104			`begin`
105			`$display("\n\n");`
106			`$display("*****************************************************");`
107			`$display("* IO Test 1 *");`
108			`$display("* Testing WISHBONE wait state insertion, and *");`
109			`$display("* iordy assertion. *");`
110			`$display("*****************************************************\n");`
111
112			`id = 0;`
113			`del_max = 16;`
114			`for(del=0;del<del_max;del=del+1)`
115			`for(id=0;id<2;id=id+1)`
116			`begin`
117			`if(!verbose)`
118			`$display("*** MODE SELECT: 'iordy' enable: %0d, wb-delay: %0d\n", id, del);`
119
120			`for(iordy_del=0;iordy_del<(id ? 600 : 1);iordy_del=iordy_del+10)`
121			`begin`
122
123			`if(verbose)`
124			`$display("*** MODE SELECT: 'iordy' enable: %0d, wb-delay: %0d iordy_del: %0d\n",`
125			`id, del, iordy_del);`
126
127			`a0.iordy_enable = id;`
128			`a0.iordy_delay = 600; // Delay in nS`
129			`a0.init_mem;`
130
131			`if(id==1) data1 = 32'h0000_0082;`
132			`else data1 = 32'h0000_0080;`
133			m0.wb_wr1( `CTRL, 4'hf, data1);
134			m0.wb_rd1( `CTRL, 4'hf, data );
135			`if(data != data1 )`
136			`begin`
137			`$display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)",`
138			`data1, data, $time);`
139			`error_cnt = error_cnt + 1;`
140			`end`
141
142			m0.wb_rd1( `STAT, 4'hf, data );
143			m0.wb_rd1( `PCTR, 4'hf, data );
144
145			`repeat(10) @(posedge clk);`
146
147			`// Read only Test of ATA registers`
148			`if(verbose) $display(">>> Running Read Only test 1 ... (%0t)", $time);`
149			`for(n=0;n<16;n=n+1)`
150			`begin`
151			m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data );
152			`if(data[15:0] != (n+8) )`
153			`begin`
154			`$display("ERROR: Read 1 Mismatch: Expected: %h Got: %h (%0t)",`
155			`(n+8), data[15:0], $time);`
156			`error_cnt = error_cnt + 1;`
157			`end`
158			`end`
159			`if(verbose) $display("");`
160
161			`// Write Then Read Test of ATA registers`
162			`if(verbose) $display(">>> Running Read/Write test 1 ... (%0t)", $time);`
163
164			`for(n=0;n<16;n=n+1)`
165			`begin`
166			m0.wb_wr1( `ATA_DEV + (n*4) , 4'hf, ~n[15:0] );
167			`if(a0.mem[n+8] != ~n[15:0] )`
168			`begin`
169			`$display("ERROR: Write 1 Mismatch: Expected: %h Got: %h (%0t)",`
170			`~n[15:0], a0.mem[n+8], $time);`
171			`error_cnt = error_cnt + 1;`
172			`end`
173			`end`
174
175			`for(n=0;n<16;n=n+1)`
176			`begin`
177			m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data );
178			`if(data[15:0] != ~n[15:0] )`
179			`begin`
180			`$display("ERROR: Read 2 Mismatch: Expected: %h Got: %h (%0t)",`
181			`~n[15:0], data[15:0], $time);`
182			`error_cnt = error_cnt + 1;`
183			`end`
184			`end`
185			`if(verbose) $display("");`
186
187			`// Write Then Read Test of ATA registers`
188			`if(verbose) $display(">>> Running Read/Write test 2 ... (%0t)", $time);`
189
190			`for(n=0;n<16;n=n+1)`
191			`begin`
192			m0.wb_wr1( `ATA_DEV + (n*4) , 4'hf, n[15:0] );
193			m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data );
194			`if(data[15:0] != n[15:0] )`
195			`begin`
196			`$display("ERROR: Read 3 Mismatch: Expected: %h Got: %h (%0t)",`
197			`n[15:0], data[15:0], $time);`
198			`error_cnt = error_cnt + 1;`
199			`end`
200			`end`
201			`if(verbose) $display("");`
202
203
204			`// Write Then Read Test of ATA registers`
205			`if(verbose) $display(">>> Running Read/Write test 3 ... (%0t)", $time);`
206
207			`for(n=0;n<16;n=n+4)`
208			`begin`
209			m0.wb_wr4( `ATA_DEV + (n*4) , 4'hf, del,
210			`{16'h0, ~n[13:0], 2'h3},`
211			`{16'h0, ~n[13:0], 2'h2},`
212			`{16'h0, ~n[13:0], 2'h1},`
213			`{16'h0, ~n[13:0], 2'h0} );`
214
215			m0.wb_rd4( `ATA_DEV + (n*4) , 4'hf, del, data, data1, data2, data3 );
216
217			`if( (data[15:0] != {~n[13:0], 2'h3}) \|`
218			`(data1[15:0] != {~n[13:0], 2'h2}) \|`
219			`(data2[15:0] != {~n[13:0], 2'h1}) \|`
220			`(data3[15:0] != {~n[13:0], 2'h0}) )`
221			`begin`
222			`$display("ERROR: Read 3 Mismatch: Expected: %h Got: %h (%0t)",`
223			`n[15:0], data[15:0], $time);`
224			`error_cnt = error_cnt + 1;`
225			`end`
226			`end`
227			`if(verbose) $display("");`
228
229
230			`// Write Then Read Test of ATA registers`
231			`if(verbose) $display(">>> Running Read/Write test 4 (RMW) ... (%0t)", $time);`
232
233			`a0.init_mem;`
234
235			`for(n=0;n<16;n=n+1)`
236			`begin`
237			`m0.wr_mem[n] = n[15:0];`
238			m0.wb_rmw( `ATA_DEV + (n*4) , 4'hf, del, 1, 1);
239			`data = m0.rd_mem[n];`
240
241			`data2[15:0] = n[15:0] + 8;`
242
243			`data1 = a0.mem[n+8];`
244			`data3 = n[15:0];`
245
246			`if( (data[15:0] != data2[15:0] ) \|`
247			`(data1[15:0] != data3[15:0]) )`
248			`begin`
249			`$display("ERROR: Read 4a Mismatch: Expected: %h Got: %h (%0t)",`
250			`data2[15:0], data[15:0], $time);`
251			`$display("ERROR: Read 4b Mismatch: Expected: %h Got: %h (%0t)",`
252			`data1[15:0], data3[15:0], $time);`
253			`error_cnt = error_cnt + 1;`
254			`end`
255			`end`
256			`if(verbose) $display("");`
257
258			`end`
259			`end`
260
261			`show_errors;`
262			`$display("*****************************************************");`
263			`$display("* Test DONE ... *");`
264			`$display("*****************************************************\n\n");`
265
266			`end`
267			`endtask`
268
269
270			`task io_test2;`
271
272			`reg [31:0] data;`
273			`reg [31:0] data1;`
274			`reg [31:0] data2;`
275			`reg [31:0] data3;`
276			`integer n;`
277			`integer id;`
278			`integer del;`
279			`integer del_max;`
280			`integer pio_mode;`
281			`integer iordy_del;`
282
283			`begin`
284			`$display("\n\n");`
285			`$display("*****************************************************");`
286			`$display("* IO Test 2 *");`
287			`$display("* Testing PIO Modes, iordy assertion and *");`
288			`$display("* iordy delays. *");`
289			`$display("*****************************************************\n");`
290
291			`id = 0;`
292			`del = 1;`
293			`verbose = 0;`
294			`iordy_del = 0;`
295			`pio_mode=4;`
296
297			`for(pio_mode=0;pio_mode<5;pio_mode=pio_mode+1)`
298			`for(id=0;id<2;id=id+1)`
299			`begin`
300			`if(!verbose)`
301			`$display("*** MODE SELECT: PIO mode: %0d iordy enable: %0d", pio_mode, id);`
302
303			`for(iordy_del=0;iordy_del < (id ? 600 : 1); iordy_del=iordy_del+1)`
304			`begin`
305
306			`if(verbose)`
307			`$display("*** MODE SELECT: PIO mode: %0d, 'iordy' enable: %0d iordy del: %0d\n",`
308			`pio_mode, id, iordy_del );`
309
310			`a0.mode = pio_mode;`
311			`a0.iordy_enable = id;`
312			`a0.iordy_delay = iordy_del; // Delay in nS`
313			`a0.init_mem;`
314
315			`data1 = 32'h0000_0001;`
316			m0.wb_wr1( `CTRL, 4'hf, data1);
317			m0.wb_rd1( `CTRL, 4'hf, data );
318			`if(data != data1 )`
319			`begin`
320			`$display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)",`
321			`data1, data, $time);`
322			`error_cnt = error_cnt + 1;`
323			`end`
324
325			`data1 = 32'h1000_0000;`
326			m0.wb_rd1( `STAT, 4'hf, data );
327			`if(data != data1 )`
328			`begin`
329			`$display("ERROR: STAT Register read Mismatch: Expected: %h Got: %h (%0t)",`
330			`data1, data, $time);`
331			`error_cnt = error_cnt + 1;`
332			`end`
333
334			`case(pio_mode)`
335			`0: data1 = {8'h18, 8'h02, 8'h1c, 8'h04}; // Teoc, T4, T2, T1`
336			`1: data1 = {8'h05, 8'h01, 8'h1c, 8'h02}; // Teoc, T4, T2, T1`
337			`2: data1 = {8'h01, 8'h01, 8'h1c, 8'h00}; // Teoc, T4, T2, T1`
338			`3: data1 = {8'h07, 8'h00, 8'h07, 8'h00}; // Teoc, T4, T2, T1`
339			`4: data1 = {8'h02, 8'h00, 8'h06, 8'h00}; // Teoc, T4, T2, T1`
340			`endcase`
341			m0.wb_wr1( `PCTR, 4'hf, data1);
342			m0.wb_rd1( `PCTR, 4'hf, data );
343			`if(data != data1 )`
344			`begin`
345			`$display("ERROR: PCTR Register write Mismatch: Expected: %h Got: %h (%0t)",`
346			`data1, data, $time);`
347			`error_cnt = error_cnt + 1;`
348			`end`
349
350			`if(id==1) data1 = 32'h0000_0082;`
351			`else data1 = 32'h0000_0080;`
352			m0.wb_wr1( `CTRL, 4'hf, data1);
353			m0.wb_rd1( `CTRL, 4'hf, data );
354			`if(data != data1 )`
355			`begin`
356			`$display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)",`
357			`data1, data, $time);`
358			`error_cnt = error_cnt + 1;`
359			`end`
360
361			`repeat(10) @(posedge clk);`
362
363			`// Read only Test of ATA registers`
364			`if(verbose) $display(">>> Running Read Only test 1 ... (%0t)", $time);`
365			`for(n=0;n<16;n=n+1)`
366			`begin`
367			m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data );
368			`if(data[15:0] != (n+8) )`
369			`begin`
370			`$display("ERROR: Read 1 Mismatch: Expected: %h Got: %h (%0t)",`
371			`(n+8), data[15:0], $time);`
372			`error_cnt = error_cnt + 1;`
373			`end`
374			`end`
375			`if(verbose) $display("");`
376
377			`// Write Then Read Test of ATA registers`
378			`if(verbose) $display(">>> Running Read/Write test 1 ... (%0t)", $time);`
379
380			`for(n=0;n<16;n=n+1)`
381			`begin`
382			m0.wb_wr1( `ATA_DEV + (n*4) , 4'hf, ~n[15:0] );
383			`if(a0.mem[n+8] != ~n[15:0] )`
384			`begin`
385			`$display("ERROR: Write 1 Mismatch: Expected: %h Got: %h (%0t)",`
386			`~n[15:0], a0.mem[n+8], $time);`
387			`error_cnt = error_cnt + 1;`
388			`end`
389			`end`
390
391			`for(n=0;n<16;n=n+1)`
392			`begin`
393			m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data );
394			`if(data[15:0] != ~n[15:0] )`
395			`begin`
396			`$display("ERROR: Read 2 Mismatch: Expected: %h Got: %h (%0t)",`
397			`~n[15:0], data[15:0], $time);`
398			`error_cnt = error_cnt + 1;`
399			`end`
400			`end`
401			`if(verbose) $display("");`
402
403			`// Write Then Read Test of ATA registers`
404			`if(verbose) $display(">>> Running Read/Write test 2 ... (%0t)", $time);`
405
406			`for(n=0;n<16;n=n+1)`
407			`begin`
408			m0.wb_wr1( `ATA_DEV + (n*4) , 4'hf, n[15:0] );
409			m0.wb_rd1( `ATA_DEV + (n*4) , 4'hf, data );
410			`if(data[15:0] != n[15:0] )`
411			`begin`
412			`$display("ERROR: Read 3 Mismatch: Expected: %h Got: %h (%0t)",`
413			`n[15:0], data[15:0], $time);`
414			`error_cnt = error_cnt + 1;`
415			`end`
416			`end`
417			`if(verbose) $display("");`
418
419
420			`// Write Then Read Test of ATA registers`
421			`if(verbose) $display(">>> Running Read/Write test 3 ... (%0t)", $time);`
422
423			`for(n=0;n<16;n=n+4)`
424			`begin`
425			m0.wb_wr4( `ATA_DEV + (n*4) , 4'hf, del,
426			`{16'h0, ~n[13:0], 2'h3},`
427			`{16'h0, ~n[13:0], 2'h2},`
428			`{16'h0, ~n[13:0], 2'h1},`
429			`{16'h0, ~n[13:0], 2'h0} );`
430
431			m0.wb_rd4( `ATA_DEV + (n*4) , 4'hf, del, data, data1, data2, data3 );
432
433			`if( (data[15:0] != {~n[13:0], 2'h3}) \|`
434			`(data1[15:0] != {~n[13:0], 2'h2}) \|`
435			`(data2[15:0] != {~n[13:0], 2'h1}) \|`
436			`(data3[15:0] != {~n[13:0], 2'h0}) )`
437			`begin`
438			`$display("ERROR: Read 3 Mismatch: Expected: %h Got: %h (%0t)",`
439			`n[15:0], data[15:0], $time);`
440			`error_cnt = error_cnt + 1;`
441			`end`
442			`end`
443			`if(verbose) $display("");`
444
445
446			`// Write Then Read Test of ATA registers`
447			`if(verbose) $display(">>> Running Read/Write test 4 (RMW) ... (%0t)", $time);`
448
449			`a0.init_mem;`
450
451			`for(n=0;n<16;n=n+1)`
452			`begin`
453			`m0.wr_mem[n] = n[15:0];`
454			m0.wb_rmw( `ATA_DEV + (n*4) , 4'hf, del, 1, 1);
455			`data = m0.rd_mem[n];`
456
457			`data2[15:0] = n[15:0] + 8;`
458
459			`data1 = a0.mem[n+8];`
460			`data3 = n[15:0];`
461
462			`if( (data[15:0] != data2[15:0] ) \|`
463			`(data1[15:0] != data3[15:0]) )`
464			`begin`
465			`$display("ERROR: Read 4a Mismatch: Expected: %h Got: %h (%0t)",`
466			`data2[15:0], data[15:0], $time);`
467			`$display("ERROR: Read 4b Mismatch: Expected: %h Got: %h (%0t)",`
468			`data1[15:0], data3[15:0], $time);`
469			`error_cnt = error_cnt + 1;`
470			`end`
471			`end`
472			`if(verbose) $display("");`
473
474			`end`
475			`end`
476
477
478			`show_errors;`
479			`$display("*****************************************************");`
480			`$display("* Test DONE ... *");`
481			`$display("*****************************************************\n\n");`
482
483			`end`
484			`endtask`
485
486
487
488			`task rst_test;`
489			`reg [31:0] data;`
490			`reg [31:0] data1;`
491
492			`begin`
493			`$display("\n\n");`
494			`$display("*****************************************************");`
495			`$display("* RST Test *");`
496			`$display("* *");`
497			`$display("*****************************************************\n");`
498
499
500			`a0.iordy_enable = 0;`
501			`a0.iordy_delay = 0; // Delay in nS`
502			`a0.init_mem;`
503
504			`data1 = 32'h0000_0080;`
505			m0.wb_wr1( `CTRL, 4'hf, data1);
506			m0.wb_rd1( `CTRL, 4'hf, data );
507			`if(data != data1 )`
508			`begin`
509			`$display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)",`
510			`data1, data, $time);`
511			`error_cnt = error_cnt + 1;`
512			`end`
513
514			m0.wb_rd1( `STAT, 4'hf, data );
515			m0.wb_rd1( `PCTR, 4'hf, data );
516
517			`if(ata_rst_ !== 1'b1)`
518			`begin`
519			`$display("ERROR: ATA Reset not deasserted ... (%0t)", $time);`
520			`error_cnt = error_cnt + 1;`
521			`end`
522			`repeat(500) @(posedge clk);`
523
524			`data1[0] = 1;`
525			m0.wb_wr1( `CTRL, 4'hf, data1);
526			m0.wb_rd1( `CTRL, 4'hf, data );
527			`if(data != data1 )`
528			`begin`
529			`$display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)",`
530			`data1, data, $time);`
531			`error_cnt = error_cnt + 1;`
532			`end`
533
534			`repeat(100)`
535			`begin`
536			`if(ata_rst_ !== 1'b0)`
537			`begin`
538			`$display("ERROR: ATA Reset not asserted ... (%0t)", $time);`
539			`error_cnt = error_cnt + 1;`
540			`end`
541
542			`@(posedge clk);`
543			`end`
544
545			`data1[0] = 0;`
546			m0.wb_wr1( `CTRL, 4'hf, data1);
547			m0.wb_rd1( `CTRL, 4'hf, data );
548			`if(data != data1 )`
549			`begin`
550			`$display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)",`
551			`data1, data, $time);`
552			`error_cnt = error_cnt + 1;`
553			`end`
554
555			`if(ata_rst_ !== 1'b1)`
556			`begin`
557			`$display("ERROR: ATA Reset not deasserted ... (%0t)", $time);`
558			`error_cnt = error_cnt + 1;`
559			`end`
560
561			`show_errors;`
562			`$display("*****************************************************");`
563			`$display("* Test DONE ... *");`
564			`$display("*****************************************************\n\n");`
565
566			`end`
567			`endtask`
568
569
570
571			`task int_test;`
572			`reg [31:0] data;`
573			`reg [31:0] data1;`
574
575			`begin`
576			`$display("\n\n");`
577			`$display("*****************************************************");`
578			`$display("* INT Test *");`
579			`$display("* *");`
580			`$display("*****************************************************\n");`
581
582			`a0.iordy_enable = 0;`
583			`a0.iordy_delay = 0;`
584			`a0.init_mem;`
585
586			`data1 = 32'h0000_0080;`
587			m0.wb_wr1( `CTRL, 4'hf, data1);
588			m0.wb_rd1( `CTRL, 4'hf, data );
589			`if(data != data1 )`
590			`begin`
591			`$display("ERROR: CTRL Register write Mismatch: Expected: %h Got: %h (%0t)",`
592			`data1, data, $time);`
593			`error_cnt = error_cnt + 1;`
594			`end`
595
596			`// No interrupts at this point`
597			m0.wb_rd1( `STAT, 4'hf, data );
598			`data1 = 32'h1000_0000;`
599			`if(data !== data1)`
600			`begin`
601			`$display("ERROR: ATA STATUS mismatch (1), Expected: %0h Got: %0h (%0t)", $time, data1, data);`
602			`error_cnt = error_cnt + 1;`
603			`end`
604
605			`repeat(20) @(posedge clk);`
606
607
608			`// No interrupts at this point`
609			m0.wb_rd1( `STAT, 4'hf, data );
610			`data1 = 32'h1000_0000;`
611			`if(data !== data1)`
612			`begin`
613			`$display("ERROR: ATA STATUS mismatch (2), Expected: %0h Got: %0h (%0t)", $time, data1, data);`
614			`error_cnt = error_cnt + 1;`
615			`end`
616
617			`// Assert Interrup`
618			`ata_intrq_r = 1;`
619			`repeat(10) @(posedge clk);`
620			`ata_intrq_r = 0;`
621
622
623			`// Check to see if int bit is set`
624			m0.wb_rd1( `STAT, 4'hf, data );
625			`data1 = 32'h1000_0001;`
626			`if(data !== data1)`
627			`begin`
628			`$display("ERROR: ATA STATUS mismatch (3), Expected: %0h Got: %0h (%0t)", data1, data, $time);`
629			`error_cnt = error_cnt + 1;`
630			`end`
631
632			`repeat(10) @(posedge clk);`
633
634			`// Make sure it is not cleared after another read`
635			m0.wb_rd1( `STAT, 4'hf, data );
636			`data1 = 32'h1000_0001;`
637			`if(data !== data1)`
638			`begin`
639			`$display("ERROR: ATA STATUS mismatch (4), Expected: %0h Got: %0h (%0t)", data1, data, $time);`
640			`error_cnt = error_cnt + 1;`
641			`end`
642
643			`// Clear interrupt`
644			`data1 = 32'h0000_0000;`
645			m0.wb_wr1( `STAT, 4'hf, data1 );
646
647
648			`// Should be cleared now ...`
649			m0.wb_rd1( `STAT, 4'hf, data );
650			`data1 = 32'h1000_0000;`
651			`if(data !== data1)`
652			`begin`
653			`$display("ERROR: ATA STATUS mismatch (5), Expected: %0h Got: %0h (%0t)", data1, data, $time);`
654			`error_cnt = error_cnt + 1;`
655			`end`
656
657			`// Check again ....`
658			m0.wb_rd1( `STAT, 4'hf, data );
659			`data1 = 32'h1000_0000;`
660			`if(data !== data1)`
661			`begin`
662			`$display("ERROR: ATA STATUS mismatch (6), Expected: %0h Got: %0h (%0t)", data1, data, $time);`
663			`error_cnt = error_cnt + 1;`
664			`end`
665
666			`repeat(100) @(posedge clk);`
667
668			`show_errors;`
669			`$display("*****************************************************");`
670			`$display("* Test DONE ... *");`
671			`$display("*****************************************************\n\n");`
672
673			`end`
674			`endtask`
675
676