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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  WISHBONE Master Model                                      ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: wb_mast_model.v,v 1.1 2001-08-16 10:01:05 rudi Exp $
//
//  $Date: 2001-08-16 10:01:05 $
//  $Revision: 1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
//
//
//
//                        
 
/*
 
task mem_fill;
 
- Fills local burst read (rd_buf[]) and write(wr_buf[]) buffers with random values.
 
 
task wb_wr1( 32 bit address, 4 bit byte select, 32 bit write data);
 
- Performs a single WISHBONE write
 
 
task wb_wr4( 32 bit address, 4 bit byte select, integer delay,
        32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4);
 
- Performs 4 consecutive WISHBONE writes
- Strobe is deasserted between writes for 'delay' number of cycles
  (This simulates wait state insertion ...)
 
 
task wb_wr_mult( 32 bit address, 4 bit byte select, integer delay,
        integer count);
 
- Simular to wb_wr4, except it pwrforms "count" number of write cycles.
  The data is taken from the internal wr_bub[] memory.
- Strobe is deasserted between writes for 'delay' number of cycles
  (This simulates wait state insertion ...)
 
 
task wb_rmw( 32 bit address, 4 bit byte select, integer delay,
        integer rcount, integer wcount);
 
- This task performs "rcount" read cycles, followed by wcount write cycles.
- read data is placed in to the internal rd_buf[] memory, write data is
  taken from the internal wr_buf[] memory.
- Strobe is deasserted between writes for 'delay' number of cycles
  (This simulates wait state insertion ...)
 
 
task wb_rd1( 32 bit address, 4 bit byte select, 32 bit read data);
 
- Performs a single WISHBONE write
 
 
task wb_rd4( 32 bit address, 4 bit byte select, integer delay,
        32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4);
 
- Performs 4 consecutive WISHBONE reads
- Strobe is deasserted between reads for 'delay' number of cycles
  (This simulates wait state insertion ...)
 
 
task wb_rd_mult( 32 bit address, 4 bit byte select, integer delay,
        integer count);
 
- Simular to wb_rd4, except it pwrforms "count" number of read cycles.
  The data is read in to the internal rd_buf[] memory.
- Strobe is deasserted between reads for 'delay' number of cycles
  (This simulates wait state insertion ...)
 
 
*/
 
 
`include "wb_model_defines.v"
 
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
 
input           clk, rst;
output  [31:0]   adr;
input   [31:0]   din;
output  [31:0]   dout;
output          cyc, stb;
output  [3:0]    sel;
output          we;
input           ack, err, rty;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
parameter mem_size = 4096;
 
reg     [31:0]   adr;
reg     [31:0]   dout;
reg             cyc, stb;
reg     [3:0]    sel;
reg             we;
 
reg     [31:0]   rd_mem[mem_size:0];
reg     [31:0]   wr_mem[mem_size:0];
integer         rd_cnt;
integer         wr_cnt;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
   begin
        adr = 32'hxxxx_xxxx;
        dout = 32'hxxxx_xxxx;
        cyc = 0;
        stb = 0;
        sel = 4'hx;
        we = 1'hx;
        rd_cnt = 0;
        wr_cnt = 0;
        #1;
        $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
   end
 
 
 
task mem_fill;
 
integer n;
begin
rd_cnt = 0;
wr_cnt = 0;
for(n=0;n<mem_size;n=n+1)
   begin
        rd_mem[n] = $random;
        wr_mem[n] = $random;
   end
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 1 Word Task
//
 
task wb_wr1;
input   [31:0]   a;
input   [3:0]    s;
input   [31:0]   d;
 
begin
 
@(posedge clk);
#1;
adr = a;
dout = d;
cyc = 1;
stb = 1;
we=1;
sel = s;
 
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#1;
cyc=0;
stb=0;
adr = 32'hxxxx_xxxx;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 4 Words Task
//
 
task wb_wr4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input   [31:0]   d1;
input   [31:0]   d2;
input   [31:0]   d3;
input   [31:0]   d4;
 
integer         delay;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
sel = s;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
adr = a;
dout = d1;
stb = 1;
we=1;
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
adr = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+4;
dout = d2;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
adr = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+8;
dout = d3;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
adr = 32'hxxxx_xxxx;
 
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
stb=1;
adr = a+12;
dout = d4;
we=1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
#1;
stb=0;
cyc=0;
 
adr = 32'hxxxx_xxxx;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
task wb_wr_mult;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           count;
 
integer         delay;
integer         count;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
 
for(n=0;n<count;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = wr_mem[n + wr_cnt];
        stb = 1;
        we=1;
        sel = s;
        if(n!=0) @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
cyc=0;
adr = 32'hxxxx_xxxx;
 
wr_cnt = wr_cnt + count;
end
endtask
 
 
task wb_rmw;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           rcount;
input           wcount;
 
integer         delay;
integer         rcount;
integer         wcount;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
for(n=0;n<rcount-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        rd_mem[n + rd_cnt] = din;
        //$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
rd_mem[n + rd_cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
#1;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
rd_cnt = rd_cnt + rcount;
 
for(n=0;n<wcount;n=n+1)
   begin
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        adr = a + (n*4);
        dout = wr_mem[n + wr_cnt];
        stb = 1;
        we=1;
        sel = s;
//      if(n!=0)
                @(posedge clk);
        while(~ack & ~err)      @(posedge clk);
        #2;
        stb=0;
        we=1'bx;
        sel = 4'hx;
        dout = 32'hxxxx_xxxx;
        adr = 32'hxxxx_xxxx;
   end
 
cyc=0;
adr = 32'hxxxx_xxxx;
 
wr_cnt = wr_cnt + wcount;
end
endtask
 
 
 
////////////////////////////////////////////////////////////////////
//
// Read 1 Word Task
//
 
task wb_rd1;
input   [31:0]   a;
input   [3:0]    s;
output  [31:0]   d;
 
begin
 
@(posedge clk);
#1;
adr = a;
cyc = 1;
stb = 1;
we  = 0;
sel = s;
 
while(~ack & ~err)      @(posedge clk);
d = din;
#1;
cyc=0;
stb=0;
adr = 32'hxxxx_xxxx;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Read 4 Words Task
//
 
 
task wb_rd4;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
output  [31:0]   d1;
output  [31:0]   d2;
output  [31:0]   d3;
output  [31:0]   d4;
 
integer         delay;
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
adr = a;
stb = 1;
while(~ack & ~err)      @(posedge clk);
d1 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+4;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d2 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
 
adr = a+8;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d3 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
repeat(delay)
   begin
        @(posedge clk);
        #1;
   end
we = 0;
sel = s;
 
adr = a+12;
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
d4 = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
end
endtask
 
 
task wb_rd_mult;
input   [31:0]   a;
input   [3:0]    s;
input           delay;
input           count;
 
integer         delay;
integer         count;
integer         n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay)   @(posedge clk);
 
for(n=0;n<count-1;n=n+1)
   begin
        adr = a + (n*4);
        stb = 1;
        while(~ack & ~err)      @(posedge clk);
        rd_mem[n + rd_cnt] = din;
        #2;
        stb=0;
        we = 1'hx;
        sel = 4'hx;
        adr = 32'hxxxx_xxxx;
        repeat(delay)
           begin
                @(posedge clk);
                #1;
           end
        we = 0;
        sel = s;
   end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err)      @(posedge clk);
rd_mem[n + rd_cnt] = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
rd_cnt = rd_cnt + count;
end
endtask
 
endmodule

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[/] [ata/] [trunk/] [bench/] [verilog/] [wb_mast_model.v] - Blame information for rev 35

Line No.	Rev	Author	Line
1	16	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Master Model ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`/////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// Copyright (C) 2001 Rudolf Usselmann ////`
12			`//// rudi@asics.ws ////`
13			`//// ////`
14			`//// This source file may be used and distributed without ////`
15			`//// restriction provided that this copyright statement is not ////`
16			`//// removed from the file and that any derivative work contains ////`
17			`//// the original copyright notice and the associated disclaimer.////`
18			`//// ////`
19			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
20			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
21			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
22			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
23			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
24			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
25			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
26			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
27			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
28			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
29			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
30			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
31			`//// POSSIBILITY OF SUCH DAMAGE. ////`
32			`//// ////`
33			`/////////////////////////////////////////////////////////////////////`
34
35			`// CVS Log`
36			`//`
37			`// $Id: wb_mast_model.v,v 1.1 2001-08-16 10:01:05 rudi Exp $`
38			`//`
39			`// $Date: 2001-08-16 10:01:05 $`
40			`// $Revision: 1.1 $`
41			`// $Author: rudi $`
42			`// $Locker: $`
43			`// $State: Exp $`
44			`//`
45			`// Change History:`
46			`// $Log: not supported by cvs2svn $`
47			`//`
48			`//`
49			`//`
50			`//`
51			`//`
52
53			`/*`
54
55			`task mem_fill;`
56
57			`- Fills local burst read (rd_buf[]) and write(wr_buf[]) buffers with random values.`
58
59
60			`task wb_wr1( 32 bit address, 4 bit byte select, 32 bit write data);`
61
62			`- Performs a single WISHBONE write`
63
64
65			`task wb_wr4( 32 bit address, 4 bit byte select, integer delay,`
66			`32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4);`
67
68			`- Performs 4 consecutive WISHBONE writes`
69			`- Strobe is deasserted between writes for 'delay' number of cycles`
70			`(This simulates wait state insertion ...)`
71
72
73			`task wb_wr_mult( 32 bit address, 4 bit byte select, integer delay,`
74			`integer count);`
75
76			`- Simular to wb_wr4, except it pwrforms "count" number of write cycles.`
77			`The data is taken from the internal wr_bub[] memory.`
78			`- Strobe is deasserted between writes for 'delay' number of cycles`
79			`(This simulates wait state insertion ...)`
80
81
82			`task wb_rmw( 32 bit address, 4 bit byte select, integer delay,`
83			`integer rcount, integer wcount);`
84
85			`- This task performs "rcount" read cycles, followed by wcount write cycles.`
86			`- read data is placed in to the internal rd_buf[] memory, write data is`
87			`taken from the internal wr_buf[] memory.`
88			`- Strobe is deasserted between writes for 'delay' number of cycles`
89			`(This simulates wait state insertion ...)`
90
91
92			`task wb_rd1( 32 bit address, 4 bit byte select, 32 bit read data);`
93
94			`- Performs a single WISHBONE write`
95
96
97			`task wb_rd4( 32 bit address, 4 bit byte select, integer delay,`
98			`32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4);`
99
100			`- Performs 4 consecutive WISHBONE reads`
101			`- Strobe is deasserted between reads for 'delay' number of cycles`
102			`(This simulates wait state insertion ...)`
103
104
105			`task wb_rd_mult( 32 bit address, 4 bit byte select, integer delay,`
106			`integer count);`
107
108			`- Simular to wb_rd4, except it pwrforms "count" number of read cycles.`
109			`The data is read in to the internal rd_buf[] memory.`
110			`- Strobe is deasserted between reads for 'delay' number of cycles`
111			`(This simulates wait state insertion ...)`
112
113
114			`*/`
115
116
117			`include "wb_model_defines.v"
118
119			`module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);`
120
121			`input clk, rst;`
122			`output [31:0] adr;`
123			`input [31:0] din;`
124			`output [31:0] dout;`
125			`output cyc, stb;`
126			`output [3:0] sel;`
127			`output we;`
128			`input ack, err, rty;`
129
130			`////////////////////////////////////////////////////////////////////`
131			`//`
132			`// Local Wires`
133			`//`
134
135			`parameter mem_size = 4096;`
136
137			`reg [31:0] adr;`
138			`reg [31:0] dout;`
139			`reg cyc, stb;`
140			`reg [3:0] sel;`
141			`reg we;`
142
143			`reg [31:0] rd_mem[mem_size:0];`
144			`reg [31:0] wr_mem[mem_size:0];`
145			`integer rd_cnt;`
146			`integer wr_cnt;`
147
148			`////////////////////////////////////////////////////////////////////`
149			`//`
150			`// Memory Logic`
151			`//`
152
153			`initial`
154			`begin`
155			`adr = 32'hxxxx_xxxx;`
156			`dout = 32'hxxxx_xxxx;`
157			`cyc = 0;`
158			`stb = 0;`
159			`sel = 4'hx;`
160			`we = 1'hx;`
161			`rd_cnt = 0;`
162			`wr_cnt = 0;`
163			`#1;`
164			`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");`
165			`end`
166
167
168
169			`task mem_fill;`
170
171			`integer n;`
172			`begin`
173			`rd_cnt = 0;`
174			`wr_cnt = 0;`
175			`for(n=0;n<mem_size;n=n+1)`
176			`begin`
177			`rd_mem[n] = $random;`
178			`wr_mem[n] = $random;`
179			`end`
180			`end`
181			`endtask`
182
183			`////////////////////////////////////////////////////////////////////`
184			`//`
185			`// Write 1 Word Task`
186			`//`
187
188			`task wb_wr1;`
189			`input [31:0] a;`
190			`input [3:0] s;`
191			`input [31:0] d;`
192
193			`begin`
194
195			`@(posedge clk);`
196			`#1;`
197			`adr = a;`
198			`dout = d;`
199			`cyc = 1;`
200			`stb = 1;`
201			`we=1;`
202			`sel = s;`
203
204			`@(posedge clk);`
205			`while(~ack & ~err) @(posedge clk);`
206			`#1;`
207			`cyc=0;`
208			`stb=0;`
209			`adr = 32'hxxxx_xxxx;`
210			`dout = 32'hxxxx_xxxx;`
211			`we = 1'hx;`
212			`sel = 4'hx;`
213
214			`end`
215			`endtask`
216
217			`////////////////////////////////////////////////////////////////////`
218			`//`
219			`// Write 4 Words Task`
220			`//`
221
222			`task wb_wr4;`
223			`input [31:0] a;`
224			`input [3:0] s;`
225			`input delay;`
226			`input [31:0] d1;`
227			`input [31:0] d2;`
228			`input [31:0] d3;`
229			`input [31:0] d4;`
230
231			`integer delay;`
232
233			`begin`
234
235			`@(posedge clk);`
236			`#1;`
237			`cyc = 1;`
238			`sel = s;`
239
240			`repeat(delay)`
241			`begin`
242			`@(posedge clk);`
243			`#1;`
244			`end`
245			`adr = a;`
246			`dout = d1;`
247			`stb = 1;`
248			`we=1;`
249			`while(~ack & ~err) @(posedge clk);`
250			`#2;`
251			`stb=0;`
252			`we=1'bx;`
253			`dout = 32'hxxxx_xxxx;`
254			`adr = 32'hxxxx_xxxx;`
255
256			`repeat(delay)`
257			`begin`
258			`@(posedge clk);`
259			`#1;`
260			`end`
261			`stb=1;`
262			`adr = a+4;`
263			`dout = d2;`
264			`we=1;`
265			`@(posedge clk);`
266			`while(~ack & ~err) @(posedge clk);`
267			`#2;`
268			`stb=0;`
269			`we=1'bx;`
270			`dout = 32'hxxxx_xxxx;`
271			`adr = 32'hxxxx_xxxx;`
272
273			`repeat(delay)`
274			`begin`
275			`@(posedge clk);`
276			`#1;`
277			`end`
278			`stb=1;`
279			`adr = a+8;`
280			`dout = d3;`
281			`we=1;`
282			`@(posedge clk);`
283			`while(~ack & ~err) @(posedge clk);`
284			`#2;`
285			`stb=0;`
286			`we=1'bx;`
287			`dout = 32'hxxxx_xxxx;`
288			`adr = 32'hxxxx_xxxx;`
289
290			`repeat(delay)`
291			`begin`
292			`@(posedge clk);`
293			`#1;`
294			`end`
295			`stb=1;`
296			`adr = a+12;`
297			`dout = d4;`
298			`we=1;`
299			`@(posedge clk);`
300			`while(~ack & ~err) @(posedge clk);`
301			`#1;`
302			`stb=0;`
303			`cyc=0;`
304
305			`adr = 32'hxxxx_xxxx;`
306			`dout = 32'hxxxx_xxxx;`
307			`we = 1'hx;`
308			`sel = 4'hx;`
309
310			`end`
311			`endtask`
312
313
314			`task wb_wr_mult;`
315			`input [31:0] a;`
316			`input [3:0] s;`
317			`input delay;`
318			`input count;`
319
320			`integer delay;`
321			`integer count;`
322			`integer n;`
323
324			`begin`
325
326			`@(posedge clk);`
327			`#1;`
328			`cyc = 1;`
329
330			`for(n=0;n<count;n=n+1)`
331			`begin`
332			`repeat(delay)`
333			`begin`
334			`@(posedge clk);`
335			`#1;`
336			`end`
337			`adr = a + (n*4);`
338			`dout = wr_mem[n + wr_cnt];`
339			`stb = 1;`
340			`we=1;`
341			`sel = s;`
342			`if(n!=0) @(posedge clk);`
343			`while(~ack & ~err) @(posedge clk);`
344			`#2;`
345			`stb=0;`
346			`we=1'bx;`
347			`sel = 4'hx;`
348			`dout = 32'hxxxx_xxxx;`
349			`adr = 32'hxxxx_xxxx;`
350			`end`
351
352			`cyc=0;`
353			`adr = 32'hxxxx_xxxx;`
354
355			`wr_cnt = wr_cnt + count;`
356			`end`
357			`endtask`
358
359
360			`task wb_rmw;`
361			`input [31:0] a;`
362			`input [3:0] s;`
363			`input delay;`
364			`input rcount;`
365			`input wcount;`
366
367			`integer delay;`
368			`integer rcount;`
369			`integer wcount;`
370			`integer n;`
371
372			`begin`
373
374			`@(posedge clk);`
375			`#1;`
376			`cyc = 1;`
377			`we = 0;`
378			`sel = s;`
379			`repeat(delay) @(posedge clk);`
380
381			`for(n=0;n<rcount-1;n=n+1)`
382			`begin`
383			`adr = a + (n*4);`
384			`stb = 1;`
385			`while(~ack & ~err) @(posedge clk);`
386			`rd_mem[n + rd_cnt] = din;`
387			`//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );`
388			`#2;`
389			`stb=0;`
390			`we = 1'hx;`
391			`sel = 4'hx;`
392			`adr = 32'hxxxx_xxxx;`
393			`repeat(delay)`
394			`begin`
395			`@(posedge clk);`
396			`#1;`
397			`end`
398			`we = 0;`
399			`sel = s;`
400			`end`
401
402			`adr = a+(n*4);`
403			`stb = 1;`
404			`@(posedge clk);`
405			`while(~ack & ~err) @(posedge clk);`
406			`rd_mem[n + rd_cnt] = din;`
407			`//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );`
408			`#1;`
409			`stb=0;`
410			`we = 1'hx;`
411			`sel = 4'hx;`
412			`adr = 32'hxxxx_xxxx;`
413
414			`rd_cnt = rd_cnt + rcount;`
415
416			`for(n=0;n<wcount;n=n+1)`
417			`begin`
418			`repeat(delay)`
419			`begin`
420			`@(posedge clk);`
421			`#1;`
422			`end`
423			`adr = a + (n*4);`
424			`dout = wr_mem[n + wr_cnt];`
425			`stb = 1;`
426			`we=1;`
427			`sel = s;`
428			`// if(n!=0)`
429			`@(posedge clk);`
430			`while(~ack & ~err) @(posedge clk);`
431			`#2;`
432			`stb=0;`
433			`we=1'bx;`
434			`sel = 4'hx;`
435			`dout = 32'hxxxx_xxxx;`
436			`adr = 32'hxxxx_xxxx;`
437			`end`
438
439			`cyc=0;`
440			`adr = 32'hxxxx_xxxx;`
441
442			`wr_cnt = wr_cnt + wcount;`
443			`end`
444			`endtask`
445
446
447
448			`////////////////////////////////////////////////////////////////////`
449			`//`
450			`// Read 1 Word Task`
451			`//`
452
453			`task wb_rd1;`
454			`input [31:0] a;`
455			`input [3:0] s;`
456			`output [31:0] d;`
457
458			`begin`
459
460			`@(posedge clk);`
461			`#1;`
462			`adr = a;`
463			`cyc = 1;`
464			`stb = 1;`
465			`we = 0;`
466			`sel = s;`
467
468			`while(~ack & ~err) @(posedge clk);`
469			`d = din;`
470			`#1;`
471			`cyc=0;`
472			`stb=0;`
473			`adr = 32'hxxxx_xxxx;`
474			`dout = 32'hxxxx_xxxx;`
475			`we = 1'hx;`
476			`sel = 4'hx;`
477
478			`end`
479			`endtask`
480
481
482			`////////////////////////////////////////////////////////////////////`
483			`//`
484			`// Read 4 Words Task`
485			`//`
486
487
488			`task wb_rd4;`
489			`input [31:0] a;`
490			`input [3:0] s;`
491			`input delay;`
492			`output [31:0] d1;`
493			`output [31:0] d2;`
494			`output [31:0] d3;`
495			`output [31:0] d4;`
496
497			`integer delay;`
498			`begin`
499
500			`@(posedge clk);`
501			`#1;`
502			`cyc = 1;`
503			`we = 0;`
504			`sel = s;`
505			`repeat(delay) @(posedge clk);`
506
507			`adr = a;`
508			`stb = 1;`
509			`while(~ack & ~err) @(posedge clk);`
510			`d1 = din;`
511			`#2;`
512			`stb=0;`
513			`we = 1'hx;`
514			`sel = 4'hx;`
515			`adr = 32'hxxxx_xxxx;`
516			`repeat(delay)`
517			`begin`
518			`@(posedge clk);`
519			`#1;`
520			`end`
521			`we = 0;`
522			`sel = s;`
523
524			`adr = a+4;`
525			`stb = 1;`
526			`@(posedge clk);`
527			`while(~ack & ~err) @(posedge clk);`
528			`d2 = din;`
529			`#2;`
530			`stb=0;`
531			`we = 1'hx;`
532			`sel = 4'hx;`
533			`adr = 32'hxxxx_xxxx;`
534			`repeat(delay)`
535			`begin`
536			`@(posedge clk);`
537			`#1;`
538			`end`
539			`we = 0;`
540			`sel = s;`
541
542
543			`adr = a+8;`
544			`stb = 1;`
545			`@(posedge clk);`
546			`while(~ack & ~err) @(posedge clk);`
547			`d3 = din;`
548			`#2;`
549			`stb=0;`
550			`we = 1'hx;`
551			`sel = 4'hx;`
552			`adr = 32'hxxxx_xxxx;`
553			`repeat(delay)`
554			`begin`
555			`@(posedge clk);`
556			`#1;`
557			`end`
558			`we = 0;`
559			`sel = s;`
560
561			`adr = a+12;`
562			`stb = 1;`
563			`@(posedge clk);`
564			`while(~ack & ~err) @(posedge clk);`
565			`d4 = din;`
566			`#1;`
567			`stb=0;`
568			`cyc=0;`
569			`we = 1'hx;`
570			`sel = 4'hx;`
571			`adr = 32'hxxxx_xxxx;`
572			`end`
573			`endtask`
574
575
576			`task wb_rd_mult;`
577			`input [31:0] a;`
578			`input [3:0] s;`
579			`input delay;`
580			`input count;`
581
582			`integer delay;`
583			`integer count;`
584			`integer n;`
585
586			`begin`
587
588			`@(posedge clk);`
589			`#1;`
590			`cyc = 1;`
591			`we = 0;`
592			`sel = s;`
593			`repeat(delay) @(posedge clk);`
594
595			`for(n=0;n<count-1;n=n+1)`
596			`begin`
597			`adr = a + (n*4);`
598			`stb = 1;`
599			`while(~ack & ~err) @(posedge clk);`
600			`rd_mem[n + rd_cnt] = din;`
601			`#2;`
602			`stb=0;`
603			`we = 1'hx;`
604			`sel = 4'hx;`
605			`adr = 32'hxxxx_xxxx;`
606			`repeat(delay)`
607			`begin`
608			`@(posedge clk);`
609			`#1;`
610			`end`
611			`we = 0;`
612			`sel = s;`
613			`end`
614
615			`adr = a+(n*4);`
616			`stb = 1;`
617			`@(posedge clk);`
618			`while(~ack & ~err) @(posedge clk);`
619			`rd_mem[n + rd_cnt] = din;`
620			`#1;`
621			`stb=0;`
622			`cyc=0;`
623			`we = 1'hx;`
624			`sel = 4'hx;`
625			`adr = 32'hxxxx_xxxx;`
626
627			`rd_cnt = rd_cnt + count;`
628			`end`
629			`endtask`
630
631			`endmodule`