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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  OCIDEC-1 ATA/ATAPI-5 Controller                            ////
////  Main Controller                                            ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001, 2002 Richard Herveille                  ////
////                          richard@asics.ws                   ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: atahost_top.v,v 1.6 2002-02-16 10:42:17 rherveille Exp $
//
//  $Date: 2002-02-16 10:42:17 $
//  $Revision: 1.6 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               rev.: 1.0    June 29th, 2001. Initial Verilog release
//               rev.: 1.1    July  3rd, 2001. Changed 'ADR_I[5:2]' into 'ADR_I' on output multiplexor sensitivity list.
//               rev.: 1.2    July  9th, 2001. Fixed register control; registers latched data on all edge cycles instead when selected.
//               rev.: 1.3    July 11th, 2001. Fixed case sensitivity error (nRESET instead of nReset) in "controller" module declaration.
//               rev.: 1.4    July 26th, 2001. Fixed non-blocking assignments.
//               rev.: 1.5  August 15th, 2001. Changed port-names to conform to new OpenCores naming-convention.
//               rev.: 1.6 October 15th, 2001. Removed ata_defines file. Changed define statement to parameter
//
//               $Log: not supported by cvs2svn $
//
//
//
 
/////////////////////////////////////////////////////////////
//
// DeviceType: OCIDEC-1: OpenCores IDE Controller type1
// Features: PIO Compatible Timing
// DeviceID: 0x01
// RevNo : 0x00
//
 
//
// Host signals:
// Reset
// DIOR-                read strobe. The falling edge enables data from device onto DD. The rising edge latches data at the host.
// DIOW-                write strobe. The rising edge latches data from DD into the device.
// DA(2:0)              3bit binary coded adress
// CS0-         select command block registers
// CS1-         select control block registers
 
`include "timescale.v"
 
module atahost_top (wb_clk_i, arst_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
                wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, wb_we_i, wb_inta_o,
                resetn_pad_o, dd_pad_i, dd_pad_o, dd_padoe_o, da_pad_o, cs0n_pad_o,
                cs1n_pad_o, diorn_pad_o, diown_pad_o, iordy_pad_i, intrq_pad_i);
        //
        // Parameter declarations
        //
        parameter ARST_LVL = 1'b0;                    // asynchronous reset level
 
        parameter TWIDTH = 8;                         // counter width
        // PIO mode 0 settings (@100MHz clock)
        parameter PIO_mode0_T1   =  6;                // 70ns
        parameter PIO_mode0_T2   = 28;                // 290ns
        parameter PIO_mode0_T4   =  2;                // 30ns
        parameter PIO_mode0_Teoc = 23;                // 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
 
        //
        // inputs & outputs
        //
 
        // WISHBONE SYSCON signals
        input wb_clk_i;                               // master clock in
        input arst_i;                                 // asynchronous reset
        input wb_rst_i;                               // synchronous reset
 
        // WISHBONE SLAVE signals
        input        wb_cyc_i;                        // valid bus cycle input
        input        wb_stb_i;                        // strobe/core select input
        output       wb_ack_o;                        // strobe acknowledge output
        output       wb_err_o;                        // error output
        input  [6:2] wb_adr_i;                        // A6 = '1' ATA devices selected
                                                      //          A5 = '1' CS1- asserted, '0' CS0- asserted
                                                      //          A4..A2 ATA address lines
                                                      // A6 = '0' ATA controller selected
        input  [31:0] wb_dat_i;                       // Databus in
        output [31:0] wb_dat_o;                       // Databus out
        input  [ 3:0] wb_sel_i;                       // Byte select signals
        input         wb_we_i;                        // Write enable input
        output        wb_inta_o;                      // interrupt request signal
 
        // ATA signals
        output        resetn_pad_o;
        input  [15:0] dd_pad_i;
        output [15:0] dd_pad_o;
        output        dd_padoe_o;
        output [ 2:0] da_pad_o;
        output        cs0n_pad_o;
        output        cs1n_pad_o;
 
        output        diorn_pad_o;
        output        diown_pad_o;
        input         iordy_pad_i;
        input         intrq_pad_i;
 
        //
        // constant declarations
        //
        parameter [3:0] DeviceId = 4'h1;
        parameter [3:0] RevisionNo = 4'h0;
 
        `define ATA_ATA_ADR wb_adr_i[6]
        `define ATA_CTRL_REG 4'b0000
        `define ATA_STAT_REG 4'b0001
        `define ATA_PIO_CMD 4'b0010
 
        //
        // Variable declarations
        //
 
        // registers
        wire        IDEctrl_IDEen, IDEctrl_rst;
        reg  [ 7:0] PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc;
        wire        PIO_cmdport_IORDYen;
        reg  [31:0] CtrlReg; // control register
 
        wire        PIOack;
        wire [15:0] PIOq;
 
        wire [31:0] stat;
 
        wire irq; // ATA bus IRQ signal
 
        /////////////////
        // Module body //
        /////////////////
 
        // generate asynchronous reset level
        // arst_signal is either a wire or a NOT-gate
        wire arst_signal = arst_i ^ ARST_LVL;
 
        // generate bus cycle / address decoder
        wire w_acc  = &wb_sel_i[1:0];                        // word access
        wire dw_acc = &wb_sel_i;                             // double word access
 
        // bus error
        wire berr = `ATA_ATA_ADR ? !w_acc : !dw_acc;
 
        // PIO accesses at least 16bit wide
        wire PIOsel = wb_cyc_i & wb_stb_i & `ATA_ATA_ADR & w_acc;
 
        // CON accesses only 32bit wide
        wire CONsel = wb_cyc_i & wb_stb_i & !(`ATA_ATA_ADR) & dw_acc;
 
        // generate registers
 
        // generate register select signals
        wire sel_ctrl        = CONsel & wb_we_i & (wb_adr_i == `ATA_CTRL_REG);
        wire sel_stat        = CONsel & wb_we_i & (wb_adr_i == `ATA_STAT_REG);
        wire sel_PIO_cmdport = CONsel & wb_we_i & (wb_adr_i == `ATA_PIO_CMD);
        // reserved 0x03-0x0f --
 
        // generate control register
        always@(posedge wb_clk_i or negedge arst_signal)
                if (~arst_signal)
                        begin
                                CtrlReg[31:1] <= 0;
                                CtrlReg[0] <= 1'b1; // set reset bit (ATA-RESETn line)
                        end
                else if (wb_rst_i)
                        begin
                                CtrlReg[31:1] <= 0;
                                CtrlReg[0] <= 1'b1; // set reset bit (ATA-RESETn line)
                        end
                else if (sel_ctrl)
                        CtrlReg <= wb_dat_i;
 
        // assign bits
        assign IDEctrl_IDEen       = CtrlReg[7];
        assign PIO_cmdport_IORDYen = CtrlReg[1];
        assign IDEctrl_rst         = CtrlReg[0];
 
 
        // generate status register clearable bits
        reg dirq, int;
 
        always@(posedge wb_clk_i or negedge arst_signal)
                if (~arst_signal)
                        begin
                                int  <= 1'b0;
                                dirq <= 1'b0;
                        end
                else if (wb_rst_i)
                        begin
                                int  <= 1'b0;
                                dirq <= 1'b0;
                        end
                else
                        begin
                                int  <= (int | (irq & !dirq)) & !(sel_stat & !wb_dat_i[0]);
                                dirq <= irq;
                        end
 
        // assign status bits
        assign stat[31:28] = DeviceId;   // set Device ID
        assign stat[27:24] = RevisionNo; // set revision number
        assign stat[23: 1] = 0;          // --clear unused bits-- 
                                   // Although stat[7]=PIOtip this bit is zero, because it is impossible 
                                   // to read the status register and access the PIO registers at the same time.
        assign stat[0]     = int;
 
 
        // generate PIO compatible / command-port timing register
        always@(posedge wb_clk_i or negedge arst_signal)
                if (~arst_signal)
                        begin
                                PIO_cmdport_T1   <= PIO_mode0_T1;
                                PIO_cmdport_T2   <= PIO_mode0_T2;
                                PIO_cmdport_T4   <= PIO_mode0_T4;
                                PIO_cmdport_Teoc <= PIO_mode0_Teoc;
                        end
                else if (wb_rst_i)
                        begin
                                PIO_cmdport_T1   <= PIO_mode0_T1;
                                PIO_cmdport_T2   <= PIO_mode0_T2;
                                PIO_cmdport_T4   <= PIO_mode0_T4;
                                PIO_cmdport_Teoc <= PIO_mode0_Teoc;
                        end
                else if(sel_PIO_cmdport)
                        begin
                                PIO_cmdport_T1   <= wb_dat_i[ 7: 0];
                                PIO_cmdport_T2   <= wb_dat_i[15: 8];
                                PIO_cmdport_T4   <= wb_dat_i[23:16];
                                PIO_cmdport_Teoc <= wb_dat_i[31:24];
                        end
 
 
        //
        // hookup controller section
        //
        atahost_controller #(TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc)
                u1 (
                        .clk(wb_clk_i),
                        .nReset(arst_signal),
                        .rst(wb_rst_i),
                        .irq(irq),
                        .IDEctrl_rst(IDEctrl_rst),
                        .IDEctrl_IDEen(IDEctrl_IDEen),
                        .PIO_cmdport_T1(PIO_cmdport_T1),
                        .PIO_cmdport_T2(PIO_cmdport_T2),
                        .PIO_cmdport_T4(PIO_cmdport_T4),
                        .PIO_cmdport_Teoc(PIO_cmdport_Teoc),
                        .PIO_cmdport_IORDYen(PIO_cmdport_IORDYen),
                        .PIOreq(PIOsel),
                        .PIOack(PIOack),
                        .PIOa(wb_adr_i[5:2]),
                        .PIOd(wb_dat_i[15:0]),
                        .PIOq(PIOq),
                        .PIOwe(wb_we_i),
                        .RESETn(resetn_pad_o),
                        .DDi(dd_pad_i),
                        .DDo(dd_pad_o),
                        .DDoe(dd_padoe_o),
                        .DA(da_pad_o),
                        .CS0n(cs0n_pad_o),
                        .CS1n(cs1n_pad_o),
                        .DIORn(diorn_pad_o),
                        .DIOWn(diown_pad_o),
                        .IORDY(iordy_pad_i),
                        .INTRQ(intrq_pad_i)
                );
 
        //
        // generate WISHBONE interconnect signals
        //
        reg [31:0] Q;
 
        // generate acknowledge signal
        assign wb_ack_o = PIOack | CONsel;
 
        // generate error signal
        assign wb_err_o = wb_cyc_i & wb_stb_i & berr;
 
        // generate interrupt signal
        assign wb_inta_o = stat[0];
 
        // generate output multiplexor
        always@(wb_adr_i or CtrlReg or stat or PIO_cmdport_T1 or PIO_cmdport_T2 or PIO_cmdport_T4 or PIO_cmdport_Teoc)
                case (wb_adr_i[5:2]) // synopsis full_case parallel_case
                        4'b0000: Q = CtrlReg;
                        4'b0001: Q = stat;
                        4'b0010: Q = {PIO_cmdport_Teoc, PIO_cmdport_T4, PIO_cmdport_T2, PIO_cmdport_T1};
                        default: Q = 0;
                endcase
 
        // assign DAT_O output
        assign wb_dat_o = `ATA_ATA_ADR ? {16'h0000, PIOq} : Q;
 
endmodule
 
 
 
 

Line No.	Rev	Author	Line
1	22	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OCIDEC-1 ATA/ATAPI-5 Controller ////`
4			`//// Main Controller ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`/////////////////////////////////////////////////////////////////////`
11			`//// ////`
12			`//// Copyright (C) 2001, 2002 Richard Herveille ////`
13			`//// richard@asics.ws ////`
14			`//// ////`
15			`//// This source file may be used and distributed without ////`
16			`//// restriction provided that this copyright statement is not ////`
17			`//// removed from the file and that any derivative work contains ////`
18			`//// the original copyright notice and the associated disclaimer.////`
19			`//// ////`
20			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
21			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
22			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
23			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
24			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
25			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
26			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
27			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
28			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
29			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
30			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
31			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
32			`//// POSSIBILITY OF SUCH DAMAGE. ////`
33			`//// ////`
34			`/////////////////////////////////////////////////////////////////////`
35
36			`// CVS Log`
37	15	rherveille	`//`
38	22	rherveille	`// $Id: atahost_top.v,v 1.6 2002-02-16 10:42:17 rherveille Exp $`
39			`//`
40			`// $Date: 2002-02-16 10:42:17 $`
41			`// $Revision: 1.6 $`
42			`// $Author: rherveille $`
43			`// $Locker: $`
44			`// $State: Exp $`
45			`//`
46			`// Change History:`
47			`// rev.: 1.0 June 29th, 2001. Initial Verilog release`
48			`// rev.: 1.1 July 3rd, 2001. Changed 'ADR_I[5:2]' into 'ADR_I' on output multiplexor sensitivity list.`
49			`// rev.: 1.2 July 9th, 2001. Fixed register control; registers latched data on all edge cycles instead when selected.`
50			`// rev.: 1.3 July 11th, 2001. Fixed case sensitivity error (nRESET instead of nReset) in "controller" module declaration.`
51			`// rev.: 1.4 July 26th, 2001. Fixed non-blocking assignments.`
52			`// rev.: 1.5 August 15th, 2001. Changed port-names to conform to new OpenCores naming-convention.`
53			`// rev.: 1.6 October 15th, 2001. Removed ata_defines file. Changed define statement to parameter`
54			`//`
55			`// $Log: not supported by cvs2svn $`
56			`//`
57			`//`
58			`//`
59	15	rherveille
60	22	rherveille	`/////////////////////////////////////////////////////////////`
61			`//`
62	15	rherveille	`// DeviceType: OCIDEC-1: OpenCores IDE Controller type1`
63			`// Features: PIO Compatible Timing`
64			`// DeviceID: 0x01`
65			`// RevNo : 0x00`
66	22	rherveille	`//`
67	15	rherveille
68			`//`
69			`// Host signals:`
70			`// Reset`
71			`// DIOR- read strobe. The falling edge enables data from device onto DD. The rising edge latches data at the host.`
72			`// DIOW- write strobe. The rising edge latches data from DD into the device.`
73			`// DA(2:0) 3bit binary coded adress`
74			`// CS0- select command block registers`
75			`// CS1- select control block registers`
76
77			`include "timescale.v"
78
79	17	rherveille	`module atahost_top (wb_clk_i, arst_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,`
80	15	rherveille	`wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, wb_we_i, wb_inta_o,`
81	18	rherveille	`resetn_pad_o, dd_pad_i, dd_pad_o, dd_padoe_o, da_pad_o, cs0n_pad_o,`
82	17	rherveille	`cs1n_pad_o, diorn_pad_o, diown_pad_o, iordy_pad_i, intrq_pad_i);`
83	15	rherveille	`//`
84			`// Parameter declarations`
85			`//`
86	19	rherveille	`parameter ARST_LVL = 1'b0; // asynchronous reset level`
87
88	15	rherveille	`parameter TWIDTH = 8; // counter width`
89			`// PIO mode 0 settings (@100MHz clock)`
90			`parameter PIO_mode0_T1 = 6; // 70ns`
91			`parameter PIO_mode0_T2 = 28; // 290ns`
92			`parameter PIO_mode0_T4 = 2; // 30ns`
93			`parameter PIO_mode0_Teoc = 23; // 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240`
94
95			`//`
96			`// inputs & outputs`
97			`//`
98
99			`// WISHBONE SYSCON signals`
100			`input wb_clk_i; // master clock in`
101	17	rherveille	`input arst_i; // asynchronous reset`
102			`input wb_rst_i; // synchronous reset`
103	15	rherveille
104			`// WISHBONE SLAVE signals`
105			`input wb_cyc_i; // valid bus cycle input`
106			`input wb_stb_i; // strobe/core select input`
107			`output wb_ack_o; // strobe acknowledge output`
108			`output wb_err_o; // error output`
109			`input [6:2] wb_adr_i; // A6 = '1' ATA devices selected`
110			`// A5 = '1' CS1- asserted, '0' CS0- asserted`
111			`// A4..A2 ATA address lines`
112			`// A6 = '0' ATA controller selected`
113			`input [31:0] wb_dat_i; // Databus in`
114			`output [31:0] wb_dat_o; // Databus out`
115			`input [ 3:0] wb_sel_i; // Byte select signals`
116			`input wb_we_i; // Write enable input`
117			`output wb_inta_o; // interrupt request signal`
118
119			`// ATA signals`
120	17	rherveille	`output resetn_pad_o;`
121			`input [15:0] dd_pad_i;`
122			`output [15:0] dd_pad_o;`
123	18	rherveille	`output dd_padoe_o;`
124	17	rherveille	`output [ 2:0] da_pad_o;`
125			`output cs0n_pad_o;`
126			`output cs1n_pad_o;`
127	15	rherveille
128	17	rherveille	`output diorn_pad_o;`
129			`output diown_pad_o;`
130			`input iordy_pad_i;`
131			`input intrq_pad_i;`
132	15	rherveille
133			`//`
134			`// constant declarations`
135			`//`
136			`parameter [3:0] DeviceId = 4'h1;`
137			`parameter [3:0] RevisionNo = 4'h0;`
138
139			`define ATA_ATA_ADR wb_adr_i[6]
140			`define ATA_CTRL_REG 4'b0000
141			`define ATA_STAT_REG 4'b0001
142			`define ATA_PIO_CMD 4'b0010
143
144			`//`
145			`// Variable declarations`
146			`//`
147
148			`// registers`
149			`wire IDEctrl_IDEen, IDEctrl_rst;`
150			`reg [ 7:0] PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc;`
151			`wire PIO_cmdport_IORDYen;`
152			`reg [31:0] CtrlReg; // control register`
153
154			`wire PIOack;`
155			`wire [15:0] PIOq;`
156
157			`wire [31:0] stat;`
158
159			`wire irq; // ATA bus IRQ signal`
160
161			`/////////////////`
162			`// Module body //`
163			`/////////////////`
164
165	17	rherveille	`// generate asynchronous reset level`
166			`// arst_signal is either a wire or a NOT-gate`
167	19	rherveille	`wire arst_signal = arst_i ^ ARST_LVL;`
168	17	rherveille
169	15	rherveille	`// generate bus cycle / address decoder`
170			`wire w_acc = &wb_sel_i[1:0]; // word access`
171			`wire dw_acc = &wb_sel_i; // double word access`
172
173			`// bus error`
174			wire berr = `ATA_ATA_ADR ? !w_acc : !dw_acc;
175
176			`// PIO accesses at least 16bit wide`
177			wire PIOsel = wb_cyc_i & wb_stb_i & `ATA_ATA_ADR & w_acc;
178
179			`// CON accesses only 32bit wide`
180			wire CONsel = wb_cyc_i & wb_stb_i & !(`ATA_ATA_ADR) & dw_acc;
181
182			`// generate registers`
183
184			`// generate register select signals`
185	17	rherveille	wire sel_ctrl = CONsel & wb_we_i & (wb_adr_i == `ATA_CTRL_REG);
186			wire sel_stat = CONsel & wb_we_i & (wb_adr_i == `ATA_STAT_REG);
187			wire sel_PIO_cmdport = CONsel & wb_we_i & (wb_adr_i == `ATA_PIO_CMD);
188	15	rherveille	`// reserved 0x03-0x0f --`
189
190			`// generate control register`
191	17	rherveille	`always@(posedge wb_clk_i or negedge arst_signal)`
192			`if (~arst_signal)`
193	15	rherveille	`begin`
194			`CtrlReg[31:1] <= 0;`
195			`CtrlReg[0] <= 1'b1; // set reset bit (ATA-RESETn line)`
196			`end`
197			`else if (wb_rst_i)`
198			`begin`
199			`CtrlReg[31:1] <= 0;`
200			`CtrlReg[0] <= 1'b1; // set reset bit (ATA-RESETn line)`
201			`end`
202			`else if (sel_ctrl)`
203			`CtrlReg <= wb_dat_i;`
204
205			`// assign bits`
206			`assign IDEctrl_IDEen = CtrlReg[7];`
207			`assign PIO_cmdport_IORDYen = CtrlReg[1];`
208			`assign IDEctrl_rst = CtrlReg[0];`
209
210
211			`// generate status register clearable bits`
212			`reg dirq, int;`
213
214	17	rherveille	`always@(posedge wb_clk_i or negedge arst_signal)`
215			`if (~arst_signal)`
216	15	rherveille	`begin`
217			`int <= 1'b0;`
218			`dirq <= 1'b0;`
219			`end`
220			`else if (wb_rst_i)`
221			`begin`
222			`int <= 1'b0;`
223			`dirq <= 1'b0;`
224			`end`
225			`else`
226			`begin`
227			`int <= (int \| (irq & !dirq)) & !(sel_stat & !wb_dat_i[0]);`
228			`dirq <= irq;`
229			`end`
230
231			`// assign status bits`
232			`assign stat[31:28] = DeviceId; // set Device ID`
233			`assign stat[27:24] = RevisionNo; // set revision number`
234			`assign stat[23: 1] = 0; // --clear unused bits--`
235			`// Although stat[7]=PIOtip this bit is zero, because it is impossible`
236			`// to read the status register and access the PIO registers at the same time.`
237			`assign stat[0] = int;`
238
239
240			`// generate PIO compatible / command-port timing register`
241	17	rherveille	`always@(posedge wb_clk_i or negedge arst_signal)`
242			`if (~arst_signal)`
243	15	rherveille	`begin`
244			`PIO_cmdport_T1 <= PIO_mode0_T1;`
245			`PIO_cmdport_T2 <= PIO_mode0_T2;`
246			`PIO_cmdport_T4 <= PIO_mode0_T4;`
247			`PIO_cmdport_Teoc <= PIO_mode0_Teoc;`
248			`end`
249			`else if (wb_rst_i)`
250			`begin`
251			`PIO_cmdport_T1 <= PIO_mode0_T1;`
252			`PIO_cmdport_T2 <= PIO_mode0_T2;`
253			`PIO_cmdport_T4 <= PIO_mode0_T4;`
254			`PIO_cmdport_Teoc <= PIO_mode0_Teoc;`
255			`end`
256			`else if(sel_PIO_cmdport)`
257			`begin`
258			`PIO_cmdport_T1 <= wb_dat_i[ 7: 0];`
259			`PIO_cmdport_T2 <= wb_dat_i[15: 8];`
260			`PIO_cmdport_T4 <= wb_dat_i[23:16];`
261			`PIO_cmdport_Teoc <= wb_dat_i[31:24];`
262			`end`
263
264
265			`//`
266			`// hookup controller section`
267			`//`
268			`atahost_controller #(TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc)`
269			`u1 (`
270			`.clk(wb_clk_i),`
271	17	rherveille	`.nReset(arst_signal),`
272	15	rherveille	`.rst(wb_rst_i),`
273			`.irq(irq),`
274			`.IDEctrl_rst(IDEctrl_rst),`
275			`.IDEctrl_IDEen(IDEctrl_IDEen),`
276			`.PIO_cmdport_T1(PIO_cmdport_T1),`
277			`.PIO_cmdport_T2(PIO_cmdport_T2),`
278			`.PIO_cmdport_T4(PIO_cmdport_T4),`
279			`.PIO_cmdport_Teoc(PIO_cmdport_Teoc),`
280			`.PIO_cmdport_IORDYen(PIO_cmdport_IORDYen),`
281			`.PIOreq(PIOsel),`
282			`.PIOack(PIOack),`
283			`.PIOa(wb_adr_i[5:2]),`
284			`.PIOd(wb_dat_i[15:0]),`
285			`.PIOq(PIOq),`
286			`.PIOwe(wb_we_i),`
287	17	rherveille	`.RESETn(resetn_pad_o),`
288			`.DDi(dd_pad_i),`
289			`.DDo(dd_pad_o),`
290	18	rherveille	`.DDoe(dd_padoe_o),`
291	17	rherveille	`.DA(da_pad_o),`
292			`.CS0n(cs0n_pad_o),`
293			`.CS1n(cs1n_pad_o),`
294			`.DIORn(diorn_pad_o),`
295			`.DIOWn(diown_pad_o),`
296			`.IORDY(iordy_pad_i),`
297			`.INTRQ(intrq_pad_i)`
298	15	rherveille	`);`
299
300			`//`
301			`// generate WISHBONE interconnect signals`
302			`//`
303			`reg [31:0] Q;`
304
305			`// generate acknowledge signal`
306			`assign wb_ack_o = PIOack \| CONsel;`
307
308			`// generate error signal`
309			`assign wb_err_o = wb_cyc_i & wb_stb_i & berr;`
310
311			`// generate interrupt signal`
312			`assign wb_inta_o = stat[0];`
313
314			`// generate output multiplexor`
315			`always@(wb_adr_i or CtrlReg or stat or PIO_cmdport_T1 or PIO_cmdport_T2 or PIO_cmdport_T4 or PIO_cmdport_Teoc)`
316			`case (wb_adr_i[5:2]) // synopsis full_case parallel_case`
317			`4'b0000: Q = CtrlReg;`
318			`4'b0001: Q = stat;`
319			`4'b0010: Q = {PIO_cmdport_Teoc, PIO_cmdport_T4, PIO_cmdport_T2, PIO_cmdport_T1};`
320			`default: Q = 0;`
321			`endcase`
322
323			`// assign DAT_O output`
324			assign wb_dat_o = `ATA_ATA_ADR ? {16'h0000, PIOq} : Q;
325
326			`endmodule`
327	17	rherveille
328
329	19	rherveille
330	22	rherveille

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