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-----------------------------
Revision: 1.0
Date: June 28th, 2001
Author: Richard Herveille
- Initial Verilog release (beta)
-----------------------------
 
-----------------------------
Revision: 1.1
Date: June 18th, 2001
Author: Richard Herveille
- Fixed some incomplete port lists and some Verilog related issues.
  Design now completely compiles
-----------------------------
 
-----------------------------
Revision: 1.1a
Date: July 3rd, 2001
Author: Richard Herveille
- Rewrote some sections (controller.v, ata.v). Minor Verilog coding styles issues.
-----------------------------
 
-----------------------------
Revision: 1.2
Date: July 9th, 2001
Author: Richard Herveille
- added 'timescale to all files
- fixed error where control registers latched data on all rising clock edges, instead of
  when addressed.
-----------------------------
 
-----------------------------
Revision: 1.3
Date: July 11th, 2001
Author: Richard Herveille
- Fixed case sensitivity error (nRESET instead of nReset) in "controller" module declaration.
- changed 'ata.v' into 'atahost.v'
- Changed PIOreq & PIOack generation (controller.vhd); made them synchronous
- Changed 'go' & 'igo' generation (pio_tctrl.vhdl).
-----------------------------
 
-----------------------------
Revision: 1.4
Date: July 26th, 2001
Author: Richard Herveille
- Fixed some blocking versus non-blocking statement issues.
-----------------------------
 
-----------------------------
Revision: 1.5
Date: August 15th, 2001.
Author: Richard Herveille
- Changed filenames and top-level port names to be conform new OpenCores conventions
-----------------------------
 

Line No.	Rev	Author	Line
1	14	rherveille	`-----------------------------`
2			`Revision: 1.0`
3			`Date: June 28th, 2001`
4			`Author: Richard Herveille`
5			`- Initial Verilog release (beta)`
6			`-----------------------------`
7
8			`-----------------------------`
9			`Revision: 1.1`
10			`Date: June 18th, 2001`
11			`Author: Richard Herveille`
12			`- Fixed some incomplete port lists and some Verilog related issues.`
13			`Design now completely compiles`
14			`-----------------------------`
15
16			`-----------------------------`
17			`Revision: 1.1a`
18			`Date: July 3rd, 2001`
19			`Author: Richard Herveille`
20			`- Rewrote some sections (controller.v, ata.v). Minor Verilog coding styles issues.`
21			`-----------------------------`
22
23			`-----------------------------`
24			`Revision: 1.2`
25			`Date: July 9th, 2001`
26			`Author: Richard Herveille`
27			`- added 'timescale to all files`
28			`- fixed error where control registers latched data on all rising clock edges, instead of`
29			`when addressed.`
30			`-----------------------------`
31
32			`-----------------------------`
33			`Revision: 1.3`
34			`Date: July 11th, 2001`
35			`Author: Richard Herveille`
36			`- Fixed case sensitivity error (nRESET instead of nReset) in "controller" module declaration.`
37			`- changed 'ata.v' into 'atahost.v'`
38			`- Changed PIOreq & PIOack generation (controller.vhd); made them synchronous`
39			`- Changed 'go' & 'igo' generation (pio_tctrl.vhdl).`
40			`-----------------------------`
41
42			`-----------------------------`
43			`Revision: 1.4`
44			`Date: July 26th, 2001`
45			`Author: Richard Herveille`
46			`- Fixed some blocking versus non-blocking statement issues.`
47			`-----------------------------`
48	15	rherveille
49			`-----------------------------`
50			`Revision: 1.5`
51			`Date: August 15th, 2001.`
52			`Author: Richard Herveille`
53			`- Changed filenames and top-level port names to be conform new OpenCores conventions`
54			`-----------------------------`
55

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[/] [ata/] [trunk/] [rtl/] [verilog/] [ocidec-1/] [revision_history.txt] - Blame information for rev 15