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Revision: 1.0
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Date: June 28th, 2001
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Author: Richard Herveille
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- Initial Verilog release (beta)
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Revision: 1.1
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Date: June 18th, 2001
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Author: Richard Herveille
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- Fixed some incomplete port lists and some Verilog related issues.
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Design now completely compiles
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Revision: 1.1a
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Date: July 3rd, 2001
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Author: Richard Herveille
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- Rewrote some sections (controller.v, ata.v). Minor Verilog coding styles issues.
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Revision: 1.2
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Date: July 9th, 2001
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Author: Richard Herveille
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- added 'timescale to all files
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- fixed error where control registers latched data on all rising clock edges, instead of
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when addressed.
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Revision: 1.3
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Date: July 11th, 2001
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Author: Richard Herveille
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- Fixed case sensitivity error (nRESET instead of nReset) in "controller" module declaration.
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- changed 'ata.v' into 'atahost.v'
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- Changed PIOreq & PIOack generation (controller.vhd); made them synchronous
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- Changed 'go' & 'igo' generation (pio_tctrl.vhdl).
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Revision: 1.4
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Date: July 26th, 2001
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Author: Richard Herveille
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- Fixed some blocking versus non-blocking statement issues.
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Revision: 1.5
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Date: August 15th, 2001.
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Author: Richard Herveille
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- Changed filenames and top-level port names to be conform new OpenCores conventions
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Revision: 1.6
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Date: September 12th, 2001.
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Author: Richard Herveille
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- Made asynchronous input programmable (using atahost_define.v)
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Revision: 1.7
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Date: October 16th, 2001.
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Author: Richard Herveille
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- Changed programmable asynchronous level from define to parameter
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Revision: 1.8
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Date: Februar 16th, 2002.
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Author: Richard Herveille
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- Added disclaimer
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- Added CVS information
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- Changed core for new counter libraries
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- Updated testbench
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Revision: 1.9
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Date: Februar 17th, 2002.
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Author: Richard Herveille
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- moved wishbone interface into 'atahost_wb_slave.v'
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Revision: 1.10
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Date: May 19th, 2002.
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Author: Richard Herveille
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- Fixed a potential bug that forced the core into an unknown state
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when an asynchronous reset was given without a running clock
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