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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  OpenCores ATA/ATAPI-5 Host Controller                      ////
////  ATA/ATAPI-5 PIO Controller (OCIDEC-2)                      ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001, 2002 Richard Herveille                  ////
////                          richard@asics.ws                   ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//
//  CVS Log
//
//  $Id: atahost_controller.v,v 1.2 2002-05-19 06:05:28 rherveille Exp $
//
//  $Date: 2002-05-19 06:05:28 $
//  $Revision: 1.2 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
 
//
// OCIDEC2 supports:    
// -Common Compatible timing access to all connected devices
//      -Separate timing accesses to data port
// -No DMA support
//
 
`include "timescale.v"
 
module atahost_controller (
                clk, nReset, rst, irq, IDEctrl_rst, IDEctrl_IDEen, IDEctrl_FATR0, IDEctrl_FATR1,
                cmdport_T1, cmdport_T2, cmdport_T4, cmdport_Teoc, cmdport_IORDYen,
                dport0_T1, dport0_T2, dport0_T4, dport0_Teoc, dport0_IORDYen,
                dport1_T1, dport1_T2, dport1_T4, dport1_Teoc, dport1_IORDYen,
                PIOreq, PIOack, PIOa, PIOd, PIOq, PIOwe,
                RESETn, DDi, DDo, DDoe, DA, CS0n, CS1n, DIORn, DIOWn, IORDY, INTRQ
        );
 
        //
        // parameters
        //
        parameter TWIDTH = 8;
        parameter PIO_mode0_T1   =  6;             // 70ns
        parameter PIO_mode0_T2   = 28;             // 290ns
        parameter PIO_mode0_T4   =  2;             // 30ns
        parameter PIO_mode0_Teoc = 23;             // 240ns
 
        //
        // inputs & outputs
        //
        input clk;                                 // master clock
        input nReset;                              // asynchronous active low reset
        input rst;                                 // synchronous active high reset
 
        output irq;                                // interrupt request signal
        reg irq;
 
        // control / registers
        input IDEctrl_rst;
        input IDEctrl_IDEen;
        input IDEctrl_FATR0;
        input IDEctrl_FATR1;
 
        input [7:0] cmdport_T1,
                    cmdport_T2,
                    cmdport_T4,
                    cmdport_Teoc;
        input       cmdport_IORDYen;               // PIO command port / non-fast timing
 
        input [7:0] dport0_T1,
                    dport0_T2,
                    dport0_T4,
                    dport0_Teoc;
        input       dport0_IORDYen;                // PIO mode data-port / fast timing device 0
 
        input [7:0] dport1_T1,
                    dport1_T2,
                    dport1_T4,
                    dport1_Teoc;
        input       dport1_IORDYen;                // PIO mode data-port / fast timing device 1
 
        input         PIOreq;                      // PIO transfer request
        output        PIOack;                      // PIO transfer ended
        input  [ 3:0] PIOa;                        // PIO address
        input  [15:0] PIOd;                        // PIO data in
        output [15:0] PIOq;                        // PIO data out
        input         PIOwe;                       // PIO direction bit '1'=write, '0'=read
 
        reg PIOack;
 
        // ATA signals
        output        RESETn;
        input  [15:0] DDi;
        output [15:0] DDo;
        output        DDoe;
        output [ 2:0] DA;
        output        CS0n;
        output        CS1n;
        output        DIORn;
        output        DIOWn;
        input         IORDY;
        input         INTRQ;
 
        reg        RESETn;
        reg [15:0] DDo;
        reg        DDoe;
        reg [ 2:0] DA;
        reg        CS0n;
        reg        CS1n;
        reg        DIORn;
        reg        DIOWn;
 
 
        //
        // signals & variables
        //
        wire PIOdone;                     // PIO timing controller done
 
        // PIO signals
        wire PIOdior, PIOdiow, PIOoe;
 
        // synchronized ATA inputs
        reg sIORDY;
 
        //
        // module body
        //
 
 
        // synchronize incoming signals
        reg cIORDY;                               // capture IORDY
        reg cINTRQ;                               // capture INTRQ
 
        always @(posedge clk)
        begin : synch_incoming
 
                cIORDY <= #1 IORDY;
                cINTRQ <= #1 INTRQ;
 
                sIORDY <= #1 cIORDY;
                irq    <= #1 cINTRQ;
        end
 
        // generate ATA signals
        always @(posedge clk or negedge nReset)
                if (~nReset)
                        begin
                                RESETn <= #1 1'b0;
                                DIORn  <= #1 1'b1;
                                DIOWn  <= #1 1'b1;
                                DA     <= #1 0;
                                CS0n   <= #1 1'b1;
                                CS1n   <= #1 1'b1;
                                DDo    <= #1 0;
                                DDoe   <= #1 1'b0;
                        end
                else if (rst)
                        begin
                                RESETn <= #1 1'b0;
                                DIORn  <= #1 1'b1;
                                DIOWn  <= #1 1'b1;
                                DA     <= #1 0;
                                CS0n   <= #1 1'b1;
                                CS1n   <= #1 1'b1;
                                DDo    <= #1 0;
                                DDoe   <= #1 1'b0;
                        end
                else
                        begin
                                RESETn <= #1 !IDEctrl_rst;
                                DA     <= #1 PIOa[2:0];
                                CS0n   <= #1 !( !PIOa[3] & PIOreq); // CS0 asserted when A(3) = '0'
                                CS1n   <= #1 !(  PIOa[3] & PIOreq); // CS1 asserted when A(3) = '1'
 
                                DDo    <= #1 PIOd;
                                DDoe   <= #1 PIOoe;
                                DIORn  <= #1 !PIOdior;
                                DIOWn  <= #1 !PIOdiow;
                        end
 
        // generate selected device
        reg SelDev;
        always @(posedge clk)
                if (PIOdone & (PIOa == 4'b0110) & PIOwe)
                        SelDev <= #1 PIOd[4];
 
        // generate PIOgo signal
        always @(posedge clk or negedge nReset)
                if (~nReset)
                        begin
                                dPIOreq <= #1 1'b0;
                                PIOgo   <= #1 1'b0;
                        end
                else if (rst)
                        begin
                                dPIOreq <= #1 1'b0;
                                PIOgo   <= #1 1'b0;
                        end
                else
                        begin
                                dPIOreq <= #1 PIOreq & !PIOack;
                                PIOgo   <= #1 (PIOreq & !dPIOreq) & IDEctrl_IDEen;
                        end
 
        //
        // Hookup PIO access controller
        //
        atahost_pio_actrl #(TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc)
                PIO_access_control (
                        .clk(clk),
                        .nReset(nReset),
                        .rst(rst),
                        .IDEctrl_FATR0(IDEctrl_FATR0),
                        .IDEctrl_FATR1(IDEctrl_FATR1),
                        .cmdport_T1(cmdport_T1),
                        .cmdport_T2(cmdport_T2),
                        .cmdport_T4(cmdport_T4),
                        .cmdport_Teoc(cmdport_Teoc),
                        .cmdport_IORDYen(cmdport_IORDYen),
                        .dport0_T1(dport0_T1),
                        .dport0_T2(dport0_T2),
                        .dport0_T4(dport0_T4),
                        .dport0_Teoc(dport0_Teoc),
                        .dport0_IORDYen(dport0_IORDYen),
                        .dport1_T1(dport1_T1),
                        .dport1_T2(dport1_T2),
                        .dport1_T4(dport1_T4),
                        .dport1_Teoc(dport1_Teoc),
                        .dport1_IORDYen(dport1_IORDYen),
                        .SelDev(SelDev),
                        .go(PIOgo),
                        .done(PIOdone),
                        .dir(PIOwe),
                        .a(PIOa),
                        .q(PIOq),
                        .DDi(DDi),
                        .oe(PIOoe),
                        .DIOR(PIOdior),
                        .DIOW(PIOdiow),
                        .IORDY(sIORDY)
                );
 
        always @(posedge clk)
                PIOack <= #1 PIOdone | (PIOreq & !IDEctrl_IDEen); // acknowledge when done or when IDE not enabled (discard request)
 
endmodule

Line No.	Rev	Author	Line
1	24	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OpenCores ATA/ATAPI-5 Host Controller ////`
4			`//// ATA/ATAPI-5 PIO Controller (OCIDEC-2) ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`/////////////////////////////////////////////////////////////////////`
11			`//// ////`
12			`//// Copyright (C) 2001, 2002 Richard Herveille ////`
13			`//// richard@asics.ws ////`
14			`//// ////`
15			`//// This source file may be used and distributed without ////`
16			`//// restriction provided that this copyright statement is not ////`
17			`//// removed from the file and that any derivative work contains ////`
18			`//// the original copyright notice and the associated disclaimer.////`
19			`//// ////`
20			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
21			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
22			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
23			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
24			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
25			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
26			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
27			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
28			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
29			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
30			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
31			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
32			`//// POSSIBILITY OF SUCH DAMAGE. ////`
33			`//// ////`
34			`/////////////////////////////////////////////////////////////////////`
35
36			`//`
37			`// CVS Log`
38			`//`
39	32	rherveille	`// $Id: atahost_controller.v,v 1.2 2002-05-19 06:05:28 rherveille Exp $`
40	24	rherveille	`//`
41	32	rherveille	`// $Date: 2002-05-19 06:05:28 $`
42			`// $Revision: 1.2 $`
43	24	rherveille	`// $Author: rherveille $`
44			`// $Locker: $`
45			`// $State: Exp $`
46			`//`
47			`// Change History:`
48			`// $Log: not supported by cvs2svn $`
49
50			`//`
51			`// OCIDEC2 supports:`
52			`// -Common Compatible timing access to all connected devices`
53			`// -Separate timing accesses to data port`
54			`// -No DMA support`
55			`//`
56
57			`include "timescale.v"
58
59			`module atahost_controller (`
60			`clk, nReset, rst, irq, IDEctrl_rst, IDEctrl_IDEen, IDEctrl_FATR0, IDEctrl_FATR1,`
61			`cmdport_T1, cmdport_T2, cmdport_T4, cmdport_Teoc, cmdport_IORDYen,`
62			`dport0_T1, dport0_T2, dport0_T4, dport0_Teoc, dport0_IORDYen,`
63			`dport1_T1, dport1_T2, dport1_T4, dport1_Teoc, dport1_IORDYen,`
64			`PIOreq, PIOack, PIOa, PIOd, PIOq, PIOwe,`
65			`RESETn, DDi, DDo, DDoe, DA, CS0n, CS1n, DIORn, DIOWn, IORDY, INTRQ`
66			`);`
67
68			`//`
69			`// parameters`
70			`//`
71			`parameter TWIDTH = 8;`
72			`parameter PIO_mode0_T1 = 6; // 70ns`
73			`parameter PIO_mode0_T2 = 28; // 290ns`
74			`parameter PIO_mode0_T4 = 2; // 30ns`
75			`parameter PIO_mode0_Teoc = 23; // 240ns`
76
77			`//`
78			`// inputs & outputs`
79			`//`
80			`input clk; // master clock`
81			`input nReset; // asynchronous active low reset`
82			`input rst; // synchronous active high reset`
83
84			`output irq; // interrupt request signal`
85			`reg irq;`
86
87			`// control / registers`
88			`input IDEctrl_rst;`
89			`input IDEctrl_IDEen;`
90			`input IDEctrl_FATR0;`
91			`input IDEctrl_FATR1;`
92
93			`input [7:0] cmdport_T1,`
94			`cmdport_T2,`
95			`cmdport_T4,`
96			`cmdport_Teoc;`
97			`input cmdport_IORDYen; // PIO command port / non-fast timing`
98
99			`input [7:0] dport0_T1,`
100			`dport0_T2,`
101			`dport0_T4,`
102			`dport0_Teoc;`
103			`input dport0_IORDYen; // PIO mode data-port / fast timing device 0`
104
105			`input [7:0] dport1_T1,`
106			`dport1_T2,`
107			`dport1_T4,`
108			`dport1_Teoc;`
109			`input dport1_IORDYen; // PIO mode data-port / fast timing device 1`
110
111			`input PIOreq; // PIO transfer request`
112			`output PIOack; // PIO transfer ended`
113			`input [ 3:0] PIOa; // PIO address`
114			`input [15:0] PIOd; // PIO data in`
115			`output [15:0] PIOq; // PIO data out`
116			`input PIOwe; // PIO direction bit '1'=write, '0'=read`
117
118			`reg PIOack;`
119
120			`// ATA signals`
121			`output RESETn;`
122			`input [15:0] DDi;`
123			`output [15:0] DDo;`
124			`output DDoe;`
125			`output [ 2:0] DA;`
126			`output CS0n;`
127			`output CS1n;`
128			`output DIORn;`
129			`output DIOWn;`
130			`input IORDY;`
131			`input INTRQ;`
132
133			`reg RESETn;`
134			`reg [15:0] DDo;`
135			`reg DDoe;`
136			`reg [ 2:0] DA;`
137			`reg CS0n;`
138			`reg CS1n;`
139			`reg DIORn;`
140			`reg DIOWn;`
141
142
143			`//`
144			`// signals & variables`
145			`//`
146			`wire PIOdone; // PIO timing controller done`
147
148			`// PIO signals`
149			`wire PIOdior, PIOdiow, PIOoe;`
150
151			`// synchronized ATA inputs`
152			`reg sIORDY;`
153
154			`//`
155			`// module body`
156			`//`
157
158
159			`// synchronize incoming signals`
160			`reg cIORDY; // capture IORDY`
161			`reg cINTRQ; // capture INTRQ`
162
163	32	rherveille	`always @(posedge clk)`
164	24	rherveille	`begin : synch_incoming`
165
166			`cIORDY <= #1 IORDY;`
167			`cINTRQ <= #1 INTRQ;`
168
169			`sIORDY <= #1 cIORDY;`
170			`irq <= #1 cINTRQ;`
171			`end`
172
173			`// generate ATA signals`
174	32	rherveille	`always @(posedge clk or negedge nReset)`
175	24	rherveille	`if (~nReset)`
176			`begin`
177			`RESETn <= #1 1'b0;`
178			`DIORn <= #1 1'b1;`
179			`DIOWn <= #1 1'b1;`
180			`DA <= #1 0;`
181	32	rherveille	`CS0n <= #1 1'b1;`
182			`CS1n <= #1 1'b1;`
183	24	rherveille	`DDo <= #1 0;`
184			`DDoe <= #1 1'b0;`
185			`end`
186			`else if (rst)`
187			`begin`
188			`RESETn <= #1 1'b0;`
189			`DIORn <= #1 1'b1;`
190			`DIOWn <= #1 1'b1;`
191			`DA <= #1 0;`
192	32	rherveille	`CS0n <= #1 1'b1;`
193			`CS1n <= #1 1'b1;`
194	24	rherveille	`DDo <= #1 0;`
195			`DDoe <= #1 1'b0;`
196			`end`
197			`else`
198			`begin`
199			`RESETn <= #1 !IDEctrl_rst;`
200			`DA <= #1 PIOa[2:0];`
201			`CS0n <= #1 !( !PIOa[3] & PIOreq); // CS0 asserted when A(3) = '0'`
202			`CS1n <= #1 !( PIOa[3] & PIOreq); // CS1 asserted when A(3) = '1'`
203
204			`DDo <= #1 PIOd;`
205			`DDoe <= #1 PIOoe;`
206			`DIORn <= #1 !PIOdior;`
207			`DIOWn <= #1 !PIOdiow;`
208			`end`
209
210			`// generate selected device`
211			`reg SelDev;`
212	32	rherveille	`always @(posedge clk)`
213	24	rherveille	`if (PIOdone & (PIOa == 4'b0110) & PIOwe)`
214			`SelDev <= #1 PIOd[4];`
215
216			`// generate PIOgo signal`
217	32	rherveille	`always @(posedge clk or negedge nReset)`
218			`if (~nReset)`
219			`begin`
220			`dPIOreq <= #1 1'b0;`
221			`PIOgo <= #1 1'b0;`
222			`end`
223			`else if (rst)`
224			`begin`
225			`dPIOreq <= #1 1'b0;`
226			`PIOgo <= #1 1'b0;`
227			`end`
228			`else`
229			`begin`
230			`dPIOreq <= #1 PIOreq & !PIOack;`
231			`PIOgo <= #1 (PIOreq & !dPIOreq) & IDEctrl_IDEen;`
232			`end`
233	24	rherveille
234			`//`
235			`// Hookup PIO access controller`
236			`//`
237			`atahost_pio_actrl #(TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc)`
238			`PIO_access_control (`
239			`.clk(clk),`
240			`.nReset(nReset),`
241			`.rst(rst),`
242			`.IDEctrl_FATR0(IDEctrl_FATR0),`
243			`.IDEctrl_FATR1(IDEctrl_FATR1),`
244			`.cmdport_T1(cmdport_T1),`
245			`.cmdport_T2(cmdport_T2),`
246			`.cmdport_T4(cmdport_T4),`
247			`.cmdport_Teoc(cmdport_Teoc),`
248			`.cmdport_IORDYen(cmdport_IORDYen),`
249			`.dport0_T1(dport0_T1),`
250			`.dport0_T2(dport0_T2),`
251			`.dport0_T4(dport0_T4),`
252			`.dport0_Teoc(dport0_Teoc),`
253			`.dport0_IORDYen(dport0_IORDYen),`
254			`.dport1_T1(dport1_T1),`
255			`.dport1_T2(dport1_T2),`
256			`.dport1_T4(dport1_T4),`
257			`.dport1_Teoc(dport1_Teoc),`
258			`.dport1_IORDYen(dport1_IORDYen),`
259			`.SelDev(SelDev),`
260			`.go(PIOgo),`
261			`.done(PIOdone),`
262			`.dir(PIOwe),`
263			`.a(PIOa),`
264			`.q(PIOq),`
265			`.DDi(DDi),`
266			`.oe(PIOoe),`
267			`.DIOR(PIOdior),`
268			`.DIOW(PIOdiow),`
269			`.IORDY(sIORDY)`
270			`);`
271
272	32	rherveille	`always @(posedge clk)`
273	24	rherveille	`PIOack <= #1 PIOdone \| (PIOreq & !IDEctrl_IDEen); // acknowledge when done or when IDE not enabled (discard request)`
274
275			`endmodule`

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