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[/] [ata/] [trunk/] [rtl/] [verilog/] [ocidec-2/] [atahost_pio_tctrl.v] - Blame information for rev 33

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  OpenCores ATA/ATAPI-5 Host Controller                      ////
////  PIO Timing Controller (common for all OCIDEC cores)        ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2001, 2002 Richard Herveille                  ////
////                          richard@asics.ws                   ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: atahost_pio_tctrl.v,v 1.1 2002-02-18 14:26:46 rherveille Exp $
//
//  $Date: 2002-02-18 14:26:46 $
//  $Revision: 1.1 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               Rev. 1.0 June 27th, 2001. Initial Verilog release
//               Rev. 1.1 July  2nd, 2001. Fixed incomplete port list and some Verilog related issues.
//               Rev. 1.2 July 11th, 2001. Changed 'igo' & 'hold_go' generation.
//
//               $Log: not supported by cvs2svn $
//               Revision 1.2  2002/02/16 10:42:17  rherveille
//               Added disclaimer
//               Added CVS information
//               Changed core for new internal counter libraries (synthesis fixes).
//
//
 
 
//
// Timing       PIO mode transfers
//--------------------------------------------
// T0:  cycle time
// T1:  address valid to DIOR-/DIOW-
// T2:  DIOR-/DIOW- pulse width
// T2i: DIOR-/DIOW- recovery time
// T3:  DIOW- data setup
// T4:  DIOW- data hold
// T5:  DIOR- data setup
// T6:  DIOR- data hold
// T9:  address hold from DIOR-/DIOW- negated
// Trd: Read data valid to IORDY asserted
// Ta:  IORDY setup time
// Tb:  IORDY pulse width
//
// Transfer sequence
//--------------------------------
// 1)   set address (DA, CS0-, CS1-)
// 2)   wait for T1
// 3)   assert DIOR-/DIOW-
//         when write action present Data (timing spec. T3 always honored), enable output enable-signal
// 4)   wait for T2
// 5)   check IORDY
//         when not IORDY goto 5
//        when IORDY negate DIOW-/DIOR-, latch data (if read action)
//    when write, hold data for T4, disable output-enable signal
// 6)   wait end_of_cycle_time. This is T2i or T9 or (T0-T1-T2) whichever takes the longest
// 7)   start new cycle
 
`include "timescale.v"
 
module atahost_pio_tctrl(clk, nReset, rst, IORDY_en, T1, T2, T4, Teoc, go, we, oe, done, dstrb, DIOR, DIOW, IORDY);
        // parameter declarations
        parameter TWIDTH = 8;
        parameter PIO_MODE0_T1   =  6;             // 70ns
        parameter PIO_MODE0_T2   = 28;             // 290ns
        parameter PIO_MODE0_T4   =  2;             // 30ns
        parameter PIO_MODE0_Teoc = 23;             // 240ns
 
        // inputs & outputs
        input clk; // master clock
        input nReset; // asynchronous active low reset
        input rst; // synchronous active high reset
 
        // timing & control register settings
        input IORDY_en;          // use IORDY (or not)
        input [TWIDTH-1:0] T1;   // T1 time (in clk-ticks)
        input [TWIDTH-1:0] T2;   // T1 time (in clk-ticks)
        input [TWIDTH-1:0] T4;   // T1 time (in clk-ticks)
        input [TWIDTH-1:0] Teoc; // T1 time (in clk-ticks)
 
        // control signals
        input go; // PIO controller selected (strobe signal)
        input we; // write enable signal. 1'b0 == read, 1'b1 == write
 
        // return signals
        output oe; // output enable signal
        reg oe;
        output done; // finished cycle
        output dstrb; // data strobe, latch data (during read)
        reg dstrb;
 
        // ata signals
        output DIOR; // IOread signal, active high
        reg DIOR;
        output DIOW; // IOwrite signal, active high
        reg DIOW;
        input  IORDY; // IOrDY signal
 
 
        //
        // constant declarations
        //
        // PIO mode 0 settings (@100MHz clock)
        wire [TWIDTH-1:0] T1_m0   = PIO_MODE0_T1;
        wire [TWIDTH-1:0] T2_m0   = PIO_MODE0_T2;
        wire [TWIDTH-1:0] T4_m0   = PIO_MODE0_T4;
        wire [TWIDTH-1:0] Teoc_m0 = PIO_MODE0_Teoc;
 
        //
        // variable declaration
        //
        reg busy, hold_go;
        wire igo;
        wire T1done, T2done, T4done, Teoc_done, IORDY_done;
        reg hT2done;
 
        //
        // module body
        //
 
        // generate internal go strobe
        // strecht go until ready for new cycle
        always@(posedge clk or negedge nReset)
                if (~nReset)
                        begin
                                busy    <= #1 1'b0;
                                hold_go <= #1 1'b0;
                        end
                else if (rst)
                        begin
                                busy    <= #1 1'b0;
                                hold_go <= #1 1'b0;
                        end
                else
                        begin
                                busy    <= #1 (igo | busy) & !Teoc_done;
                                hold_go <= #1 (go | (hold_go & busy)) & !igo;
                        end
 
        assign igo = (go | hold_go) & !busy;
 
        // 1)   hookup T1 counter
        ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T1)
                t1_cnt(
                        .clk(clk),
                        .rst(rst),
                        .nReset(nReset),
                        .cnt_en(1'b1),
                        .go(igo),
                        .d(T1),
                        .q(),
                        .done(T1done)
                );
 
        // 2)   set (and reset) DIOR-/DIOW-, set output-enable when writing to device
        always@(posedge clk or negedge nReset)
                if (~nReset)
                        begin
                                DIOR <= #1 1'b0;
                                DIOW <= #1 1'b0;
                                oe   <= #1 1'b0;
                        end
                else if (rst)
                        begin
                                DIOR <= #1 1'b0;
                                DIOW <= #1 1'b0;
                                oe   <= #1 1'b0;
                        end
                else
                        begin
                                DIOR <= #1 (!we & T1done) | (DIOR & !IORDY_done);
                                DIOW <= #1 ( we & T1done) | (DIOW & !IORDY_done);
                                oe   <= #1 ( (we & igo) | oe) & !T4done;           // negate oe when t4-done
                        end
 
        // 3)   hookup T2 counter
        ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T2)
                t2_cnt(
                        .clk(clk),
                        .rst(rst),
                        .nReset(nReset),
                        .cnt_en(1'b1),
                        .go(T1done),
                        .d(T2),
                        .q(),
                        .done(T2done)
                );
 
        // 4)   check IORDY (if used), generate release_DIOR-/DIOW- signal (ie negate DIOR-/DIOW-)
        // hold T2done
        always@(posedge clk or negedge nReset)
                if (~nReset)
                        hT2done <= #1 1'b0;
                else if (rst)
                        hT2done <= #1 1'b0;
                else
                        hT2done <= #1 (T2done | hT2done) & !IORDY_done;
 
        assign IORDY_done = (T2done | hT2done) & (IORDY | !IORDY_en);
 
        // generate datastrobe, capture data at rising DIOR- edge
        always@(posedge clk)
                dstrb <= #1 IORDY_done;
 
        // hookup data hold counter
        ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T4)
                dhold_cnt(
                        .clk(clk),
                        .rst(rst),
                        .nReset(nReset),
                        .cnt_en(1'b1),
                        .go(IORDY_done),
                        .d(T4),
                        .q(),
                        .done(T4done)
                );
 
        assign done = T4done; // placing done here provides the fastest return possible, 
                        // while still guaranteeing data and address hold-times
 
        // 5)   hookup end_of_cycle counter
        ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_Teoc)
                eoc_cnt(
                        .clk(clk),
                        .rst(rst),
                        .nReset(nReset),
                        .cnt_en(1'b1),
                        .go(IORDY_done),
                        .d(Teoc),
                        .q(),
                        .done(Teoc_done)
                );
 
endmodule

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[/] [ata/] [trunk/] [rtl/] [verilog/] [ocidec-2/] [atahost_pio_tctrl.v] - Blame information for rev 33

Line No.	Rev	Author	Line
1	24	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OpenCores ATA/ATAPI-5 Host Controller ////`
4			`//// PIO Timing Controller (common for all OCIDEC cores) ////`
5			`//// ////`
6			`//// Author: Richard Herveille ////`
7			`//// richard@asics.ws ////`
8			`//// www.asics.ws ////`
9			`//// ////`
10			`/////////////////////////////////////////////////////////////////////`
11			`//// ////`
12			`//// Copyright (C) 2001, 2002 Richard Herveille ////`
13			`//// richard@asics.ws ////`
14			`//// ////`
15			`//// This source file may be used and distributed without ////`
16			`//// restriction provided that this copyright statement is not ////`
17			`//// removed from the file and that any derivative work contains ////`
18			`//// the original copyright notice and the associated disclaimer.////`
19			`//// ////`
20			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
21			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
22			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
23			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
24			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
25			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
26			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
27			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
28			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
29			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
30			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
31			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
32			`//// POSSIBILITY OF SUCH DAMAGE. ////`
33			`//// ////`
34			`/////////////////////////////////////////////////////////////////////`
35
36			`// CVS Log`
37			`//`
38			`// $Id: atahost_pio_tctrl.v,v 1.1 2002-02-18 14:26:46 rherveille Exp $`
39			`//`
40			`// $Date: 2002-02-18 14:26:46 $`
41			`// $Revision: 1.1 $`
42			`// $Author: rherveille $`
43			`// $Locker: $`
44			`// $State: Exp $`
45			`//`
46			`// Change History:`
47			`// Rev. 1.0 June 27th, 2001. Initial Verilog release`
48			`// Rev. 1.1 July 2nd, 2001. Fixed incomplete port list and some Verilog related issues.`
49			`// Rev. 1.2 July 11th, 2001. Changed 'igo' & 'hold_go' generation.`
50			`//`
51			`// $Log: not supported by cvs2svn $`
52			`// Revision 1.2 2002/02/16 10:42:17 rherveille`
53			`// Added disclaimer`
54			`// Added CVS information`
55			`// Changed core for new internal counter libraries (synthesis fixes).`
56			`//`
57			`//`
58
59
60			`//`
61			`// Timing PIO mode transfers`
62			`//--------------------------------------------`
63			`// T0: cycle time`
64			`// T1: address valid to DIOR-/DIOW-`
65			`// T2: DIOR-/DIOW- pulse width`
66			`// T2i: DIOR-/DIOW- recovery time`
67			`// T3: DIOW- data setup`
68			`// T4: DIOW- data hold`
69			`// T5: DIOR- data setup`
70			`// T6: DIOR- data hold`
71			`// T9: address hold from DIOR-/DIOW- negated`
72			`// Trd: Read data valid to IORDY asserted`
73			`// Ta: IORDY setup time`
74			`// Tb: IORDY pulse width`
75			`//`
76			`// Transfer sequence`
77			`//--------------------------------`
78			`// 1) set address (DA, CS0-, CS1-)`
79			`// 2) wait for T1`
80			`// 3) assert DIOR-/DIOW-`
81			`// when write action present Data (timing spec. T3 always honored), enable output enable-signal`
82			`// 4) wait for T2`
83			`// 5) check IORDY`
84			`// when not IORDY goto 5`
85			`// when IORDY negate DIOW-/DIOR-, latch data (if read action)`
86			`// when write, hold data for T4, disable output-enable signal`
87			`// 6) wait end_of_cycle_time. This is T2i or T9 or (T0-T1-T2) whichever takes the longest`
88			`// 7) start new cycle`
89
90			`include "timescale.v"
91
92			`module atahost_pio_tctrl(clk, nReset, rst, IORDY_en, T1, T2, T4, Teoc, go, we, oe, done, dstrb, DIOR, DIOW, IORDY);`
93			`// parameter declarations`
94			`parameter TWIDTH = 8;`
95			`parameter PIO_MODE0_T1 = 6; // 70ns`
96			`parameter PIO_MODE0_T2 = 28; // 290ns`
97			`parameter PIO_MODE0_T4 = 2; // 30ns`
98			`parameter PIO_MODE0_Teoc = 23; // 240ns`
99
100			`// inputs & outputs`
101			`input clk; // master clock`
102			`input nReset; // asynchronous active low reset`
103			`input rst; // synchronous active high reset`
104
105			`// timing & control register settings`
106			`input IORDY_en; // use IORDY (or not)`
107			`input [TWIDTH-1:0] T1; // T1 time (in clk-ticks)`
108			`input [TWIDTH-1:0] T2; // T1 time (in clk-ticks)`
109			`input [TWIDTH-1:0] T4; // T1 time (in clk-ticks)`
110			`input [TWIDTH-1:0] Teoc; // T1 time (in clk-ticks)`
111
112			`// control signals`
113			`input go; // PIO controller selected (strobe signal)`
114			`input we; // write enable signal. 1'b0 == read, 1'b1 == write`
115
116			`// return signals`
117			`output oe; // output enable signal`
118			`reg oe;`
119			`output done; // finished cycle`
120			`output dstrb; // data strobe, latch data (during read)`
121			`reg dstrb;`
122
123			`// ata signals`
124			`output DIOR; // IOread signal, active high`
125			`reg DIOR;`
126			`output DIOW; // IOwrite signal, active high`
127			`reg DIOW;`
128			`input IORDY; // IOrDY signal`
129
130
131			`//`
132			`// constant declarations`
133			`//`
134			`// PIO mode 0 settings (@100MHz clock)`
135			`wire [TWIDTH-1:0] T1_m0 = PIO_MODE0_T1;`
136			`wire [TWIDTH-1:0] T2_m0 = PIO_MODE0_T2;`
137			`wire [TWIDTH-1:0] T4_m0 = PIO_MODE0_T4;`
138			`wire [TWIDTH-1:0] Teoc_m0 = PIO_MODE0_Teoc;`
139
140			`//`
141			`// variable declaration`
142			`//`
143			`reg busy, hold_go;`
144			`wire igo;`
145			`wire T1done, T2done, T4done, Teoc_done, IORDY_done;`
146			`reg hT2done;`
147
148			`//`
149			`// module body`
150			`//`
151
152			`// generate internal go strobe`
153			`// strecht go until ready for new cycle`
154			`always@(posedge clk or negedge nReset)`
155			`if (~nReset)`
156			`begin`
157			`busy <= #1 1'b0;`
158			`hold_go <= #1 1'b0;`
159			`end`
160			`else if (rst)`
161			`begin`
162			`busy <= #1 1'b0;`
163			`hold_go <= #1 1'b0;`
164			`end`
165			`else`
166			`begin`
167			`busy <= #1 (igo \| busy) & !Teoc_done;`
168			`hold_go <= #1 (go \| (hold_go & busy)) & !igo;`
169			`end`
170
171			`assign igo = (go \| hold_go) & !busy;`
172
173			`// 1) hookup T1 counter`
174			`ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T1)`
175			`t1_cnt(`
176			`.clk(clk),`
177			`.rst(rst),`
178			`.nReset(nReset),`
179			`.cnt_en(1'b1),`
180			`.go(igo),`
181			`.d(T1),`
182			`.q(),`
183			`.done(T1done)`
184			`);`
185
186			`// 2) set (and reset) DIOR-/DIOW-, set output-enable when writing to device`
187			`always@(posedge clk or negedge nReset)`
188			`if (~nReset)`
189			`begin`
190			`DIOR <= #1 1'b0;`
191			`DIOW <= #1 1'b0;`
192			`oe <= #1 1'b0;`
193			`end`
194			`else if (rst)`
195			`begin`
196			`DIOR <= #1 1'b0;`
197			`DIOW <= #1 1'b0;`
198			`oe <= #1 1'b0;`
199			`end`
200			`else`
201			`begin`
202			`DIOR <= #1 (!we & T1done) \| (DIOR & !IORDY_done);`
203			`DIOW <= #1 ( we & T1done) \| (DIOW & !IORDY_done);`
204			`oe <= #1 ( (we & igo) \| oe) & !T4done; // negate oe when t4-done`
205			`end`
206
207			`// 3) hookup T2 counter`
208			`ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T2)`
209			`t2_cnt(`
210			`.clk(clk),`
211			`.rst(rst),`
212			`.nReset(nReset),`
213			`.cnt_en(1'b1),`
214			`.go(T1done),`
215			`.d(T2),`
216			`.q(),`
217			`.done(T2done)`
218			`);`
219
220			`// 4) check IORDY (if used), generate release_DIOR-/DIOW- signal (ie negate DIOR-/DIOW-)`
221			`// hold T2done`
222			`always@(posedge clk or negedge nReset)`
223			`if (~nReset)`
224			`hT2done <= #1 1'b0;`
225			`else if (rst)`
226			`hT2done <= #1 1'b0;`
227			`else`
228			`hT2done <= #1 (T2done \| hT2done) & !IORDY_done;`
229
230			`assign IORDY_done = (T2done \| hT2done) & (IORDY \| !IORDY_en);`
231
232			`// generate datastrobe, capture data at rising DIOR- edge`
233			`always@(posedge clk)`
234			`dstrb <= #1 IORDY_done;`
235
236			`// hookup data hold counter`
237			`ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_T4)`
238			`dhold_cnt(`
239			`.clk(clk),`
240			`.rst(rst),`
241			`.nReset(nReset),`
242			`.cnt_en(1'b1),`
243			`.go(IORDY_done),`
244			`.d(T4),`
245			`.q(),`
246			`.done(T4done)`
247			`);`
248
249			`assign done = T4done; // placing done here provides the fastest return possible,`
250			`// while still guaranteeing data and address hold-times`
251
252			`// 5) hookup end_of_cycle counter`
253			`ro_cnt #(TWIDTH, 1'b0, PIO_MODE0_Teoc)`
254			`eoc_cnt(`
255			`.clk(clk),`
256			`.rst(rst),`
257			`.nReset(nReset),`
258			`.cnt_en(1'b1),`
259			`.go(IORDY_done),`
260			`.d(Teoc),`
261			`.q(),`
262			`.done(Teoc_done)`
263			`);`
264
265			`endmodule`