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rherveille |
---------------------------------------------------------------------
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---- ----
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---- OpenCores IDE Controller (OCIDEC-1) ----
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---- PIO Contoller ----
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---- ----
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---- Author: Richard Herveille ----
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---- richard@asics.ws ----
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---- www.asics.ws ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2001, 2002 Richard Herveille ----
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---- richard@asics.ws ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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-- rev.: 1.0 march 18th, 2001
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-- rev.: 1.0a april 12th, 2001. Removed references to records.vhd to make it compatible with freely available VHDL to Verilog converter tools
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-- rev.: 1.1 june 18th, 2001. Changed PIOack generation. Avoid asserting PIOack continuously when IDEen = '0'
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-- rev.: 1.2 june 26th, 2001. Changed dPIOreq generation. Core did not support wishbone burst accesses to ATA-device.
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-- rev.: 1.3 july 11th, 2001. Changed PIOreq & PIOack generation (made them synchronous).
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--
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--
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-- CVS Log
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--
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rherveille |
-- $Id: atahost_controller.vhd,v 1.2 2002-05-19 06:06:48 rherveille Exp $
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rherveille |
--
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rherveille |
-- $Date: 2002-05-19 06:06:48 $
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-- $Revision: 1.2 $
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rherveille |
-- $Author: rherveille $
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-- $Locker: $
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-- $State: Exp $
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--
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-- Change History:
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-- $Log: not supported by cvs2svn $
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--
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-- OCIDEC1 supports:
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-- -Common Compatible timing access to all connected devices
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity atahost_controller is
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generic(
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TWIDTH : natural := 8; -- counter width
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-- PIO mode 0 settings (@100MHz clock)
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PIO_mode0_T1 : natural := 6; -- 70ns
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PIO_mode0_T2 : natural := 28; -- 290ns
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PIO_mode0_T4 : natural := 2; -- 30ns
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PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
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);
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port(
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clk : in std_logic; -- master clock in
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nReset : in std_logic := '1'; -- asynchronous active low reset
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rst : in std_logic := '0'; -- synchronous active high reset
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irq : out std_logic; -- interrupt request signal
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-- control / registers
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IDEctrl_rst,
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IDEctrl_IDEen : in std_logic;
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-- PIO registers
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PIO_cmdport_T1,
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PIO_cmdport_T2,
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PIO_cmdport_T4,
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PIO_cmdport_Teoc : in unsigned(7 downto 0); -- PIO command timing
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PIO_cmdport_IORDYen : in std_logic;
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PIOreq : in std_logic; -- PIO transfer request
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PIOack : buffer std_logic; -- PIO transfer ended
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PIOa : in unsigned(3 downto 0); -- PIO address
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PIOd : in std_logic_vector(15 downto 0); -- PIO data in
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PIOq : out std_logic_vector(15 downto 0); -- PIO data out
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PIOwe : in std_logic; -- PIO direction bit '1'=write, '0'=read
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-- ATA signals
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RESETn : out std_logic;
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DDi : in std_logic_vector(15 downto 0);
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DDo : out std_logic_vector(15 downto 0);
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DDoe : out std_logic;
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DA : out unsigned(2 downto 0);
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CS0n : out std_logic;
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CS1n : out std_logic;
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DIORn : out std_logic;
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DIOWn : out std_logic;
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IORDY : in std_logic;
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INTRQ : in std_logic
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);
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end entity atahost_controller;
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architecture structural of atahost_controller is
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--
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-- Component declarations
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--
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component atahost_pio_tctrl is
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generic(
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TWIDTH : natural := 8; -- counter width
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-- PIO mode 0 settings (@100MHz clock)
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PIO_mode0_T1 : natural := 6; -- 70ns
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PIO_mode0_T2 : natural := 28; -- 290ns
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PIO_mode0_T4 : natural := 2; -- 30ns
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PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
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);
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port(
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clk : in std_logic; -- master clock
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nReset : in std_logic; -- asynchronous active low reset
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rst : in std_logic; -- synchronous active high reset
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-- timing/control register settings
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IORDY_en : in std_logic; -- use IORDY (or not)
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T1 : in unsigned(TWIDTH -1 downto 0); -- T1 time (in clk-ticks)
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T2 : in unsigned(TWIDTH -1 downto 0); -- T2 time (in clk-ticks)
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T4 : in unsigned(TWIDTH -1 downto 0); -- T4 time (in clk-ticks)
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Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time
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-- control signals
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go : in std_logic; -- PIO controller selected (strobe signal)
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we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device
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-- return signals
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oe : buffer std_logic; -- output enable signal
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done : out std_logic; -- finished cycle
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dstrb : out std_logic; -- data strobe, latch data (during read)
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-- ATA signals
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DIOR, -- IOread signal, active high
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DIOW : buffer std_logic; -- IOwrite signal, active high
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IORDY : in std_logic -- IORDY signal
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);
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end component atahost_pio_tctrl;
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--
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-- signals
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--
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signal dPIOreq, PIOgo : std_logic; -- start PIO timing controller
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signal PIOdone : std_logic; -- PIO timing controller done
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-- PIO signals
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signal PIOdior, PIOdiow : std_logic;
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signal PIOoe : std_logic;
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-- Timing settings
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signal dstrb : std_logic;
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signal T1, T2, T4, Teoc : unsigned(TWIDTH -1 downto 0);
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signal IORDYen : std_logic;
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-- synchronized ATA inputs
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signal sIORDY : std_logic;
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begin
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--
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-- synchronize incoming signals
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--
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synch_incoming: block
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signal cIORDY : std_logic; -- capture IORDY
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signal cINTRQ : std_logic; -- capture INTRQ
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begin
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process(clk)
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begin
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if (clk'event and clk = '1') then
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cIORDY <= IORDY;
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cINTRQ <= INTRQ;
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sIORDY <= cIORDY;
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irq <= cINTRQ;
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end if;
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end process;
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end block synch_incoming;
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--
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-- generate ATA signals
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--
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gen_ata_sigs: block
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begin
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-- generate registers for ATA signals
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gen_regs: process(clk, nReset)
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begin
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if (nReset = '0') then
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RESETn <= '0';
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DIORn <= '1';
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DIOWn <= '1';
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DA <= (others => '0');
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CS0n <= '1';
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CS1n <= '1';
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DDo <= (others => '0');
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DDoe <= '0';
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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RESETn <= '0';
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DIORn <= '1';
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DIOWn <= '1';
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DA <= (others => '0');
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CS0n <= '1';
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CS1n <= '1';
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DDo <= (others => '0');
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DDoe <= '0';
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else
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RESETn <= not IDEctrl_rst;
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DA <= PIOa(2 downto 0);
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CS0n <= not (not PIOa(3) and PIOreq); -- CS0 asserted when A(3) = '0'
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CS1n <= not ( PIOa(3) and PIOreq); -- CS1 asserted when A(3) = '1'
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DDo <= PIOd;
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DDoe <= PIOoe;
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DIORn <= not PIOdior;
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DIOWn <= not PIOdiow;
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end if;
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end if;
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end process gen_regs;
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end block gen_ata_sigs;
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--
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--------------------------
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-- PIO transfer control --
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--------------------------
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--
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-- capture ATA data for PIO access
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gen_PIOq: process(clk)
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begin
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if (clk'event and clk = '1') then
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if (dstrb = '1') then
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PIOq <= DDi;
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end if;
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end if;
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end process gen_PIOq;
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-- generate PIOgo signal
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gen_PIOgo: process(clk, nReset)
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begin
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if (nReset = '0') then
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dPIOreq <= '0';
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PIOgo <= '0';
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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dPIOreq <= '0';
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PIOgo <= '0';
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else
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dPIOreq <= PIOreq and not PIOack;
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PIOgo <= (PIOreq and not dPIOreq) and IDEctrl_IDEen;
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end if;
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end
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end process gen_PIOgo;
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-- set Timing signals
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T1 <= PIO_cmdport_T1;
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T2 <= PIO_cmdport_T2;
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T4 <= PIO_cmdport_T4;
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Teoc <= PIO_cmdport_Teoc;
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IORDYen <= PIO_cmdport_IORDYen;
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--
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-- hookup timing controller
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--
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PIO_timing_controller: atahost_pio_tctrl
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generic map (
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TWIDTH => TWIDTH,
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PIO_mode0_T1 => PIO_mode0_T1,
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PIO_mode0_T2 => PIO_mode0_T2,
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PIO_mode0_T4 => PIO_mode0_T4,
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PIO_mode0_Teoc => PIO_mode0_Teoc
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)
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port map (
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clk => clk,
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nReset => nReset,
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rst => rst,
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IORDY_en => IORDYen,
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T1 => T1,
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T2 => T2,
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T4 => T4,
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Teoc => Teoc,
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go => PIOgo,
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we => PIOwe,
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oe => PIOoe,
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done => PIOdone,
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dstrb => dstrb,
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DIOR => PIOdior,
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DIOW => PIOdiow,
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IORDY => sIORDY
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);
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-- generate acknowledge
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gen_ack: process(clk)
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begin
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if (clk'event and clk = '1') then
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PIOack <= PIOdone or (PIOreq and not IDEctrl_IDEen); -- acknowledge when done or when IDE not enabled (discard request)
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end if;
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end process gen_ack;
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end architecture structural;
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