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[/] [ata/] [trunk/] [rtl/] [vhdl/] [ocidec1/] [atahost_controller.vhd] - Blame information for rev 35

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---------------------------------------------------------------------
----                                                             ----
----  OpenCores IDE Controller (OCIDEC-1)                        ----
----  PIO Contoller                                              ----
----                                                             ----
----  Author: Richard Herveille                                  ----
----          richard@asics.ws                                   ----
----          www.asics.ws                                       ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2001, 2002 Richard Herveille                  ----
----                          richard@asics.ws                   ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
---- POSSIBILITY OF SUCH DAMAGE.                                 ----
----                                                             ----
---------------------------------------------------------------------
 
-- rev.: 1.0  march 18th, 2001
-- rev.: 1.0a april 12th, 2001. Removed references to records.vhd to make it compatible with freely available VHDL to Verilog converter tools
-- rev.: 1.1  june  18th, 2001. Changed PIOack generation. Avoid asserting PIOack continuously when IDEen = '0'
-- rev.: 1.2  june  26th, 2001. Changed dPIOreq generation. Core did not support wishbone burst accesses to ATA-device.
-- rev.: 1.3  july  11th, 2001. Changed PIOreq & PIOack generation (made them synchronous). 
--
--
--  CVS Log
--
--  $Id: atahost_controller.vhd,v 1.2 2002-05-19 06:06:48 rherveille Exp $
--
--  $Date: 2002-05-19 06:06:48 $
--  $Revision: 1.2 $
--  $Author: rherveille $
--  $Locker:  $
--  $State: Exp $
--
-- Change History:
--               $Log: not supported by cvs2svn $
--
 
 
-- OCIDEC1 supports:    
-- -Common Compatible timing access to all connected devices
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity atahost_controller is
        generic(
                TWIDTH : natural := 8;                        -- counter width
 
                -- PIO mode 0 settings (@100MHz clock)
                PIO_mode0_T1 : natural := 6;                  -- 70ns
                PIO_mode0_T2 : natural := 28;                 -- 290ns
                PIO_mode0_T4 : natural := 2;                  -- 30ns
                PIO_mode0_Teoc : natural := 23                -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
        );
        port(
                clk : in std_logic;                           -- master clock in
                nReset : in std_logic := '1';                 -- asynchronous active low reset
                rst : in std_logic := '0';                    -- synchronous active high reset
 
                irq : out std_logic;                          -- interrupt request signal
 
                -- control / registers
                IDEctrl_rst,
                IDEctrl_IDEen : in std_logic;
 
                -- PIO registers
                PIO_cmdport_T1,
                PIO_cmdport_T2,
                PIO_cmdport_T4,
                PIO_cmdport_Teoc : in unsigned(7 downto 0);   -- PIO command timing
                PIO_cmdport_IORDYen : in std_logic;
 
                PIOreq : in std_logic;                        -- PIO transfer request
                PIOack : buffer std_logic;                    -- PIO transfer ended
                PIOa   : in unsigned(3 downto 0);             -- PIO address
                PIOd   : in std_logic_vector(15 downto 0);    -- PIO data in
                PIOq   : out std_logic_vector(15 downto 0);   -- PIO data out
                PIOwe  : in std_logic;                        -- PIO direction bit '1'=write, '0'=read
 
                -- ATA signals
                RESETn : out std_logic;
                DDi      : in std_logic_vector(15 downto 0);
                DDo    : out std_logic_vector(15 downto 0);
                DDoe   : out std_logic;
                DA     : out unsigned(2 downto 0);
                CS0n   : out std_logic;
                CS1n   : out std_logic;
 
                DIORn   : out std_logic;
                DIOWn   : out std_logic;
                IORDY   : in std_logic;
                INTRQ   : in std_logic
        );
end entity atahost_controller;
 
architecture structural of atahost_controller is
        --
        -- Component declarations
        --
        component atahost_pio_tctrl is
        generic(
                TWIDTH : natural := 8;                   -- counter width
 
                -- PIO mode 0 settings (@100MHz clock)
                PIO_mode0_T1 : natural := 6;             -- 70ns
                PIO_mode0_T2 : natural := 28;            -- 290ns
                PIO_mode0_T4 : natural := 2;             -- 30ns
                PIO_mode0_Teoc : natural := 23           -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
        );
        port(
                clk : in std_logic;                      -- master clock
                nReset : in std_logic;                   -- asynchronous active low reset
                rst : in std_logic;                      -- synchronous active high reset
 
                -- timing/control register settings
                IORDY_en : in std_logic;                 -- use IORDY (or not)
                T1 : in unsigned(TWIDTH -1 downto 0);    -- T1 time (in clk-ticks)
                T2 : in unsigned(TWIDTH -1 downto 0);    -- T2 time (in clk-ticks)
                T4 : in unsigned(TWIDTH -1 downto 0);    -- T4 time (in clk-ticks)
                Teoc : in unsigned(TWIDTH -1 downto 0);  -- end of cycle time
 
                -- control signals
                go : in std_logic;                       -- PIO controller selected (strobe signal)
                we : in std_logic;                       -- write enable signal. '0'=read from device, '1'=write to device
 
                -- return signals
                oe :  buffer std_logic;                  -- output enable signal
                done : out std_logic;                    -- finished cycle
                dstrb : out std_logic;                   -- data strobe, latch data (during read)
 
                -- ATA signals
                DIOR,                                    -- IOread signal, active high
                DIOW : buffer std_logic;                 -- IOwrite signal, active high
                IORDY : in std_logic                     -- IORDY signal
        );
        end component atahost_pio_tctrl;
 
        --
        -- signals
        --
        signal dPIOreq, PIOgo : std_logic;              -- start PIO timing controller
        signal PIOdone : std_logic;                     -- PIO timing controller done
 
        -- PIO signals
        signal PIOdior, PIOdiow : std_logic;
        signal PIOoe : std_logic;
 
        -- Timing settings
        signal dstrb : std_logic;
        signal T1, T2, T4, Teoc : unsigned(TWIDTH -1 downto 0);
        signal IORDYen : std_logic;
 
        -- synchronized ATA inputs
        signal sIORDY : std_logic;
 
begin
 
        --
        -- synchronize incoming signals
        --
        synch_incoming: block
                signal cIORDY : std_logic;                   -- capture IORDY
                signal cINTRQ : std_logic;                   -- capture INTRQ
        begin
                process(clk)
                begin
                        if (clk'event and clk = '1') then
                                cIORDY <= IORDY;
                                cINTRQ <= INTRQ;
 
                                sIORDY <= cIORDY;
                                irq <= cINTRQ;
                        end if;
                end process;
        end block synch_incoming;
 
        --
        -- generate ATA signals
        --
        gen_ata_sigs: block
        begin
                -- generate registers for ATA signals
                gen_regs: process(clk, nReset)
                begin
                        if (nReset = '0') then
                                RESETn <= '0';
                                DIORn  <= '1';
                                DIOWn  <= '1';
                                DA     <= (others => '0');
                                CS0n    <= '1';
                                CS1n      <= '1';
                                DDo    <= (others => '0');
                                DDoe   <= '0';
                        elsif (clk'event and clk = '1') then
                                if (rst = '1') then
                                        RESETn <= '0';
                                        DIORn  <= '1';
                                        DIOWn  <= '1';
                                        DA     <= (others => '0');
                                        CS0n      <= '1';
                                        CS1n      <= '1';
                                        DDo    <= (others => '0');
                                        DDoe   <= '0';
                                else
                                        RESETn <= not IDEctrl_rst;
                                        DA     <= PIOa(2 downto 0);
                                        CS0n      <= not (not PIOa(3) and PIOreq); -- CS0 asserted when A(3) = '0'
                                        CS1n      <= not (    PIOa(3) and PIOreq); -- CS1 asserted when A(3) = '1'
 
                                        DDo    <= PIOd;
                                        DDoe   <= PIOoe;
                                        DIORn  <= not PIOdior;
                                        DIOWn  <= not PIOdiow;
                                end if;
                        end if;
                end process gen_regs;
        end block gen_ata_sigs;
 
 
        --
        --------------------------
        -- PIO transfer control --
        --------------------------
        --
        -- capture ATA data for PIO access
        gen_PIOq: process(clk)
        begin
                if (clk'event and clk = '1') then
                        if (dstrb = '1') then
                                PIOq <= DDi;
                        end if;
                end if;
        end process gen_PIOq;
 
        -- generate PIOgo signal
        gen_PIOgo: process(clk, nReset)
        begin
                if (nReset = '0') then
                        dPIOreq <= '0';
                        PIOgo   <= '0';
                elsif (clk'event and clk = '1') then
                        if (rst = '1') then
                                dPIOreq <= '0';
                                PIOgo   <= '0';
                        else
                                dPIOreq <= PIOreq and not PIOack;
                                PIOgo   <= (PIOreq and not dPIOreq) and IDEctrl_IDEen;
                        end if;
        end
        end process gen_PIOgo;
 
        -- set Timing signals
        T1      <= PIO_cmdport_T1;
        T2      <= PIO_cmdport_T2;
        T4      <= PIO_cmdport_T4;
        Teoc    <= PIO_cmdport_Teoc;
        IORDYen <= PIO_cmdport_IORDYen;
 
        --
        -- hookup timing controller
        --
        PIO_timing_controller: atahost_pio_tctrl
                generic map (
                        TWIDTH         => TWIDTH,
                        PIO_mode0_T1   => PIO_mode0_T1,
                        PIO_mode0_T2   => PIO_mode0_T2,
                        PIO_mode0_T4   => PIO_mode0_T4,
                        PIO_mode0_Teoc => PIO_mode0_Teoc
                )
                port map (
                        clk      => clk,
                        nReset   => nReset,
                        rst      => rst,
                        IORDY_en => IORDYen,
                        T1       => T1,
                        T2       => T2,
                        T4       => T4,
                        Teoc     => Teoc,
                        go       => PIOgo,
                        we       => PIOwe,
                        oe       => PIOoe,
                        done     => PIOdone,
                        dstrb    => dstrb,
                        DIOR     => PIOdior,
                        DIOW     => PIOdiow,
                        IORDY    => sIORDY
                );
 
        -- generate acknowledge
        gen_ack: process(clk)
        begin
                if (clk'event and clk = '1') then
                        PIOack <= PIOdone or (PIOreq and not IDEctrl_IDEen); -- acknowledge when done or when IDE not enabled (discard request)
                end if;
        end process gen_ack;
end architecture structural;
 

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[/] [ata/] [trunk/] [rtl/] [vhdl/] [ocidec1/] [atahost_controller.vhd] - Blame information for rev 35

Line No.	Rev	Author	Line
1	25	rherveille	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- OpenCores IDE Controller (OCIDEC-1) ----`
4			`---- PIO Contoller ----`
5			`---- ----`
6			`---- Author: Richard Herveille ----`
7			`---- richard@asics.ws ----`
8			`---- www.asics.ws ----`
9			`---- ----`
10			`---------------------------------------------------------------------`
11			`---- ----`
12			`---- Copyright (C) 2001, 2002 Richard Herveille ----`
13			`---- richard@asics.ws ----`
14			`---- ----`
15			`---- This source file may be used and distributed without ----`
16			`---- restriction provided that this copyright statement is not ----`
17			`---- removed from the file and that any derivative work contains ----`
18			`---- the original copyright notice and the associated disclaimer.----`
19			`---- ----`
20			---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
21			`---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----`
22			`---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----`
23			`---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----`
24			`---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
25			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----`
26			`---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----`
27			`---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----`
28			`---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----`
29			`---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
30			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----`
31			`---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----`
32			`---- POSSIBILITY OF SUCH DAMAGE. ----`
33			`---- ----`
34			`---------------------------------------------------------------------`
35
36			`-- rev.: 1.0 march 18th, 2001`
37			`-- rev.: 1.0a april 12th, 2001. Removed references to records.vhd to make it compatible with freely available VHDL to Verilog converter tools`
38			`-- rev.: 1.1 june 18th, 2001. Changed PIOack generation. Avoid asserting PIOack continuously when IDEen = '0'`
39			`-- rev.: 1.2 june 26th, 2001. Changed dPIOreq generation. Core did not support wishbone burst accesses to ATA-device.`
40			`-- rev.: 1.3 july 11th, 2001. Changed PIOreq & PIOack generation (made them synchronous).`
41			`--`
42			`--`
43			`-- CVS Log`
44			`--`
45	32	rherveille	`-- $Id: atahost_controller.vhd,v 1.2 2002-05-19 06:06:48 rherveille Exp $`
46	25	rherveille	`--`
47	32	rherveille	`-- $Date: 2002-05-19 06:06:48 $`
48			`-- $Revision: 1.2 $`
49	25	rherveille	`-- $Author: rherveille $`
50			`-- $Locker: $`
51			`-- $State: Exp $`
52			`--`
53			`-- Change History:`
54			`-- $Log: not supported by cvs2svn $`
55			`--`
56
57
58			`-- OCIDEC1 supports:`
59			`-- -Common Compatible timing access to all connected devices`
60			`--`
61
62			`library ieee;`
63			`use ieee.std_logic_1164.all;`
64			`use ieee.std_logic_arith.all;`
65
66			`entity atahost_controller is`
67			`generic(`
68			`TWIDTH : natural := 8; -- counter width`
69
70			`-- PIO mode 0 settings (@100MHz clock)`
71			`PIO_mode0_T1 : natural := 6; -- 70ns`
72			`PIO_mode0_T2 : natural := 28; -- 290ns`
73			`PIO_mode0_T4 : natural := 2; -- 30ns`
74			`PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240`
75			`);`
76			`port(`
77			`clk : in std_logic; -- master clock in`
78			`nReset : in std_logic := '1'; -- asynchronous active low reset`
79			`rst : in std_logic := '0'; -- synchronous active high reset`
80
81			`irq : out std_logic; -- interrupt request signal`
82
83			`-- control / registers`
84			`IDEctrl_rst,`
85			`IDEctrl_IDEen : in std_logic;`
86
87			`-- PIO registers`
88			`PIO_cmdport_T1,`
89			`PIO_cmdport_T2,`
90			`PIO_cmdport_T4,`
91			`PIO_cmdport_Teoc : in unsigned(7 downto 0); -- PIO command timing`
92			`PIO_cmdport_IORDYen : in std_logic;`
93
94			`PIOreq : in std_logic; -- PIO transfer request`
95			`PIOack : buffer std_logic; -- PIO transfer ended`
96			`PIOa : in unsigned(3 downto 0); -- PIO address`
97			`PIOd : in std_logic_vector(15 downto 0); -- PIO data in`
98			`PIOq : out std_logic_vector(15 downto 0); -- PIO data out`
99			`PIOwe : in std_logic; -- PIO direction bit '1'=write, '0'=read`
100
101			`-- ATA signals`
102			`RESETn : out std_logic;`
103			`DDi : in std_logic_vector(15 downto 0);`
104			`DDo : out std_logic_vector(15 downto 0);`
105			`DDoe : out std_logic;`
106			`DA : out unsigned(2 downto 0);`
107			`CS0n : out std_logic;`
108			`CS1n : out std_logic;`
109
110			`DIORn : out std_logic;`
111			`DIOWn : out std_logic;`
112			`IORDY : in std_logic;`
113			`INTRQ : in std_logic`
114			`);`
115			`end entity atahost_controller;`
116
117			`architecture structural of atahost_controller is`
118			`--`
119			`-- Component declarations`
120			`--`
121			`component atahost_pio_tctrl is`
122			`generic(`
123			`TWIDTH : natural := 8; -- counter width`
124
125			`-- PIO mode 0 settings (@100MHz clock)`
126			`PIO_mode0_T1 : natural := 6; -- 70ns`
127			`PIO_mode0_T2 : natural := 28; -- 290ns`
128			`PIO_mode0_T4 : natural := 2; -- 30ns`
129			`PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240`
130			`);`
131			`port(`
132			`clk : in std_logic; -- master clock`
133			`nReset : in std_logic; -- asynchronous active low reset`
134			`rst : in std_logic; -- synchronous active high reset`
135
136			`-- timing/control register settings`
137			`IORDY_en : in std_logic; -- use IORDY (or not)`
138			`T1 : in unsigned(TWIDTH -1 downto 0); -- T1 time (in clk-ticks)`
139			`T2 : in unsigned(TWIDTH -1 downto 0); -- T2 time (in clk-ticks)`
140			`T4 : in unsigned(TWIDTH -1 downto 0); -- T4 time (in clk-ticks)`
141			`Teoc : in unsigned(TWIDTH -1 downto 0); -- end of cycle time`
142
143			`-- control signals`
144			`go : in std_logic; -- PIO controller selected (strobe signal)`
145			`we : in std_logic; -- write enable signal. '0'=read from device, '1'=write to device`
146
147			`-- return signals`
148			`oe : buffer std_logic; -- output enable signal`
149			`done : out std_logic; -- finished cycle`
150			`dstrb : out std_logic; -- data strobe, latch data (during read)`
151
152			`-- ATA signals`
153			`DIOR, -- IOread signal, active high`
154			`DIOW : buffer std_logic; -- IOwrite signal, active high`
155			`IORDY : in std_logic -- IORDY signal`
156			`);`
157			`end component atahost_pio_tctrl;`
158
159			`--`
160			`-- signals`
161			`--`
162			`signal dPIOreq, PIOgo : std_logic; -- start PIO timing controller`
163			`signal PIOdone : std_logic; -- PIO timing controller done`
164
165			`-- PIO signals`
166			`signal PIOdior, PIOdiow : std_logic;`
167			`signal PIOoe : std_logic;`
168
169			`-- Timing settings`
170			`signal dstrb : std_logic;`
171			`signal T1, T2, T4, Teoc : unsigned(TWIDTH -1 downto 0);`
172			`signal IORDYen : std_logic;`
173
174			`-- synchronized ATA inputs`
175			`signal sIORDY : std_logic;`
176
177			`begin`
178
179			`--`
180			`-- synchronize incoming signals`
181			`--`
182			`synch_incoming: block`
183			`signal cIORDY : std_logic; -- capture IORDY`
184			`signal cINTRQ : std_logic; -- capture INTRQ`
185			`begin`
186			`process(clk)`
187			`begin`
188			`if (clk'event and clk = '1') then`
189			`cIORDY <= IORDY;`
190			`cINTRQ <= INTRQ;`
191
192			`sIORDY <= cIORDY;`
193			`irq <= cINTRQ;`
194			`end if;`
195			`end process;`
196			`end block synch_incoming;`
197
198			`--`
199			`-- generate ATA signals`
200			`--`
201			`gen_ata_sigs: block`
202			`begin`
203			`-- generate registers for ATA signals`
204			`gen_regs: process(clk, nReset)`
205			`begin`
206			`if (nReset = '0') then`
207			`RESETn <= '0';`
208			`DIORn <= '1';`
209			`DIOWn <= '1';`
210			`DA <= (others => '0');`
211			`CS0n <= '1';`
212			`CS1n <= '1';`
213			`DDo <= (others => '0');`
214			`DDoe <= '0';`
215			`elsif (clk'event and clk = '1') then`
216			`if (rst = '1') then`
217			`RESETn <= '0';`
218			`DIORn <= '1';`
219			`DIOWn <= '1';`
220			`DA <= (others => '0');`
221			`CS0n <= '1';`
222			`CS1n <= '1';`
223			`DDo <= (others => '0');`
224			`DDoe <= '0';`
225			`else`
226			`RESETn <= not IDEctrl_rst;`
227			`DA <= PIOa(2 downto 0);`
228			`CS0n <= not (not PIOa(3) and PIOreq); -- CS0 asserted when A(3) = '0'`
229			`CS1n <= not ( PIOa(3) and PIOreq); -- CS1 asserted when A(3) = '1'`
230
231			`DDo <= PIOd;`
232			`DDoe <= PIOoe;`
233			`DIORn <= not PIOdior;`
234			`DIOWn <= not PIOdiow;`
235			`end if;`
236			`end if;`
237			`end process gen_regs;`
238			`end block gen_ata_sigs;`
239
240
241			`--`
242			`--------------------------`
243			`-- PIO transfer control --`
244			`--------------------------`
245			`--`
246			`-- capture ATA data for PIO access`
247			`gen_PIOq: process(clk)`
248			`begin`
249			`if (clk'event and clk = '1') then`
250			`if (dstrb = '1') then`
251			`PIOq <= DDi;`
252			`end if;`
253			`end if;`
254			`end process gen_PIOq;`
255
256			`-- generate PIOgo signal`
257	32	rherveille	`gen_PIOgo: process(clk, nReset)`
258	25	rherveille	`begin`
259	32	rherveille	`if (nReset = '0') then`
260			`dPIOreq <= '0';`
261			`PIOgo <= '0';`
262			`elsif (clk'event and clk = '1') then`
263			`if (rst = '1') then`
264			`dPIOreq <= '0';`
265			`PIOgo <= '0';`
266			`else`
267			`dPIOreq <= PIOreq and not PIOack;`
268			`PIOgo <= (PIOreq and not dPIOreq) and IDEctrl_IDEen;`
269			`end if;`
270			`end`
271	25	rherveille	`end process gen_PIOgo;`
272
273			`-- set Timing signals`
274			`T1 <= PIO_cmdport_T1;`
275			`T2 <= PIO_cmdport_T2;`
276			`T4 <= PIO_cmdport_T4;`
277			`Teoc <= PIO_cmdport_Teoc;`
278			`IORDYen <= PIO_cmdport_IORDYen;`
279
280			`--`
281			`-- hookup timing controller`
282			`--`
283			`PIO_timing_controller: atahost_pio_tctrl`
284			`generic map (`
285			`TWIDTH => TWIDTH,`
286			`PIO_mode0_T1 => PIO_mode0_T1,`
287			`PIO_mode0_T2 => PIO_mode0_T2,`
288			`PIO_mode0_T4 => PIO_mode0_T4,`
289			`PIO_mode0_Teoc => PIO_mode0_Teoc`
290			`)`
291			`port map (`
292			`clk => clk,`
293			`nReset => nReset,`
294			`rst => rst,`
295			`IORDY_en => IORDYen,`
296			`T1 => T1,`
297			`T2 => T2,`
298			`T4 => T4,`
299			`Teoc => Teoc,`
300			`go => PIOgo,`
301			`we => PIOwe,`
302			`oe => PIOoe,`
303			`done => PIOdone,`
304			`dstrb => dstrb,`
305			`DIOR => PIOdior,`
306			`DIOW => PIOdiow,`
307			`IORDY => sIORDY`
308			`);`
309
310			`-- generate acknowledge`
311			`gen_ack: process(clk)`
312			`begin`
313			`if (clk'event and clk = '1') then`
314			`PIOack <= PIOdone or (PIOreq and not IDEctrl_IDEen); -- acknowledge when done or when IDE not enabled (discard request)`
315			`end if;`
316			`end process gen_ack;`
317			`end architecture structural;`
318